1 /* 2 * Copyright (c) 2013-2023, ARM Limited and Contributors. All rights reserved. 3 * 4 * SPDX-License-Identifier: BSD-3-Clause 5 */ 6 7 #include <string.h> 8 9 #include <platform_def.h> 10 11 #include <arch_helpers.h> 12 #include <common/bl_common.h> 13 #include <common/debug.h> 14 #include <drivers/arm/cci.h> 15 #include <lib/utils.h> 16 #include <plat_private.h> 17 18 #ifdef PLAT_RK_CCI_BASE 19 static const int cci_map[] = { 20 PLAT_RK_CCI_CLUSTER0_SL_IFACE_IX, 21 PLAT_RK_CCI_CLUSTER1_SL_IFACE_IX 22 }; 23 #endif 24 25 /****************************************************************************** 26 * Macro generating the code for the function setting up the pagetables as per 27 * the platform memory map & initialize the mmu, for the given exception level 28 ******************************************************************************/ 29 #define DEFINE_CONFIGURE_MMU_EL(_el) \ 30 void plat_configure_mmu_el ## _el(unsigned long total_base, \ 31 unsigned long total_size, \ 32 unsigned long ro_start, \ 33 unsigned long ro_limit, \ 34 unsigned long coh_start, \ 35 unsigned long coh_limit) \ 36 { \ 37 mmap_add_region(total_base, total_base, \ 38 total_size, \ 39 MT_MEMORY | MT_RW | MT_SECURE); \ 40 mmap_add_region(ro_start, ro_start, \ 41 ro_limit - ro_start, \ 42 MT_MEMORY | MT_RO | MT_SECURE); \ 43 if ((coh_limit - coh_start) != 0) \ 44 mmap_add_region(coh_start, coh_start, \ 45 coh_limit - coh_start, \ 46 MT_DEVICE | MT_RW | MT_SECURE); \ 47 mmap_add(plat_rk_mmap); \ 48 rockchip_plat_mmu_el##_el(); \ 49 init_xlat_tables(); \ 50 \ 51 enable_mmu_el ## _el(0); \ 52 } 53 54 /* Define EL3 variants of the function initialising the MMU */ 55 DEFINE_CONFIGURE_MMU_EL(3) 56 57 unsigned int plat_get_syscnt_freq2(void) 58 { 59 return SYS_COUNTER_FREQ_IN_TICKS; 60 } 61 62 void plat_cci_init(void) 63 { 64 #ifdef PLAT_RK_CCI_BASE 65 /* Initialize CCI driver */ 66 cci_init(PLAT_RK_CCI_BASE, cci_map, ARRAY_SIZE(cci_map)); 67 #endif 68 } 69 70 void plat_cci_enable(void) 71 { 72 /* 73 * Enable CCI coherency for this cluster. 74 * No need for locks as no other cpu is active at the moment. 75 */ 76 #ifdef PLAT_RK_CCI_BASE 77 cci_enable_snoop_dvm_reqs(MPIDR_AFFLVL1_VAL(read_mpidr())); 78 #endif 79 } 80 81 void plat_cci_disable(void) 82 { 83 #ifdef PLAT_RK_CCI_BASE 84 cci_disable_snoop_dvm_reqs(MPIDR_AFFLVL1_VAL(read_mpidr())); 85 #endif 86 } 87