1/* 2 * Copyright (c) 2018-2022, ARM Limited and Contributors. All rights reserved. 3 * 4 * SPDX-License-Identifier: BSD-3-Clause 5 */ 6 7#include <arch.h> 8#include <asm_macros.S> 9#include <common/bl_common.h> 10#include <cortex_a77.h> 11#include <cpu_macros.S> 12#include <plat_macros.S> 13#include "wa_cve_2022_23960_bhb_vector.S" 14 15/* Hardware handled coherency */ 16#if HW_ASSISTED_COHERENCY == 0 17#error "Cortex-A77 must be compiled with HW_ASSISTED_COHERENCY enabled" 18#endif 19 20/* 64-bit only core */ 21#if CTX_INCLUDE_AARCH32_REGS == 1 22#error "Cortex-A77 supports only AArch64. Compile with CTX_INCLUDE_AARCH32_REGS=0" 23#endif 24 25#if WORKAROUND_CVE_2022_23960 26 wa_cve_2022_23960_bhb_vector_table CORTEX_A77_BHB_LOOP_COUNT, cortex_a77 27#endif /* WORKAROUND_CVE_2022_23960 */ 28 29 /* -------------------------------------------------- 30 * Errata Workaround for Cortex A77 Errata #1508412. 31 * This applies only to revision <= r1p0 of Cortex A77. 32 * Inputs: 33 * x0: variant[4:7] and revision[0:3] of current cpu. 34 * Shall clobber: x0-x17 35 * -------------------------------------------------- 36 */ 37func errata_a77_1508412_wa 38 /* 39 * Compare x0 against revision r1p0 40 */ 41 mov x17, x30 42 bl check_errata_1508412 43 cbz x0, 3f 44 /* 45 * Compare x0 against revision r0p0 46 */ 47 bl check_errata_1508412_0 48 cbz x0, 1f 49 ldr x0, =0x0 50 msr CORTEX_A77_CPUPSELR_EL3, x0 51 ldr x0, =0x00E8400000 52 msr CORTEX_A77_CPUPOR_EL3, x0 53 ldr x0, =0x00FFE00000 54 msr CORTEX_A77_CPUPMR_EL3, x0 55 ldr x0, =0x4004003FF 56 msr CORTEX_A77_CPUPCR_EL3, x0 57 ldr x0, =0x1 58 msr CORTEX_A77_CPUPSELR_EL3, x0 59 ldr x0, =0x00E8C00040 60 msr CORTEX_A77_CPUPOR_EL3, x0 61 ldr x0, =0x00FFE00040 62 msr CORTEX_A77_CPUPMR_EL3, x0 63 b 2f 641: 65 ldr x0, =0x0 66 msr CORTEX_A77_CPUPSELR_EL3, x0 67 ldr x0, =0x00E8400000 68 msr CORTEX_A77_CPUPOR_EL3, x0 69 ldr x0, =0x00FF600000 70 msr CORTEX_A77_CPUPMR_EL3, x0 71 ldr x0, =0x00E8E00080 72 msr CORTEX_A77_CPUPOR2_EL3, x0 73 ldr x0, =0x00FFE000C0 74 msr CORTEX_A77_CPUPMR2_EL3, x0 752: 76 ldr x0, =0x04004003FF 77 msr CORTEX_A77_CPUPCR_EL3, x0 78 isb 793: 80 ret x17 81endfunc errata_a77_1508412_wa 82 83func check_errata_1508412 84 mov x1, #0x10 85 b cpu_rev_var_ls 86endfunc check_errata_1508412 87 88func check_errata_1508412_0 89 mov x1, #0x0 90 b cpu_rev_var_ls 91endfunc check_errata_1508412_0 92 93 /* -------------------------------------------------- 94 * Errata Workaround for Cortex A77 Errata #1925769. 95 * This applies to revision <= r1p1 of Cortex A77. 96 * Inputs: 97 * x0: variant[4:7] and revision[0:3] of current cpu. 98 * Shall clobber: x0-x17 99 * -------------------------------------------------- 100 */ 101func errata_a77_1925769_wa 102 /* Compare x0 against revision <= r1p1 */ 103 mov x17, x30 104 bl check_errata_1925769 105 cbz x0, 1f 106 107 /* Set bit 8 in ECTLR_EL1 */ 108 mrs x1, CORTEX_A77_CPUECTLR_EL1 109 orr x1, x1, #CORTEX_A77_CPUECTLR_EL1_BIT_8 110 msr CORTEX_A77_CPUECTLR_EL1, x1 111 isb 1121: 113 ret x17 114endfunc errata_a77_1925769_wa 115 116func check_errata_1925769 117 /* Applies to everything <= r1p1 */ 118 mov x1, #0x11 119 b cpu_rev_var_ls 120endfunc check_errata_1925769 121 122 /* -------------------------------------------------- 123 * Errata Workaround for Cortex A77 Errata #1946167. 124 * This applies to revision <= r1p1 of Cortex A77. 125 * Inputs: 126 * x0: variant[4:7] and revision[0:3] of current cpu. 127 * Shall clobber: x0-x17 128 * -------------------------------------------------- 129 */ 130func errata_a77_1946167_wa 131 /* Compare x0 against revision <= r1p1 */ 132 mov x17, x30 133 bl check_errata_1946167 134 cbz x0, 1f 135 136 ldr x0,=0x4 137 msr CORTEX_A77_CPUPSELR_EL3,x0 138 ldr x0,=0x10E3900002 139 msr CORTEX_A77_CPUPOR_EL3,x0 140 ldr x0,=0x10FFF00083 141 msr CORTEX_A77_CPUPMR_EL3,x0 142 ldr x0,=0x2001003FF 143 msr CORTEX_A77_CPUPCR_EL3,x0 144 145 ldr x0,=0x5 146 msr CORTEX_A77_CPUPSELR_EL3,x0 147 ldr x0,=0x10E3800082 148 msr CORTEX_A77_CPUPOR_EL3,x0 149 ldr x0,=0x10FFF00083 150 msr CORTEX_A77_CPUPMR_EL3,x0 151 ldr x0,=0x2001003FF 152 msr CORTEX_A77_CPUPCR_EL3,x0 153 154 ldr x0,=0x6 155 msr CORTEX_A77_CPUPSELR_EL3,x0 156 ldr x0,=0x10E3800200 157 msr CORTEX_A77_CPUPOR_EL3,x0 158 ldr x0,=0x10FFF003E0 159 msr CORTEX_A77_CPUPMR_EL3,x0 160 ldr x0,=0x2001003FF 161 msr CORTEX_A77_CPUPCR_EL3,x0 162 163 isb 1641: 165 ret x17 166endfunc errata_a77_1946167_wa 167 168func check_errata_1946167 169 /* Applies to everything <= r1p1 */ 170 mov x1, #0x11 171 b cpu_rev_var_ls 172endfunc check_errata_1946167 173 174 /* -------------------------------------------------- 175 * Errata Workaround for Cortex A77 Errata #1791578. 176 * This applies to revisions r0p0, r1p0, and r1p1 and is still open. 177 * x0: variant[4:7] and revision[0:3] of current cpu. 178 * Shall clobber: x0-x17 179 * -------------------------------------------------- 180 */ 181func errata_a77_1791578_wa 182 /* Check workaround compatibility. */ 183 mov x17, x30 184 bl check_errata_1791578 185 cbz x0, 1f 186 187 /* Set bit 2 in ACTLR2_EL1 */ 188 mrs x1, CORTEX_A77_ACTLR2_EL1 189 orr x1, x1, #CORTEX_A77_ACTLR2_EL1_BIT_2 190 msr CORTEX_A77_ACTLR2_EL1, x1 191 isb 1921: 193 ret x17 194endfunc errata_a77_1791578_wa 195 196func check_errata_1791578 197 /* Applies to r0p0, r1p0, and r1p1 right now */ 198 mov x1, #0x11 199 b cpu_rev_var_ls 200endfunc check_errata_1791578 201 202func check_errata_cve_2022_23960 203#if WORKAROUND_CVE_2022_23960 204 mov x0, #ERRATA_APPLIES 205#else 206 mov x0, #ERRATA_MISSING 207#endif 208 ret 209endfunc check_errata_cve_2022_23960 210 211 /* ------------------------------------------------- 212 * The CPU Ops reset function for Cortex-A77. 213 * Shall clobber: x0-x19 214 * ------------------------------------------------- 215 */ 216func cortex_a77_reset_func 217 mov x19, x30 218 bl cpu_get_rev_var 219 mov x18, x0 220 221#if ERRATA_A77_1508412 222 mov x0, x18 223 bl errata_a77_1508412_wa 224#endif 225 226#if ERRATA_A77_1925769 227 mov x0, x18 228 bl errata_a77_1925769_wa 229#endif 230 231#if ERRATA_A77_1946167 232 mov x0, x18 233 bl errata_a77_1946167_wa 234#endif 235 236#if ERRATA_A77_1791578 237 mov x0, x18 238 bl errata_a77_1791578_wa 239#endif 240 241#if IMAGE_BL31 && WORKAROUND_CVE_2022_23960 242 /* 243 * The Cortex-A77 generic vectors are overridden to apply errata 244 * mitigation on exception entry from lower ELs. 245 */ 246 adr x0, wa_cve_vbar_cortex_a77 247 msr vbar_el3, x0 248#endif /* IMAGE_BL31 && WORKAROUND_CVE_2022_23960 */ 249 250 isb 251 ret x19 252endfunc cortex_a77_reset_func 253 254 /* --------------------------------------------- 255 * HW will do the cache maintenance while powering down 256 * --------------------------------------------- 257 */ 258func cortex_a77_core_pwr_dwn 259 /* --------------------------------------------- 260 * Enable CPU power down bit in power control register 261 * --------------------------------------------- 262 */ 263 mrs x0, CORTEX_A77_CPUPWRCTLR_EL1 264 orr x0, x0, #CORTEX_A77_CPUPWRCTLR_EL1_CORE_PWRDN_BIT 265 msr CORTEX_A77_CPUPWRCTLR_EL1, x0 266 isb 267 ret 268endfunc cortex_a77_core_pwr_dwn 269 270#if REPORT_ERRATA 271/* 272 * Errata printing function for Cortex-A77. Must follow AAPCS. 273 */ 274func cortex_a77_errata_report 275 stp x8, x30, [sp, #-16]! 276 277 bl cpu_get_rev_var 278 mov x8, x0 279 280 /* 281 * Report all errata. The revision-variant information is passed to 282 * checking functions of each errata. 283 */ 284 report_errata ERRATA_A77_1508412, cortex_a77, 1508412 285 report_errata ERRATA_A77_1925769, cortex_a77, 1925769 286 report_errata ERRATA_A77_1946167, cortex_a77, 1946167 287 report_errata ERRATA_A77_1791578, cortex_a77, 1791578 288 report_errata WORKAROUND_CVE_2022_23960, cortex_a77, cve_2022_23960 289 290 ldp x8, x30, [sp], #16 291 ret 292endfunc cortex_a77_errata_report 293#endif 294 295 296 /* --------------------------------------------- 297 * This function provides Cortex-A77 specific 298 * register information for crash reporting. 299 * It needs to return with x6 pointing to 300 * a list of register names in ascii and 301 * x8 - x15 having values of registers to be 302 * reported. 303 * --------------------------------------------- 304 */ 305.section .rodata.cortex_a77_regs, "aS" 306cortex_a77_regs: /* The ascii list of register names to be reported */ 307 .asciz "cpuectlr_el1", "" 308 309func cortex_a77_cpu_reg_dump 310 adr x6, cortex_a77_regs 311 mrs x8, CORTEX_A77_CPUECTLR_EL1 312 ret 313endfunc cortex_a77_cpu_reg_dump 314 315declare_cpu_ops cortex_a77, CORTEX_A77_MIDR, \ 316 cortex_a77_reset_func, \ 317 cortex_a77_core_pwr_dwn 318