1 /* 2 * Copyright (c) 2015-2020, Renesas Electronics Corporation. All rights reserved. 3 * 4 * SPDX-License-Identifier: BSD-3-Clause 5 */ 6 7 #include <common/debug.h> 8 9 #include "emmc_config.h" 10 #include "emmc_def.h" 11 #include "emmc_hal.h" 12 #include "emmc_registers.h" 13 #include "emmc_std.h" 14 #include "micro_delay.h" 15 16 static void emmc_little_to_big(uint8_t *p, uint32_t value) 17 { 18 if (p == NULL) 19 return; 20 21 p[0] = (uint8_t) (value >> 24); 22 p[1] = (uint8_t) (value >> 16); 23 p[2] = (uint8_t) (value >> 8); 24 p[3] = (uint8_t) value; 25 26 } 27 28 static void emmc_softreset(void) 29 { 30 int32_t loop = 10000; 31 int32_t retry = 1000; 32 33 /* flag clear */ 34 mmc_drv_obj.during_cmd_processing = FALSE; 35 mmc_drv_obj.during_transfer = FALSE; 36 mmc_drv_obj.during_dma_transfer = FALSE; 37 mmc_drv_obj.state_machine_blocking = FALSE; 38 mmc_drv_obj.force_terminate = FALSE; 39 mmc_drv_obj.dma_error_flag = FALSE; 40 41 /* during operation ? */ 42 if ((GETR_32(SD_INFO2) & SD_INFO2_CBSY) == 0) 43 goto reset; 44 45 /* wait CMDSEQ = 0 */ 46 while (loop > 0) { 47 if ((GETR_32(SD_INFO2) & SD_INFO2_CBSY) == 0) 48 break; /* ready */ 49 50 loop--; 51 if ((loop == 0) && (retry > 0)) { 52 rcar_micro_delay(1000U); /* wait 1ms */ 53 loop = 10000; 54 retry--; 55 } 56 } 57 58 reset: 59 /* reset */ 60 SETR_32(SOFT_RST, (GETR_32(SOFT_RST) & (~SOFT_RST_SDRST))); 61 SETR_32(SOFT_RST, (GETR_32(SOFT_RST) | SOFT_RST_SDRST)); 62 63 /* initialize */ 64 SETR_32(SD_INFO1, 0x00000000U); 65 SETR_32(SD_INFO2, SD_INFO2_CLEAR); 66 SETR_32(SD_INFO1_MASK, 0x00000000U); /* all interrupt disable */ 67 SETR_32(SD_INFO2_MASK, SD_INFO2_CLEAR); /* all interrupt disable */ 68 } 69 70 static void emmc_read_response(uint32_t *response) 71 { 72 uint8_t *p; 73 74 if (response == NULL) 75 return; 76 77 /* read response */ 78 if (mmc_drv_obj.response_length != EMMC_MAX_RESPONSE_LENGTH) { 79 *response = GETR_32(SD_RSP10); /* [39:8] */ 80 return; 81 } 82 83 /* CSD or CID */ 84 p = (uint8_t *) (response); 85 emmc_little_to_big(p, ((GETR_32(SD_RSP76) << 8) 86 | (GETR_32(SD_RSP54) >> 24))); /* [127:96] */ 87 emmc_little_to_big(p + 4, ((GETR_32(SD_RSP54) << 8) 88 | (GETR_32(SD_RSP32) >> 24))); /* [95:64] */ 89 emmc_little_to_big(p + 8, ((GETR_32(SD_RSP32) << 8) 90 | (GETR_32(SD_RSP10) >> 24))); /* [63:32] */ 91 emmc_little_to_big(p + 12, (GETR_32(SD_RSP10) << 8)); 92 } 93 94 static EMMC_ERROR_CODE emmc_response_check(uint32_t *response, 95 uint32_t error_mask) 96 { 97 98 HAL_MEMCARD_RESPONSE_TYPE response_type = 99 ((HAL_MEMCARD_RESPONSE_TYPE)mmc_drv_obj.cmd_info.cmd & HAL_MEMCARD_RESPONSE_TYPE_MASK); 100 101 if (response == NULL) 102 return EMMC_ERR_PARAM; 103 104 if (response_type == HAL_MEMCARD_RESPONSE_NONE) 105 return EMMC_SUCCESS; 106 107 108 if (response_type <= HAL_MEMCARD_RESPONSE_R1b) { 109 /* R1 or R1b */ 110 mmc_drv_obj.current_state = 111 (EMMC_R1_STATE) ((*response & EMMC_R1_STATE_MASK) >> 112 EMMC_R1_STATE_SHIFT); 113 if ((*response & error_mask) != 0) { 114 if ((0x80 & *response) != 0) { 115 ERROR("BL2: emmc SWITCH_ERROR\n"); 116 } 117 return EMMC_ERR_CARD_STATUS_BIT; 118 } 119 return EMMC_SUCCESS; 120 } 121 122 if (response_type == HAL_MEMCARD_RESPONSE_R4) { 123 if ((*response & EMMC_R4_STATUS) != 0) 124 return EMMC_ERR_CARD_STATUS_BIT; 125 } 126 127 return EMMC_SUCCESS; 128 } 129 130 static void emmc_WaitCmd2Cmd_8Cycle(void) 131 { 132 uint32_t dataL, wait = 0; 133 134 dataL = GETR_32(SD_CLK_CTRL); 135 dataL &= 0x000000FF; 136 137 switch (dataL) { 138 case 0xFF: 139 case 0x00: 140 case 0x01: 141 case 0x02: 142 case 0x04: 143 case 0x08: 144 case 0x10: 145 case 0x20: 146 wait = 10U; 147 break; 148 case 0x40: 149 wait = 20U; 150 break; 151 case 0x80: 152 wait = 30U; 153 break; 154 } 155 156 rcar_micro_delay(wait); 157 } 158 159 static void cmdErrSdInfo2Log(void) 160 { 161 ERROR("BL2: emmc ERR SD_INFO2 = 0x%x\n", mmc_drv_obj.error_info.info2); 162 } 163 164 static void emmc_data_transfer_dma(void) 165 { 166 mmc_drv_obj.during_dma_transfer = TRUE; 167 mmc_drv_obj.dma_error_flag = FALSE; 168 169 SETR_32(SD_INFO1_MASK, 0x00000000U); 170 SETR_32(SD_INFO2_MASK, (SD_INFO2_ALL_ERR | SD_INFO2_CLEAR)); 171 172 /* DMAC setting */ 173 if (mmc_drv_obj.cmd_info.dir == HAL_MEMCARD_WRITE) { 174 /* transfer complete interrupt enable */ 175 SETR_32(DM_CM_INFO1_MASK, 176 (DM_CM_INFO_MASK_CLEAR | DM_CM_INFO_CH0_ENABLE)); 177 SETR_32(DM_CM_INFO2_MASK, 178 (DM_CM_INFO_MASK_CLEAR | DM_CM_INFO_CH0_ENABLE)); 179 /* BUFF --> FIFO */ 180 SETR_32(DM_CM_DTRAN_MODE, (DM_CM_DTRAN_MODE_CH0 | 181 DM_CM_DTRAN_MODE_BIT_WIDTH)); 182 } else { 183 /* transfer complete interrupt enable */ 184 SETR_32(DM_CM_INFO1_MASK, 185 (DM_CM_INFO_MASK_CLEAR | DM_CM_INFO_CH1_ENABLE)); 186 SETR_32(DM_CM_INFO2_MASK, 187 (DM_CM_INFO_MASK_CLEAR | DM_CM_INFO_CH1_ENABLE)); 188 /* FIFO --> BUFF */ 189 SETR_32(DM_CM_DTRAN_MODE, (DM_CM_DTRAN_MODE_CH1 190 | DM_CM_DTRAN_MODE_BIT_WIDTH)); 191 } 192 SETR_32(DM_DTRAN_ADDR, (((uintptr_t) mmc_drv_obj.buff_address_virtual & 193 DM_DTRAN_ADDR_WRITE_MASK))); 194 195 SETR_32(DM_CM_DTRAN_CTRL, DM_CM_DTRAN_CTRL_START); 196 } 197 198 EMMC_ERROR_CODE emmc_exec_cmd(uint32_t error_mask, uint32_t *response) 199 { 200 EMMC_ERROR_CODE rtn_code = EMMC_SUCCESS; 201 HAL_MEMCARD_RESPONSE_TYPE response_type; 202 HAL_MEMCARD_COMMAND_TYPE cmd_type; 203 EMMC_INT_STATE state; 204 uint32_t err_not_care_flag = FALSE; 205 206 /* parameter check */ 207 if (response == NULL) { 208 emmc_write_error_info(EMMC_FUNCNO_EXEC_CMD, EMMC_ERR_PARAM); 209 return EMMC_ERR_PARAM; 210 } 211 212 /* state check */ 213 if (mmc_drv_obj.clock_enable != TRUE) { 214 emmc_write_error_info(EMMC_FUNCNO_EXEC_CMD, EMMC_ERR_STATE); 215 return EMMC_ERR_STATE; 216 } 217 218 if (mmc_drv_obj.state_machine_blocking == TRUE) { 219 emmc_write_error_info(EMMC_FUNCNO_EXEC_CMD, EMMC_ERR); 220 return EMMC_ERR; 221 } 222 223 state = ESTATE_BEGIN; 224 response_type = 225 ((HAL_MEMCARD_RESPONSE_TYPE)mmc_drv_obj.cmd_info.cmd & 226 HAL_MEMCARD_RESPONSE_TYPE_MASK); 227 cmd_type = 228 ((HAL_MEMCARD_COMMAND_TYPE) mmc_drv_obj.cmd_info.cmd & 229 HAL_MEMCARD_COMMAND_TYPE_MASK); 230 231 /* state machine */ 232 while ((mmc_drv_obj.force_terminate != TRUE) && (state != ESTATE_END)) { 233 /* The interrupt factor flag is observed. */ 234 emmc_interrupt(); 235 236 /* wait interrupt */ 237 if (mmc_drv_obj.state_machine_blocking == TRUE) 238 continue; 239 240 switch (state) { 241 case ESTATE_BEGIN: 242 /* Busy check */ 243 if ((mmc_drv_obj.error_info.info2 & SD_INFO2_CBSY) != 0) { 244 emmc_write_error_info(EMMC_FUNCNO_EXEC_CMD, 245 EMMC_ERR_CARD_BUSY); 246 return EMMC_ERR_CARD_BUSY; 247 } 248 249 /* clear register */ 250 SETR_32(SD_INFO1, 0x00000000U); 251 SETR_32(SD_INFO2, SD_INFO2_CLEAR); 252 SETR_32(SD_INFO1_MASK, SD_INFO1_INFO0); 253 SETR_32(SD_INFO2_MASK, 254 (SD_INFO2_ALL_ERR | SD_INFO2_CLEAR)); 255 256 state = ESTATE_ISSUE_CMD; 257 /* fallthrough */ 258 case ESTATE_ISSUE_CMD: 259 /* ARG */ 260 SETR_32(SD_ARG, mmc_drv_obj.cmd_info.arg); 261 /* issue cmd */ 262 SETR_32(SD_CMD, mmc_drv_obj.cmd_info.hw); 263 /* Set driver flag */ 264 mmc_drv_obj.during_cmd_processing = TRUE; 265 mmc_drv_obj.state_machine_blocking = TRUE; 266 267 if (response_type == HAL_MEMCARD_RESPONSE_NONE) { 268 state = ESTATE_NON_RESP_CMD; 269 } else { 270 state = ESTATE_RCV_RESP; 271 } 272 273 break; 274 275 case ESTATE_NON_RESP_CMD: 276 /* interrupt disable */ 277 SETR_32(SD_INFO1_MASK, 0x00000000U); 278 SETR_32(SD_INFO2_MASK, SD_INFO2_CLEAR); 279 280 /* check interrupt */ 281 if ((mmc_drv_obj.int_event2 & SD_INFO2_ALL_ERR) != 0) { 282 /* error interrupt */ 283 cmdErrSdInfo2Log(); 284 rtn_code = EMMC_ERR_INFO2; 285 state = ESTATE_ERROR; 286 } else if ((mmc_drv_obj.int_event1 & SD_INFO1_INFO0) == 287 0) { 288 /* not receive expected interrupt */ 289 rtn_code = EMMC_ERR_RESPONSE; 290 state = ESTATE_ERROR; 291 } else { 292 emmc_WaitCmd2Cmd_8Cycle(); 293 state = ESTATE_END; 294 } 295 break; 296 297 case ESTATE_RCV_RESP: 298 /* interrupt disable */ 299 SETR_32(SD_INFO1_MASK, 0x00000000U); 300 SETR_32(SD_INFO2_MASK, SD_INFO2_CLEAR); 301 302 /* check interrupt */ 303 if ((mmc_drv_obj.int_event2 & SD_INFO2_ALL_ERR) != 0) { 304 if ((mmc_drv_obj.get_partition_access_flag == 305 TRUE) 306 && ((mmc_drv_obj.int_event2 & SD_INFO2_ERR6) 307 != 0U)) { 308 err_not_care_flag = TRUE; 309 rtn_code = EMMC_ERR_CMD_TIMEOUT; 310 } else { 311 /* error interrupt */ 312 cmdErrSdInfo2Log(); 313 rtn_code = EMMC_ERR_INFO2; 314 } 315 state = ESTATE_ERROR; 316 break; 317 } else if ((mmc_drv_obj.int_event1 & SD_INFO1_INFO0) == 318 0) { 319 /* not receive expected interrupt */ 320 rtn_code = EMMC_ERR_RESPONSE; 321 state = ESTATE_ERROR; 322 break; 323 } 324 325 /* read response */ 326 emmc_read_response(response); 327 328 /* check response */ 329 rtn_code = emmc_response_check(response, error_mask); 330 if (rtn_code != EMMC_SUCCESS) { 331 state = ESTATE_ERROR; 332 break; 333 } 334 335 if (response_type == HAL_MEMCARD_RESPONSE_R1b) { 336 /* R1b */ 337 SETR_32(SD_INFO2_MASK, 338 (SD_INFO2_ALL_ERR | SD_INFO2_CLEAR)); 339 state = ESTATE_RCV_RESPONSE_BUSY; 340 } else { 341 state = ESTATE_CHECK_RESPONSE_COMPLETE; 342 } 343 break; 344 345 case ESTATE_RCV_RESPONSE_BUSY: 346 /* check interrupt */ 347 if ((mmc_drv_obj.int_event2 & SD_INFO2_ALL_ERR) != 0) { 348 /* error interrupt */ 349 cmdErrSdInfo2Log(); 350 rtn_code = EMMC_ERR_INFO2; 351 state = ESTATE_ERROR; 352 break; 353 } 354 /* DAT0 not Busy */ 355 if ((SD_INFO2_DAT0 & mmc_drv_obj.error_info.info2) != 0) { 356 state = ESTATE_CHECK_RESPONSE_COMPLETE; 357 break; 358 } 359 break; 360 361 case ESTATE_CHECK_RESPONSE_COMPLETE: 362 if (cmd_type >= HAL_MEMCARD_COMMAND_TYPE_ADTC_WRITE) { 363 state = ESTATE_DATA_TRANSFER; 364 } else { 365 emmc_WaitCmd2Cmd_8Cycle(); 366 state = ESTATE_END; 367 } 368 break; 369 370 case ESTATE_DATA_TRANSFER: 371 /* ADTC command */ 372 mmc_drv_obj.during_transfer = TRUE; 373 mmc_drv_obj.state_machine_blocking = TRUE; 374 375 if (mmc_drv_obj.transfer_mode == HAL_MEMCARD_DMA) { 376 /* DMA */ 377 emmc_data_transfer_dma(); 378 } else { 379 /* PIO */ 380 /* interrupt enable (FIFO read/write enable) */ 381 if (mmc_drv_obj.cmd_info.dir == 382 HAL_MEMCARD_WRITE) { 383 SETR_32(SD_INFO2_MASK, 384 (SD_INFO2_BWE | SD_INFO2_ALL_ERR 385 | SD_INFO2_CLEAR)); 386 } else { 387 SETR_32(SD_INFO2_MASK, 388 (SD_INFO2_BRE | SD_INFO2_ALL_ERR 389 | SD_INFO2_CLEAR)); 390 } 391 } 392 state = ESTATE_DATA_TRANSFER_COMPLETE; 393 break; 394 395 case ESTATE_DATA_TRANSFER_COMPLETE: 396 /* check interrupt */ 397 if ((mmc_drv_obj.int_event2 & SD_INFO2_ALL_ERR) != 0) { 398 /* error interrupt */ 399 cmdErrSdInfo2Log(); 400 rtn_code = EMMC_ERR_INFO2; 401 state = ESTATE_TRANSFER_ERROR; 402 break; 403 } 404 405 /* DMAC error ? */ 406 if (mmc_drv_obj.dma_error_flag == TRUE) { 407 /* Error occurred in DMAC driver. */ 408 rtn_code = EMMC_ERR_FROM_DMAC_TRANSFER; 409 state = ESTATE_TRANSFER_ERROR; 410 } else if (mmc_drv_obj.during_dma_transfer == TRUE) { 411 /* DMAC not finished. unknown error */ 412 rtn_code = EMMC_ERR; 413 state = ESTATE_TRANSFER_ERROR; 414 } else { 415 SETR_32(SD_INFO1_MASK, SD_INFO1_INFO2); 416 SETR_32(SD_INFO2_MASK, 417 (SD_INFO2_ALL_ERR | SD_INFO2_CLEAR)); 418 419 mmc_drv_obj.state_machine_blocking = TRUE; 420 421 state = ESTATE_ACCESS_END; 422 } 423 break; 424 425 case ESTATE_ACCESS_END: 426 427 /* clear flag */ 428 if (mmc_drv_obj.transfer_mode == HAL_MEMCARD_DMA) { 429 /* W (CC_EXT_MODE, H'0000_1010) SD_BUF DMA transfer disabled */ 430 SETR_32(CC_EXT_MODE, CC_EXT_MODE_CLEAR); 431 SETR_32(SD_STOP, 0x00000000U); 432 mmc_drv_obj.during_dma_transfer = FALSE; 433 } 434 435 SETR_32(SD_INFO1_MASK, 0x00000000U); 436 SETR_32(SD_INFO2_MASK, SD_INFO2_CLEAR); 437 SETR_32(SD_INFO1, 0x00000000U); 438 SETR_32(SD_INFO2, SD_INFO2_CLEAR); 439 440 if ((mmc_drv_obj.int_event1 & SD_INFO1_INFO2) != 0) { 441 emmc_WaitCmd2Cmd_8Cycle(); 442 state = ESTATE_END; 443 } else { 444 state = ESTATE_ERROR; 445 } 446 break; 447 448 case ESTATE_TRANSFER_ERROR: 449 /* The error occurred in the Data transfer. */ 450 if (mmc_drv_obj.transfer_mode == HAL_MEMCARD_DMA) { 451 /* W (CC_EXT_MODE, H'0000_1010) SD_BUF DMA transfer disabled */ 452 SETR_32(CC_EXT_MODE, CC_EXT_MODE_CLEAR); 453 SETR_32(SD_STOP, 0x00000000U); 454 mmc_drv_obj.during_dma_transfer = FALSE; 455 } 456 457 /* fallthrough */ 458 case ESTATE_ERROR: 459 if (err_not_care_flag == TRUE) { 460 mmc_drv_obj.during_cmd_processing = FALSE; 461 } else { 462 emmc_softreset(); 463 emmc_write_error_info(EMMC_FUNCNO_EXEC_CMD, 464 rtn_code); 465 } 466 return rtn_code; 467 468 default: 469 state = ESTATE_END; 470 break; 471 } /* switch (state) */ 472 } /* while ( (mmc_drv_obj.force_terminate != TRUE) && (state != ESTATE_END) ) */ 473 474 /* force terminate */ 475 if (mmc_drv_obj.force_terminate == TRUE) { 476 /* timeout timer is expired. Or, PIO data transfer error. */ 477 /* Timeout occurred in the DMA transfer. */ 478 if (mmc_drv_obj.during_dma_transfer == TRUE) { 479 mmc_drv_obj.during_dma_transfer = FALSE; 480 } 481 ERROR("BL2: emmc exec_cmd:EMMC_ERR_FORCE_TERMINATE\n"); 482 emmc_softreset(); 483 484 return EMMC_ERR_FORCE_TERMINATE; /* error information has already been written. */ 485 } 486 487 /* success */ 488 mmc_drv_obj.during_cmd_processing = FALSE; 489 mmc_drv_obj.during_transfer = FALSE; 490 491 return EMMC_SUCCESS; 492 } 493