1 /* 2 * Copyright (c) 2020-2024, Arm Limited and Contributors. All rights reserved. 3 * 4 * SPDX-License-Identifier: BSD-3-Clause 5 */ 6 7 #include <assert.h> 8 9 #include <libfdt.h> 10 #include <tc_plat.h> 11 12 #include <arch_helpers.h> 13 #include <common/bl_common.h> 14 #include <common/debug.h> 15 #include <drivers/arm/css/css_mhu_doorbell.h> 16 #include <drivers/arm/css/scmi.h> 17 #include <drivers/arm/sbsa.h> 18 #include <lib/fconf/fconf.h> 19 #include <lib/fconf/fconf_dyn_cfg_getter.h> 20 #include <plat/arm/common/plat_arm.h> 21 #include <plat/common/platform.h> 22 23 #ifdef PLATFORM_TEST_TFM_TESTSUITE 24 #include <psa/crypto_platform.h> 25 #include <psa/crypto_types.h> 26 #include <psa/crypto_values.h> 27 #endif /* PLATFORM_TEST_TFM_TESTSUITE */ 28 29 #ifdef PLATFORM_TEST_TFM_TESTSUITE 30 /* 31 * We pretend using an external RNG (through MBEDTLS_PSA_CRYPTO_EXTERNAL_RNG 32 * mbedTLS config option) so we need to provide an implementation of 33 * mbedtls_psa_external_get_random(). Provide a fake one, since we do not 34 * actually use any of external RNG and this function is only needed during 35 * the execution of TF-M testsuite during exporting the public part of the 36 * delegated attestation key. 37 */ 38 psa_status_t mbedtls_psa_external_get_random( 39 mbedtls_psa_external_random_context_t *context, 40 uint8_t *output, size_t output_size, 41 size_t *output_length) 42 { 43 for (size_t i = 0U; i < output_size; i++) { 44 output[i] = (uint8_t)(read_cntpct_el0() & 0xFFU); 45 } 46 47 *output_length = output_size; 48 49 return PSA_SUCCESS; 50 } 51 #endif /* PLATFORM_TEST_TFM_TESTSUITE */ 52 53 #if TARGET_PLATFORM <= 2 54 static scmi_channel_plat_info_t tc_scmi_plat_info = { 55 .scmi_mbx_mem = CSS_SCMI_PAYLOAD_BASE, 56 .db_reg_addr = PLAT_CSS_MHU_BASE + SENDER_REG_SET(0), 57 .db_preserve_mask = 0xfffffffe, 58 .db_modify_mask = 0x1, 59 .ring_doorbell = &mhuv2_ring_doorbell, 60 }; 61 #elif TARGET_PLATFORM == 3 62 static scmi_channel_plat_info_t tc_scmi_plat_info = { 63 .scmi_mbx_mem = CSS_SCMI_PAYLOAD_BASE, 64 .db_reg_addr = PLAT_CSS_MHU_BASE + MHU_V3_SENDER_REG_SET(0), 65 .db_preserve_mask = 0xfffffffe, 66 .db_modify_mask = 0x1, 67 .ring_doorbell = &mhu_ring_doorbell, 68 }; 69 70 static void enable_ns_mcn_pmu(void) 71 { 72 /* 73 * Enable non-secure access to MCN PMU registers 74 */ 75 for (int i = 0; i < MCN_INSTANCES; i++) { 76 uintptr_t mcn_scr = MCN_MICROARCH_BASE_ADDR + MCN_SCR_OFFSET + 77 (i * MCN_ADDRESS_SPACE_SIZE); 78 mmio_setbits_32(mcn_scr, 1 << MCN_SCR_PMU_BIT); 79 } 80 } 81 82 static void set_mcn_slc_alloc_mode(void) 83 { 84 /* 85 * SLC WRALLOCMODE and RDALLOCMODE are configured by default to 86 * 0b01 (always alloc), configure both to 0b10 (use bus signal 87 * attribute from interface). 88 */ 89 for (int i = 0; i < MCN_INSTANCES; i++) { 90 uintptr_t slccfg_ctl_ns = MCN_MPAM_NS_BASE_ADDR + 91 (i * MCN_ADDRESS_SPACE_SIZE) + MPAM_SLCCFG_CTL_OFFSET; 92 uintptr_t slccfg_ctl_s = MCN_MPAM_S_BASE_ADDR + 93 (i * MCN_ADDRESS_SPACE_SIZE) + MPAM_SLCCFG_CTL_OFFSET; 94 95 mmio_clrsetbits_32(slccfg_ctl_ns, 96 (SLC_RDALLOCMODE_MASK | SLC_WRALLOCMODE_MASK), 97 (SLC_ALLOC_BUS_SIGNAL_ATTR << SLC_RDALLOCMODE_SHIFT) | 98 (SLC_ALLOC_BUS_SIGNAL_ATTR << SLC_WRALLOCMODE_SHIFT)); 99 mmio_clrsetbits_32(slccfg_ctl_s, 100 (SLC_RDALLOCMODE_MASK | SLC_WRALLOCMODE_MASK), 101 (SLC_ALLOC_BUS_SIGNAL_ATTR << SLC_RDALLOCMODE_SHIFT) | 102 (SLC_ALLOC_BUS_SIGNAL_ATTR << SLC_WRALLOCMODE_SHIFT)); 103 } 104 } 105 #endif 106 107 void bl31_platform_setup(void) 108 { 109 tc_bl31_common_platform_setup(); 110 #if TARGET_PLATFORM == 3 111 enable_ns_mcn_pmu(); 112 set_mcn_slc_alloc_mode(); 113 #endif 114 } 115 116 scmi_channel_plat_info_t *plat_css_get_scmi_info(unsigned int channel_id __unused) 117 { 118 119 return &tc_scmi_plat_info; 120 121 } 122 123 void bl31_early_platform_setup2(u_register_t arg0, u_register_t arg1, 124 u_register_t arg2, u_register_t arg3) 125 { 126 arm_bl31_early_platform_setup((void *)arg0, arg1, arg2, (void *)arg3); 127 128 /* Fill the properties struct with the info from the config dtb */ 129 fconf_populate("FW_CONFIG", arg1); 130 } 131 132 #ifdef PLATFORM_TESTS 133 static __dead2 void tc_run_platform_tests(void) 134 { 135 int tests_failed; 136 137 printf("\nStarting platform tests...\n"); 138 139 #ifdef PLATFORM_TEST_NV_COUNTERS 140 tests_failed = nv_counter_test(); 141 #elif PLATFORM_TEST_ROTPK 142 tests_failed = rotpk_test(); 143 #elif PLATFORM_TEST_TFM_TESTSUITE 144 tests_failed = run_platform_tests(); 145 #endif 146 147 printf("Platform tests %s.\n", 148 (tests_failed != 0) ? "failed" : "succeeded"); 149 150 /* Suspend booting, no matter the tests outcome. */ 151 printf("Suspend booting...\n"); 152 plat_error_handler(-1); 153 } 154 #endif 155 156 void tc_bl31_common_platform_setup(void) 157 { 158 arm_bl31_platform_setup(); 159 160 #ifdef PLATFORM_TESTS 161 tc_run_platform_tests(); 162 #endif 163 } 164 165 const plat_psci_ops_t *plat_arm_psci_override_pm_ops(plat_psci_ops_t *ops) 166 { 167 return css_scmi_override_pm_ops(ops); 168 } 169 170 void __init bl31_plat_arch_setup(void) 171 { 172 arm_bl31_plat_arch_setup(); 173 174 /* HW_CONFIG was also loaded by BL2 */ 175 const struct dyn_cfg_dtb_info_t *hw_config_info; 176 177 hw_config_info = FCONF_GET_PROPERTY(dyn_cfg, dtb, HW_CONFIG_ID); 178 assert(hw_config_info != NULL); 179 180 fconf_populate("HW_CONFIG", hw_config_info->config_addr); 181 } 182 183 #if defined(SPD_spmd) && (SPMC_AT_EL3 == 0) 184 void tc_bl31_plat_runtime_setup(void) 185 { 186 /* Start secure watchdog timer. */ 187 plat_arm_secure_wdt_start(); 188 189 arm_bl31_plat_runtime_setup(); 190 } 191 192 void bl31_plat_runtime_setup(void) 193 { 194 tc_bl31_plat_runtime_setup(); 195 } 196 197 /* 198 * Platform handler for Group0 secure interrupt. 199 */ 200 int plat_spmd_handle_group0_interrupt(uint32_t intid) 201 { 202 /* Trusted Watchdog timer is the only source of Group0 interrupt now. */ 203 if (intid == SBSA_SECURE_WDOG_INTID) { 204 /* Refresh the timer. */ 205 plat_arm_secure_wdt_refresh(); 206 207 return 0; 208 } 209 210 return -1; 211 } 212 #endif /*defined(SPD_spmd) && (SPMC_AT_EL3 == 0)*/ 213