1 /* 2 * Copyright (c) 2014-2022, Arm Limited and Contributors. All rights reserved. 3 * 4 * SPDX-License-Identifier: BSD-3-Clause 5 */ 6 7 #ifndef PLATFORM_DEF_H 8 #define PLATFORM_DEF_H 9 10 #include <drivers/arm/tzc400.h> 11 #include <lib/utils_def.h> 12 #include <plat/arm/board/common/v2m_def.h> 13 #include <plat/arm/common/arm_def.h> 14 #include <plat/arm/common/arm_spm_def.h> 15 #include <plat/common/common_def.h> 16 17 #include "../fvp_def.h" 18 19 /* Required platform porting definitions */ 20 #define PLATFORM_CORE_COUNT (U(FVP_CLUSTER_COUNT) * \ 21 U(FVP_MAX_CPUS_PER_CLUSTER) * \ 22 U(FVP_MAX_PE_PER_CPU)) 23 24 #define PLAT_NUM_PWR_DOMAINS (U(FVP_CLUSTER_COUNT) + \ 25 PLATFORM_CORE_COUNT + U(1)) 26 27 #define PLAT_MAX_PWR_LVL ARM_PWR_LVL2 28 29 /* 30 * Other platform porting definitions are provided by included headers 31 */ 32 33 /* 34 * Required ARM standard platform porting definitions 35 */ 36 #define PLAT_ARM_CLUSTER_COUNT U(FVP_CLUSTER_COUNT) 37 38 #define PLAT_ARM_TRUSTED_SRAM_SIZE UL(0x00040000) /* 256 KB */ 39 40 #define PLAT_ARM_TRUSTED_ROM_BASE UL(0x00000000) 41 #define PLAT_ARM_TRUSTED_ROM_SIZE UL(0x04000000) /* 64 MB */ 42 43 #define PLAT_ARM_TRUSTED_DRAM_BASE UL(0x06000000) 44 #define PLAT_ARM_TRUSTED_DRAM_SIZE UL(0x02000000) /* 32 MB */ 45 46 #if ENABLE_RME 47 #define PLAT_ARM_RMM_BASE (RMM_BASE) 48 #define PLAT_ARM_RMM_SIZE (RMM_LIMIT - RMM_BASE) 49 #endif 50 51 /* 52 * Max size of SPMC is 2MB for fvp. With SPMD enabled this value corresponds to 53 * max size of BL32 image. 54 */ 55 #if defined(SPD_spmd) 56 #define PLAT_ARM_SPMC_BASE PLAT_ARM_TRUSTED_DRAM_BASE 57 #define PLAT_ARM_SPMC_SIZE UL(0x200000) /* 2 MB */ 58 #endif 59 60 /* virtual address used by dynamic mem_protect for chunk_base */ 61 #define PLAT_ARM_MEM_PROTEC_VA_FRAME UL(0xc0000000) 62 63 /* No SCP in FVP */ 64 #define PLAT_ARM_SCP_TZC_DRAM1_SIZE UL(0x0) 65 66 #define PLAT_ARM_DRAM2_BASE ULL(0x880000000) /* 36-bit range */ 67 #define PLAT_ARM_DRAM2_SIZE ULL(0x780000000) /* 30 GB */ 68 69 #define FVP_DRAM3_BASE ULL(0x8800000000) /* 40-bit range */ 70 #define FVP_DRAM3_SIZE ULL(0x7800000000) /* 480 GB */ 71 #define FVP_DRAM3_END (FVP_DRAM3_BASE + FVP_DRAM3_SIZE - 1U) 72 73 #define FVP_DRAM4_BASE ULL(0x88000000000) /* 44-bit range */ 74 #define FVP_DRAM4_SIZE ULL(0x78000000000) /* 7.5 TB */ 75 #define FVP_DRAM4_END (FVP_DRAM4_BASE + FVP_DRAM4_SIZE - 1U) 76 77 #define FVP_DRAM5_BASE ULL(0x880000000000) /* 48-bit range */ 78 #define FVP_DRAM5_SIZE ULL(0x780000000000) /* 120 TB */ 79 #define FVP_DRAM5_END (FVP_DRAM5_BASE + FVP_DRAM5_SIZE - 1U) 80 81 #define FVP_DRAM6_BASE ULL(0x8800000000000) /* 52-bit range */ 82 #define FVP_DRAM6_SIZE ULL(0x7800000000000) /* 1920 TB */ 83 #define FVP_DRAM6_END (FVP_DRAM6_BASE + FVP_DRAM6_SIZE - 1U) 84 85 /* Range of kernel DTB load address */ 86 #define FVP_DTB_DRAM_MAP_START ULL(0x82000000) 87 #define FVP_DTB_DRAM_MAP_SIZE ULL(0x02000000) /* 32 MB */ 88 89 #define ARM_DTB_DRAM_NS MAP_REGION_FLAT( \ 90 FVP_DTB_DRAM_MAP_START, \ 91 FVP_DTB_DRAM_MAP_SIZE, \ 92 MT_MEMORY | MT_RO | MT_NS) 93 /* 94 * Load address of BL33 for this platform port 95 */ 96 #define PLAT_ARM_NS_IMAGE_BASE (ARM_DRAM1_BASE + UL(0x8000000)) 97 98 /* 99 * PLAT_ARM_MMAP_ENTRIES depends on the number of entries in the 100 * plat_arm_mmap array defined for each BL stage. 101 */ 102 #if defined(IMAGE_BL31) 103 # if SPM_MM 104 # define PLAT_ARM_MMAP_ENTRIES 10 105 # if ENABLE_RME 106 # define MAX_XLAT_TABLES 10 107 # else 108 # define MAX_XLAT_TABLES 9 109 # endif 110 # define PLAT_SP_IMAGE_MMAP_REGIONS 30 111 # define PLAT_SP_IMAGE_MAX_XLAT_TABLES 10 112 # else 113 # define PLAT_ARM_MMAP_ENTRIES 9 114 # if USE_DEBUGFS 115 # if ENABLE_RME 116 # define MAX_XLAT_TABLES 9 117 # else 118 # define MAX_XLAT_TABLES 8 119 # endif 120 # else 121 # if ENABLE_RME 122 # define MAX_XLAT_TABLES 8 123 # else 124 # define MAX_XLAT_TABLES 7 125 # endif 126 # endif 127 # endif 128 #elif defined(IMAGE_BL32) 129 # define PLAT_ARM_MMAP_ENTRIES 9 130 # define MAX_XLAT_TABLES 6 131 #elif !USE_ROMLIB 132 # define PLAT_ARM_MMAP_ENTRIES 11 133 # define MAX_XLAT_TABLES 5 134 #else 135 # define PLAT_ARM_MMAP_ENTRIES 12 136 # define MAX_XLAT_TABLES 6 137 #endif 138 139 /* 140 * PLAT_ARM_MAX_BL1_RW_SIZE is calculated using the current BL1 RW debug size 141 * plus a little space for growth. 142 */ 143 #define PLAT_ARM_MAX_BL1_RW_SIZE UL(0xB000) 144 145 /* 146 * PLAT_ARM_MAX_ROMLIB_RW_SIZE is define to use a full page 147 */ 148 149 #if USE_ROMLIB 150 #define PLAT_ARM_MAX_ROMLIB_RW_SIZE UL(0x1000) 151 #define PLAT_ARM_MAX_ROMLIB_RO_SIZE UL(0xe000) 152 #define FVP_BL2_ROMLIB_OPTIMIZATION UL(0x5000) 153 #else 154 #define PLAT_ARM_MAX_ROMLIB_RW_SIZE UL(0) 155 #define PLAT_ARM_MAX_ROMLIB_RO_SIZE UL(0) 156 #define FVP_BL2_ROMLIB_OPTIMIZATION UL(0) 157 #endif 158 159 /* 160 * PLAT_ARM_MAX_BL2_SIZE is calculated using the current BL2 debug size plus a 161 * little space for growth. 162 */ 163 #if TRUSTED_BOARD_BOOT && COT_DESC_IN_DTB 164 # define PLAT_ARM_MAX_BL2_SIZE (UL(0x1E000) - FVP_BL2_ROMLIB_OPTIMIZATION) 165 #elif CRYPTO_SUPPORT 166 # define PLAT_ARM_MAX_BL2_SIZE (UL(0x1D000) - FVP_BL2_ROMLIB_OPTIMIZATION) 167 #else 168 # define PLAT_ARM_MAX_BL2_SIZE (UL(0x13000) - FVP_BL2_ROMLIB_OPTIMIZATION) 169 #endif 170 171 #if RESET_TO_BL31 172 /* Size of Trusted SRAM - the first 4KB of shared memory - GPT L0 Tables */ 173 #define PLAT_ARM_MAX_BL31_SIZE (PLAT_ARM_TRUSTED_SRAM_SIZE - \ 174 ARM_SHARED_RAM_SIZE - \ 175 ARM_L0_GPT_SIZE) 176 #else 177 /* 178 * Since BL31 NOBITS overlays BL2 and BL1-RW, PLAT_ARM_MAX_BL31_SIZE is 179 * calculated using the current BL31 PROGBITS debug size plus the sizes of 180 * BL2 and BL1-RW 181 */ 182 #define PLAT_ARM_MAX_BL31_SIZE (UL(0x3D000) - ARM_L0_GPT_SIZE) 183 #endif /* RESET_TO_BL31 */ 184 185 #ifndef __aarch64__ 186 #if RESET_TO_SP_MIN 187 /* Size of Trusted SRAM - the first 4KB of shared memory */ 188 #define PLAT_ARM_MAX_BL32_SIZE (PLAT_ARM_TRUSTED_SRAM_SIZE - \ 189 ARM_SHARED_RAM_SIZE) 190 #else 191 /* 192 * Since BL32 NOBITS overlays BL2 and BL1-RW, PLAT_ARM_MAX_BL32_SIZE is 193 * calculated using the current SP_MIN PROGBITS debug size plus the sizes of 194 * BL2 and BL1-RW 195 */ 196 # define PLAT_ARM_MAX_BL32_SIZE UL(0x3B000) 197 #endif /* RESET_TO_SP_MIN */ 198 #endif 199 200 /* 201 * Size of cacheable stacks 202 */ 203 #if defined(IMAGE_BL1) 204 # if CRYPTO_SUPPORT 205 # define PLATFORM_STACK_SIZE UL(0x1000) 206 # else 207 # define PLATFORM_STACK_SIZE UL(0x500) 208 # endif /* CRYPTO_SUPPORT */ 209 #elif defined(IMAGE_BL2) 210 # if CRYPTO_SUPPORT 211 # define PLATFORM_STACK_SIZE UL(0x1000) 212 # else 213 # define PLATFORM_STACK_SIZE UL(0x600) 214 # endif /* CRYPTO_SUPPORT */ 215 #elif defined(IMAGE_BL2U) 216 # define PLATFORM_STACK_SIZE UL(0x400) 217 #elif defined(IMAGE_BL31) 218 # define PLATFORM_STACK_SIZE UL(0x800) 219 #elif defined(IMAGE_BL32) 220 # define PLATFORM_STACK_SIZE UL(0x440) 221 #elif defined(IMAGE_RMM) 222 # define PLATFORM_STACK_SIZE UL(0x440) 223 #endif 224 225 #define MAX_IO_DEVICES 3 226 #define MAX_IO_HANDLES 4 227 228 /* Reserve the last block of flash for PSCI MEM PROTECT flag */ 229 #define PLAT_ARM_FLASH_IMAGE_BASE V2M_FLASH0_BASE 230 #define PLAT_ARM_FLASH_IMAGE_MAX_SIZE (V2M_FLASH0_SIZE - V2M_FLASH_BLOCK_SIZE) 231 232 #if ARM_GPT_SUPPORT 233 /* 234 * Offset of the FIP in the GPT image. BL1 component uses this option 235 * as it does not load the partition table to get the FIP base 236 * address. At sector 34 by default (i.e. after reserved sectors 0-33) 237 * Offset = 34 * 512(sector size) = 17408 i.e. 0x4400 238 */ 239 #define PLAT_ARM_FIP_OFFSET_IN_GPT 0x4400 240 #endif /* ARM_GPT_SUPPORT */ 241 242 #define PLAT_ARM_NVM_BASE V2M_FLASH0_BASE 243 #define PLAT_ARM_NVM_SIZE (V2M_FLASH0_SIZE - V2M_FLASH_BLOCK_SIZE) 244 245 /* 246 * PL011 related constants 247 */ 248 #define PLAT_ARM_BOOT_UART_BASE V2M_IOFPGA_UART0_BASE 249 #define PLAT_ARM_BOOT_UART_CLK_IN_HZ V2M_IOFPGA_UART0_CLK_IN_HZ 250 251 #define PLAT_ARM_RUN_UART_BASE V2M_IOFPGA_UART1_BASE 252 #define PLAT_ARM_RUN_UART_CLK_IN_HZ V2M_IOFPGA_UART1_CLK_IN_HZ 253 254 #define PLAT_ARM_CRASH_UART_BASE PLAT_ARM_RUN_UART_BASE 255 #define PLAT_ARM_CRASH_UART_CLK_IN_HZ PLAT_ARM_RUN_UART_CLK_IN_HZ 256 257 #define PLAT_ARM_TSP_UART_BASE V2M_IOFPGA_UART2_BASE 258 #define PLAT_ARM_TSP_UART_CLK_IN_HZ V2M_IOFPGA_UART2_CLK_IN_HZ 259 260 #define PLAT_ARM_TRP_UART_BASE V2M_IOFPGA_UART3_BASE 261 #define PLAT_ARM_TRP_UART_CLK_IN_HZ V2M_IOFPGA_UART3_CLK_IN_HZ 262 263 #define PLAT_FVP_SMMUV3_BASE UL(0x2b400000) 264 265 /* CCI related constants */ 266 #define PLAT_FVP_CCI400_BASE UL(0x2c090000) 267 #define PLAT_FVP_CCI400_CLUS0_SL_PORT 3 268 #define PLAT_FVP_CCI400_CLUS1_SL_PORT 4 269 270 /* CCI-500/CCI-550 on Base platform */ 271 #define PLAT_FVP_CCI5XX_BASE UL(0x2a000000) 272 #define PLAT_FVP_CCI5XX_CLUS0_SL_PORT 5 273 #define PLAT_FVP_CCI5XX_CLUS1_SL_PORT 6 274 275 /* CCN related constants. Only CCN 502 is currently supported */ 276 #define PLAT_ARM_CCN_BASE UL(0x2e000000) 277 #define PLAT_ARM_CLUSTER_TO_CCN_ID_MAP 1, 5, 7, 11 278 279 /* System timer related constants */ 280 #define PLAT_ARM_NSTIMER_FRAME_ID U(1) 281 282 /* Mailbox base address */ 283 #define PLAT_ARM_TRUSTED_MAILBOX_BASE ARM_TRUSTED_SRAM_BASE 284 285 286 /* TrustZone controller related constants 287 * 288 * Currently only filters 0 and 2 are connected on Base FVP. 289 * Filter 0 : CPU clusters (no access to DRAM by default) 290 * Filter 1 : not connected 291 * Filter 2 : LCDs (access to VRAM allowed by default) 292 * Filter 3 : not connected 293 * Programming unconnected filters will have no effect at the 294 * moment. These filter could, however, be connected in future. 295 * So care should be taken not to configure the unused filters. 296 * 297 * Allow only non-secure access to all DRAM to supported devices. 298 * Give access to the CPUs and Virtio. Some devices 299 * would normally use the default ID so allow that too. 300 */ 301 #define PLAT_ARM_TZC_BASE UL(0x2a4a0000) 302 #define PLAT_ARM_TZC_FILTERS TZC_400_REGION_ATTR_FILTER_BIT(0) 303 304 #define PLAT_ARM_TZC_NS_DEV_ACCESS ( \ 305 TZC_REGION_ACCESS_RDWR(FVP_NSAID_DEFAULT) | \ 306 TZC_REGION_ACCESS_RDWR(FVP_NSAID_PCI) | \ 307 TZC_REGION_ACCESS_RDWR(FVP_NSAID_AP) | \ 308 TZC_REGION_ACCESS_RDWR(FVP_NSAID_VIRTIO) | \ 309 TZC_REGION_ACCESS_RDWR(FVP_NSAID_VIRTIO_OLD)) 310 311 /* 312 * GIC related constants to cater for both GICv2 and GICv3 instances of an 313 * FVP. They could be overridden at runtime in case the FVP implements the 314 * legacy VE memory map. 315 */ 316 #define PLAT_ARM_GICD_BASE BASE_GICD_BASE 317 #define PLAT_ARM_GICR_BASE BASE_GICR_BASE 318 #define PLAT_ARM_GICC_BASE BASE_GICC_BASE 319 320 /* 321 * Define a list of Group 1 Secure and Group 0 interrupts as per GICv3 322 * terminology. On a GICv2 system or mode, the lists will be merged and treated 323 * as Group 0 interrupts. 324 */ 325 #define PLAT_ARM_G1S_IRQ_PROPS(grp) \ 326 ARM_G1S_IRQ_PROPS(grp), \ 327 INTR_PROP_DESC(FVP_IRQ_TZ_WDOG, GIC_HIGHEST_SEC_PRIORITY, (grp), \ 328 GIC_INTR_CFG_LEVEL), \ 329 INTR_PROP_DESC(FVP_IRQ_SEC_SYS_TIMER, GIC_HIGHEST_SEC_PRIORITY, (grp), \ 330 GIC_INTR_CFG_LEVEL) 331 332 #define PLAT_ARM_G0_IRQ_PROPS(grp) ARM_G0_IRQ_PROPS(grp) 333 334 #if SDEI_IN_FCONF 335 #define PLAT_SDEI_DP_EVENT_MAX_CNT ARM_SDEI_DP_EVENT_MAX_CNT 336 #define PLAT_SDEI_DS_EVENT_MAX_CNT ARM_SDEI_DS_EVENT_MAX_CNT 337 #else 338 #define PLAT_ARM_PRIVATE_SDEI_EVENTS ARM_SDEI_PRIVATE_EVENTS 339 #define PLAT_ARM_SHARED_SDEI_EVENTS ARM_SDEI_SHARED_EVENTS 340 #endif 341 342 #define PLAT_ARM_SP_IMAGE_STACK_BASE (PLAT_SP_IMAGE_NS_BUF_BASE + \ 343 PLAT_SP_IMAGE_NS_BUF_SIZE) 344 345 #define PLAT_SP_PRI PLAT_RAS_PRI 346 347 /* 348 * Physical and virtual address space limits for MMU in AARCH64 & AARCH32 modes 349 */ 350 #ifdef __aarch64__ 351 #define PLAT_PHY_ADDR_SPACE_SIZE (1ULL << 36) 352 #define PLAT_VIRT_ADDR_SPACE_SIZE (1ULL << 36) 353 #else 354 #define PLAT_PHY_ADDR_SPACE_SIZE (1ULL << 32) 355 #define PLAT_VIRT_ADDR_SPACE_SIZE (1ULL << 32) 356 #endif 357 358 /* 359 * Maximum size of Event Log buffer used in Measured Boot Event Log driver 360 */ 361 #define PLAT_ARM_EVENT_LOG_MAX_SIZE UL(0x400) 362 363 #endif /* PLATFORM_DEF_H */ 364