1// SPDX-License-Identifier: (GPL-2.0+ OR BSD-3-Clause) 2/* 3 * Copyright (c) 2017-2022, STMicroelectronics - All Rights Reserved 4 * Author: Ludovic Barre <ludovic.barre@st.com> for STMicroelectronics. 5 */ 6#include <dt-bindings/interrupt-controller/arm-gic.h> 7#include <dt-bindings/clock/stm32mp1-clks.h> 8#include <dt-bindings/reset/stm32mp1-resets.h> 9 10/ { 11 #address-cells = <1>; 12 #size-cells = <1>; 13 14 cpus { 15 #address-cells = <1>; 16 #size-cells = <0>; 17 18 cpu0: cpu@0 { 19 compatible = "arm,cortex-a7"; 20 device_type = "cpu"; 21 reg = <0>; 22 nvmem-cells = <&part_number_otp>; 23 nvmem-cell-names = "part_number"; 24 }; 25 }; 26 27 nvmem_layout: nvmem_layout@0 { 28 compatible = "st,stm32-nvmem-layout"; 29 30 nvmem-cells = <&cfg0_otp>, 31 <&part_number_otp>, 32 <&monotonic_otp>, 33 <&nand_otp>, 34 <&uid_otp>, 35 <&package_otp>, 36 <&hw2_otp>; 37 38 nvmem-cell-names = "cfg0_otp", 39 "part_number_otp", 40 "monotonic_otp", 41 "nand_otp", 42 "uid_otp", 43 "package_otp", 44 "hw2_otp"; 45 }; 46 47 psci { 48 compatible = "arm,psci-1.0"; 49 method = "smc"; 50 }; 51 52 intc: interrupt-controller@a0021000 { 53 compatible = "arm,cortex-a7-gic"; 54 #interrupt-cells = <3>; 55 interrupt-controller; 56 reg = <0xa0021000 0x1000>, 57 <0xa0022000 0x2000>; 58 }; 59 60 clocks { 61 clk_hse: clk-hse { 62 #clock-cells = <0>; 63 compatible = "fixed-clock"; 64 clock-frequency = <24000000>; 65 }; 66 67 clk_hsi: clk-hsi { 68 #clock-cells = <0>; 69 compatible = "fixed-clock"; 70 clock-frequency = <64000000>; 71 }; 72 73 clk_lse: clk-lse { 74 #clock-cells = <0>; 75 compatible = "fixed-clock"; 76 clock-frequency = <32768>; 77 }; 78 79 clk_lsi: clk-lsi { 80 #clock-cells = <0>; 81 compatible = "fixed-clock"; 82 clock-frequency = <32000>; 83 }; 84 85 clk_csi: clk-csi { 86 #clock-cells = <0>; 87 compatible = "fixed-clock"; 88 clock-frequency = <4000000>; 89 }; 90 }; 91 92 soc { 93 compatible = "simple-bus"; 94 #address-cells = <1>; 95 #size-cells = <1>; 96 interrupt-parent = <&intc>; 97 ranges; 98 99 timers12: timer@40006000 { 100 #address-cells = <1>; 101 #size-cells = <0>; 102 compatible = "st,stm32-timers"; 103 reg = <0x40006000 0x400>; 104 clocks = <&rcc TIM12_K>; 105 clock-names = "int"; 106 status = "disabled"; 107 }; 108 109 usart2: serial@4000e000 { 110 compatible = "st,stm32h7-uart"; 111 reg = <0x4000e000 0x400>; 112 interrupts-extended = <&exti 27 IRQ_TYPE_LEVEL_HIGH>; 113 clocks = <&rcc USART2_K>; 114 resets = <&rcc USART2_R>; 115 status = "disabled"; 116 }; 117 118 usart3: serial@4000f000 { 119 compatible = "st,stm32h7-uart"; 120 reg = <0x4000f000 0x400>; 121 interrupts-extended = <&exti 28 IRQ_TYPE_LEVEL_HIGH>; 122 clocks = <&rcc USART3_K>; 123 resets = <&rcc USART3_R>; 124 status = "disabled"; 125 }; 126 127 uart4: serial@40010000 { 128 compatible = "st,stm32h7-uart"; 129 reg = <0x40010000 0x400>; 130 interrupts-extended = <&exti 30 IRQ_TYPE_LEVEL_HIGH>; 131 clocks = <&rcc UART4_K>; 132 resets = <&rcc UART4_R>; 133 wakeup-source; 134 status = "disabled"; 135 }; 136 137 uart5: serial@40011000 { 138 compatible = "st,stm32h7-uart"; 139 reg = <0x40011000 0x400>; 140 interrupts-extended = <&exti 31 IRQ_TYPE_LEVEL_HIGH>; 141 clocks = <&rcc UART5_K>; 142 resets = <&rcc UART5_R>; 143 status = "disabled"; 144 }; 145 146 i2c2: i2c@40013000 { 147 compatible = "st,stm32mp15-i2c"; 148 reg = <0x40013000 0x400>; 149 interrupt-names = "event", "error"; 150 interrupts = <&exti 22 IRQ_TYPE_LEVEL_HIGH>, 151 <&intc GIC_SPI 34 IRQ_TYPE_LEVEL_HIGH>; 152 clocks = <&rcc I2C2_K>; 153 resets = <&rcc I2C2_R>; 154 #address-cells = <1>; 155 #size-cells = <0>; 156 st,syscfg-fmp = <&syscfg 0x4 0x2>; 157 wakeup-source; 158 status = "disabled"; 159 }; 160 161 uart7: serial@40018000 { 162 compatible = "st,stm32h7-uart"; 163 reg = <0x40018000 0x400>; 164 interrupts-extended = <&exti 32 IRQ_TYPE_LEVEL_HIGH>; 165 clocks = <&rcc UART7_K>; 166 resets = <&rcc UART7_R>; 167 status = "disabled"; 168 }; 169 170 uart8: serial@40019000 { 171 compatible = "st,stm32h7-uart"; 172 reg = <0x40019000 0x400>; 173 interrupts-extended = <&exti 33 IRQ_TYPE_LEVEL_HIGH>; 174 clocks = <&rcc UART8_K>; 175 resets = <&rcc UART8_R>; 176 status = "disabled"; 177 }; 178 179 usart6: serial@44003000 { 180 compatible = "st,stm32h7-uart"; 181 reg = <0x44003000 0x400>; 182 interrupts-extended = <&exti 29 IRQ_TYPE_LEVEL_HIGH>; 183 clocks = <&rcc USART6_K>; 184 resets = <&rcc USART6_R>; 185 status = "disabled"; 186 }; 187 188 timers15: timer@44006000 { 189 #address-cells = <1>; 190 #size-cells = <0>; 191 compatible = "st,stm32-timers"; 192 reg = <0x44006000 0x400>; 193 clocks = <&rcc TIM15_K>; 194 clock-names = "int"; 195 status = "disabled"; 196 }; 197 198 usbotg_hs: usb-otg@49000000 { 199 compatible = "st,stm32mp15-hsotg", "snps,dwc2"; 200 reg = <0x49000000 0x10000>; 201 clocks = <&rcc USBO_K>; 202 clock-names = "otg"; 203 resets = <&rcc USBO_R>; 204 reset-names = "dwc2"; 205 interrupts-extended = <&exti 44 IRQ_TYPE_LEVEL_HIGH>; 206 g-rx-fifo-size = <512>; 207 g-np-tx-fifo-size = <32>; 208 g-tx-fifo-size = <256 16 16 16 16 16 16 16>; 209 dr_mode = "otg"; 210 usb33d-supply = <&usb33>; 211 status = "disabled"; 212 }; 213 214 rcc: rcc@50000000 { 215 compatible = "st,stm32mp1-rcc", "syscon"; 216 reg = <0x50000000 0x1000>; 217 #address-cells = <1>; 218 #size-cells = <0>; 219 #clock-cells = <1>; 220 #reset-cells = <1>; 221 interrupts = <GIC_SPI 5 IRQ_TYPE_LEVEL_HIGH>; 222 secure-interrupts = <GIC_SPI 145 IRQ_TYPE_LEVEL_HIGH>; 223 secure-interrupt-names = "wakeup"; 224 }; 225 226 pwr_regulators: pwr@50001000 { 227 compatible = "st,stm32mp1,pwr-reg"; 228 reg = <0x50001000 0x10>; 229 st,tzcr = <&rcc 0x0 0x1>; 230 231 reg11: reg11 { 232 regulator-name = "reg11"; 233 regulator-min-microvolt = <1100000>; 234 regulator-max-microvolt = <1100000>; 235 }; 236 237 reg18: reg18 { 238 regulator-name = "reg18"; 239 regulator-min-microvolt = <1800000>; 240 regulator-max-microvolt = <1800000>; 241 }; 242 243 usb33: usb33 { 244 regulator-name = "usb33"; 245 regulator-min-microvolt = <3300000>; 246 regulator-max-microvolt = <3300000>; 247 }; 248 }; 249 250 pwr_mcu: pwr_mcu@50001014 { 251 compatible = "st,stm32mp151-pwr-mcu", "syscon"; 252 reg = <0x50001014 0x4>; 253 }; 254 255 pwr_irq: pwr@50001020 { 256 compatible = "st,stm32mp1-pwr"; 257 reg = <0x50001020 0x100>; 258 interrupts = <GIC_SPI 149 IRQ_TYPE_LEVEL_HIGH>; 259 interrupt-controller; 260 #interrupt-cells = <3>; 261 }; 262 263 exti: interrupt-controller@5000d000 { 264 compatible = "st,stm32mp1-exti", "syscon"; 265 interrupt-controller; 266 #interrupt-cells = <2>; 267 reg = <0x5000d000 0x400>; 268 269 /* exti_pwr is an extra interrupt controller used for 270 * EXTI 55 to 60. It's mapped on pwr interrupt 271 * controller. 272 */ 273 exti_pwr: exti-pwr { 274 interrupt-controller; 275 #interrupt-cells = <2>; 276 interrupt-parent = <&pwr_irq>; 277 st,irq-number = <6>; 278 }; 279 }; 280 281 syscfg: syscon@50020000 { 282 compatible = "st,stm32mp157-syscfg", "syscon"; 283 reg = <0x50020000 0x400>; 284 clocks = <&rcc SYSCFG>; 285 }; 286 287 hash1: hash@54002000 { 288 compatible = "st,stm32f756-hash"; 289 reg = <0x54002000 0x400>; 290 interrupts = <GIC_SPI 80 IRQ_TYPE_LEVEL_HIGH>; 291 clocks = <&rcc HASH1>; 292 resets = <&rcc HASH1_R>; 293 status = "disabled"; 294 }; 295 296 rng1: rng@54003000 { 297 compatible = "st,stm32-rng"; 298 reg = <0x54003000 0x400>; 299 clocks = <&rcc RNG1_K>; 300 resets = <&rcc RNG1_R>; 301 status = "disabled"; 302 }; 303 304 fmc: memory-controller@58002000 { 305 #address-cells = <2>; 306 #size-cells = <1>; 307 compatible = "st,stm32mp1-fmc2-ebi"; 308 reg = <0x58002000 0x1000>; 309 clocks = <&rcc FMC_K>; 310 resets = <&rcc FMC_R>; 311 status = "disabled"; 312 313 ranges = <0 0 0x60000000 0x04000000>, /* EBI CS 1 */ 314 <1 0 0x64000000 0x04000000>, /* EBI CS 2 */ 315 <2 0 0x68000000 0x04000000>, /* EBI CS 3 */ 316 <3 0 0x6c000000 0x04000000>, /* EBI CS 4 */ 317 <4 0 0x80000000 0x10000000>; /* NAND */ 318 319 nand-controller@4,0 { 320 #address-cells = <1>; 321 #size-cells = <0>; 322 compatible = "st,stm32mp1-fmc2-nfc"; 323 reg = <4 0x00000000 0x1000>, 324 <4 0x08010000 0x1000>, 325 <4 0x08020000 0x1000>, 326 <4 0x01000000 0x1000>, 327 <4 0x09010000 0x1000>, 328 <4 0x09020000 0x1000>; 329 interrupts = <GIC_SPI 48 IRQ_TYPE_LEVEL_HIGH>; 330 status = "disabled"; 331 }; 332 }; 333 334 qspi: spi@58003000 { 335 compatible = "st,stm32f469-qspi"; 336 reg = <0x58003000 0x1000>, <0x70000000 0x10000000>; 337 reg-names = "qspi", "qspi_mm"; 338 interrupts = <GIC_SPI 92 IRQ_TYPE_LEVEL_HIGH>; 339 clocks = <&rcc QSPI_K>; 340 resets = <&rcc QSPI_R>; 341 status = "disabled"; 342 }; 343 344 sdmmc1: mmc@58005000 { 345 compatible = "st,stm32-sdmmc2", "arm,pl18x", "arm,primecell"; 346 arm,primecell-periphid = <0x00253180>; 347 reg = <0x58005000 0x1000>, <0x58006000 0x1000>; 348 interrupts = <GIC_SPI 49 IRQ_TYPE_LEVEL_HIGH>; 349 interrupt-names = "cmd_irq"; 350 clocks = <&rcc SDMMC1_K>; 351 clock-names = "apb_pclk"; 352 resets = <&rcc SDMMC1_R>; 353 cap-sd-highspeed; 354 cap-mmc-highspeed; 355 max-frequency = <120000000>; 356 status = "disabled"; 357 }; 358 359 sdmmc2: mmc@58007000 { 360 compatible = "st,stm32-sdmmc2", "arm,pl18x", "arm,primecell"; 361 arm,primecell-periphid = <0x00253180>; 362 reg = <0x58007000 0x1000>, <0x58008000 0x1000>; 363 interrupts = <GIC_SPI 124 IRQ_TYPE_LEVEL_HIGH>; 364 interrupt-names = "cmd_irq"; 365 clocks = <&rcc SDMMC2_K>; 366 clock-names = "apb_pclk"; 367 resets = <&rcc SDMMC2_R>; 368 cap-sd-highspeed; 369 cap-mmc-highspeed; 370 max-frequency = <120000000>; 371 status = "disabled"; 372 }; 373 374 iwdg2: watchdog@5a002000 { 375 compatible = "st,stm32mp1-iwdg"; 376 reg = <0x5a002000 0x400>; 377 secure-interrupts = <GIC_SPI 151 IRQ_TYPE_LEVEL_HIGH>; 378 clocks = <&rcc IWDG2>, <&rcc CK_LSI>; 379 clock-names = "pclk", "lsi"; 380 status = "disabled"; 381 }; 382 383 ddr: ddr@5a003000{ 384 compatible = "st,stm32mp1-ddr"; 385 reg = <0x5A003000 0x550 0x5A004000 0x234>; 386 clocks = <&rcc AXIDCG>, 387 <&rcc DDRC1>, 388 <&rcc DDRC2>, 389 <&rcc DDRPHYC>, 390 <&rcc DDRCAPB>, 391 <&rcc DDRPHYCAPB>; 392 clock-names = "axidcg", 393 "ddrc1", 394 "ddrc2", 395 "ddrphyc", 396 "ddrcapb", 397 "ddrphycapb"; 398 status = "okay"; 399 }; 400 401 usbphyc: usbphyc@5a006000 { 402 #address-cells = <1>; 403 #size-cells = <0>; 404 #clock-cells = <0>; 405 compatible = "st,stm32mp1-usbphyc"; 406 reg = <0x5a006000 0x1000>; 407 clocks = <&rcc USBPHY_K>; 408 resets = <&rcc USBPHY_R>; 409 vdda1v1-supply = <®11>; 410 vdda1v8-supply = <®18>; 411 status = "disabled"; 412 413 usbphyc_port0: usb-phy@0 { 414 #phy-cells = <0>; 415 reg = <0>; 416 }; 417 418 usbphyc_port1: usb-phy@1 { 419 #phy-cells = <1>; 420 reg = <1>; 421 }; 422 }; 423 424 usart1: serial@5c000000 { 425 compatible = "st,stm32h7-uart"; 426 reg = <0x5c000000 0x400>; 427 interrupts = <GIC_SPI 37 IRQ_TYPE_LEVEL_HIGH>; 428 clocks = <&rcc USART1_K>; 429 resets = <&rcc USART1_R>; 430 status = "disabled"; 431 }; 432 433 spi6: spi@5c001000 { 434 #address-cells = <1>; 435 #size-cells = <0>; 436 compatible = "st,stm32h7-spi"; 437 reg = <0x5c001000 0x400>; 438 interrupts = <GIC_SPI 86 IRQ_TYPE_LEVEL_HIGH>; 439 clocks = <&rcc SPI6_K>; 440 resets = <&rcc SPI6_R>; 441 status = "disabled"; 442 }; 443 444 i2c4: i2c@5c002000 { 445 compatible = "st,stm32mp15-i2c"; 446 reg = <0x5c002000 0x400>; 447 interrupt-names = "event", "error"; 448 interrupts-extended = <&exti 24 IRQ_TYPE_LEVEL_HIGH>, 449 <&intc GIC_SPI 96 IRQ_TYPE_LEVEL_HIGH>; 450 clocks = <&rcc I2C4_K>; 451 resets = <&rcc I2C4_R>; 452 #address-cells = <1>; 453 #size-cells = <0>; 454 st,syscfg-fmp = <&syscfg 0x4 0x8>; 455 wakeup-source; 456 status = "disabled"; 457 }; 458 459 iwdg1: watchdog@5c003000 { 460 compatible = "st,stm32mp1-iwdg"; 461 reg = <0x5C003000 0x400>; 462 interrupts = <GIC_SPI 150 IRQ_TYPE_LEVEL_HIGH>; 463 clocks = <&rcc IWDG1>, <&rcc CK_LSI>; 464 clock-names = "pclk", "lsi"; 465 status = "disabled"; 466 }; 467 468 rtc: rtc@5c004000 { 469 compatible = "st,stm32mp1-rtc"; 470 reg = <0x5c004000 0x400>; 471 clocks = <&rcc RTCAPB>, <&rcc RTC>; 472 clock-names = "pclk", "rtc_ck"; 473 interrupts-extended = <&exti 19 IRQ_TYPE_LEVEL_HIGH>; 474 status = "disabled"; 475 }; 476 477 bsec: efuse@5c005000 { 478 compatible = "st,stm32mp15-bsec"; 479 reg = <0x5c005000 0x400>; 480 #address-cells = <1>; 481 #size-cells = <1>; 482 483 cfg0_otp: cfg0_otp@0 { 484 reg = <0x0 0x1>; 485 }; 486 part_number_otp: part_number_otp@4 { 487 reg = <0x4 0x1>; 488 }; 489 monotonic_otp: monotonic_otp@10 { 490 reg = <0x10 0x4>; 491 }; 492 nand_otp: nand_otp@24 { 493 reg = <0x24 0x4>; 494 }; 495 uid_otp: uid_otp@34 { 496 reg = <0x34 0xc>; 497 }; 498 package_otp: package_otp@40 { 499 reg = <0x40 0x4>; 500 }; 501 hw2_otp: hw2_otp@48 { 502 reg = <0x48 0x4>; 503 }; 504 ts_cal1: calib@5c { 505 reg = <0x5c 0x2>; 506 }; 507 ts_cal2: calib@5e { 508 reg = <0x5e 0x2>; 509 }; 510 mac_addr: mac_addr@e4 { 511 reg = <0xe4 0x8>; 512 st,non-secure-otp; 513 }; 514 }; 515 516 etzpc: etzpc@5c007000 { 517 compatible = "st,stm32-etzpc"; 518 reg = <0x5C007000 0x400>; 519 clocks = <&rcc TZPC>; 520 status = "disabled"; 521 secure-status = "okay"; 522 }; 523 524 stgen: stgen@5c008000 { 525 compatible = "st,stm32-stgen"; 526 reg = <0x5C008000 0x1000>; 527 }; 528 529 i2c6: i2c@5c009000 { 530 compatible = "st,stm32mp15-i2c"; 531 reg = <0x5c009000 0x400>; 532 interrupt-names = "event", "error"; 533 interrupts-extended = <&exti 54 IRQ_TYPE_LEVEL_HIGH>, 534 <&intc GIC_SPI 136 IRQ_TYPE_LEVEL_HIGH>; 535 clocks = <&rcc I2C6_K>; 536 resets = <&rcc I2C6_R>; 537 #address-cells = <1>; 538 #size-cells = <0>; 539 st,syscfg-fmp = <&syscfg 0x4 0x20>; 540 wakeup-source; 541 status = "disabled"; 542 }; 543 544 tamp: tamp@5c00a000 { 545 compatible = "st,stm32-tamp", "simple-bus", "syscon", "simple-mfd"; 546 reg = <0x5c00a000 0x400>; 547 secure-interrupts = <GIC_SPI 197 IRQ_TYPE_LEVEL_HIGH>; 548 clocks = <&rcc RTCAPB>; 549 }; 550 551 /* 552 * Break node order to solve dependency probe issue between 553 * pinctrl and exti. 554 */ 555 pinctrl: pin-controller@50002000 { 556 #address-cells = <1>; 557 #size-cells = <1>; 558 compatible = "st,stm32mp157-pinctrl"; 559 ranges = <0 0x50002000 0xa400>; 560 interrupt-parent = <&exti>; 561 st,syscfg = <&exti 0x60 0xff>; 562 pins-are-numbered; 563 564 gpioa: gpio@50002000 { 565 gpio-controller; 566 #gpio-cells = <2>; 567 interrupt-controller; 568 #interrupt-cells = <2>; 569 reg = <0x0 0x400>; 570 clocks = <&rcc GPIOA>; 571 st,bank-name = "GPIOA"; 572 status = "disabled"; 573 }; 574 575 gpiob: gpio@50003000 { 576 gpio-controller; 577 #gpio-cells = <2>; 578 interrupt-controller; 579 #interrupt-cells = <2>; 580 reg = <0x1000 0x400>; 581 clocks = <&rcc GPIOB>; 582 st,bank-name = "GPIOB"; 583 status = "disabled"; 584 }; 585 586 gpioc: gpio@50004000 { 587 gpio-controller; 588 #gpio-cells = <2>; 589 interrupt-controller; 590 #interrupt-cells = <2>; 591 reg = <0x2000 0x400>; 592 clocks = <&rcc GPIOC>; 593 st,bank-name = "GPIOC"; 594 status = "disabled"; 595 }; 596 597 gpiod: gpio@50005000 { 598 gpio-controller; 599 #gpio-cells = <2>; 600 interrupt-controller; 601 #interrupt-cells = <2>; 602 reg = <0x3000 0x400>; 603 clocks = <&rcc GPIOD>; 604 st,bank-name = "GPIOD"; 605 status = "disabled"; 606 }; 607 608 gpioe: gpio@50006000 { 609 gpio-controller; 610 #gpio-cells = <2>; 611 interrupt-controller; 612 #interrupt-cells = <2>; 613 reg = <0x4000 0x400>; 614 clocks = <&rcc GPIOE>; 615 st,bank-name = "GPIOE"; 616 status = "disabled"; 617 }; 618 619 gpiof: gpio@50007000 { 620 gpio-controller; 621 #gpio-cells = <2>; 622 interrupt-controller; 623 #interrupt-cells = <2>; 624 reg = <0x5000 0x400>; 625 clocks = <&rcc GPIOF>; 626 st,bank-name = "GPIOF"; 627 status = "disabled"; 628 }; 629 630 gpiog: gpio@50008000 { 631 gpio-controller; 632 #gpio-cells = <2>; 633 interrupt-controller; 634 #interrupt-cells = <2>; 635 reg = <0x6000 0x400>; 636 clocks = <&rcc GPIOG>; 637 st,bank-name = "GPIOG"; 638 status = "disabled"; 639 }; 640 641 gpioh: gpio@50009000 { 642 gpio-controller; 643 #gpio-cells = <2>; 644 interrupt-controller; 645 #interrupt-cells = <2>; 646 reg = <0x7000 0x400>; 647 clocks = <&rcc GPIOH>; 648 st,bank-name = "GPIOH"; 649 status = "disabled"; 650 }; 651 652 gpioi: gpio@5000a000 { 653 gpio-controller; 654 #gpio-cells = <2>; 655 interrupt-controller; 656 #interrupt-cells = <2>; 657 reg = <0x8000 0x400>; 658 clocks = <&rcc GPIOI>; 659 st,bank-name = "GPIOI"; 660 status = "disabled"; 661 }; 662 663 gpioj: gpio@5000b000 { 664 gpio-controller; 665 #gpio-cells = <2>; 666 interrupt-controller; 667 #interrupt-cells = <2>; 668 reg = <0x9000 0x400>; 669 clocks = <&rcc GPIOJ>; 670 st,bank-name = "GPIOJ"; 671 status = "disabled"; 672 }; 673 674 gpiok: gpio@5000c000 { 675 gpio-controller; 676 #gpio-cells = <2>; 677 interrupt-controller; 678 #interrupt-cells = <2>; 679 reg = <0xa000 0x400>; 680 clocks = <&rcc GPIOK>; 681 st,bank-name = "GPIOK"; 682 status = "disabled"; 683 }; 684 }; 685 686 pinctrl_z: pin-controller-z@54004000 { 687 #address-cells = <1>; 688 #size-cells = <1>; 689 compatible = "st,stm32mp157-z-pinctrl"; 690 ranges = <0 0x54004000 0x400>; 691 pins-are-numbered; 692 interrupt-parent = <&exti>; 693 st,syscfg = <&exti 0x60 0xff>; 694 695 gpioz: gpio@54004000 { 696 gpio-controller; 697 #gpio-cells = <2>; 698 interrupt-controller; 699 #interrupt-cells = <2>; 700 reg = <0 0x400>; 701 clocks = <&rcc GPIOZ>; 702 st,bank-name = "GPIOZ"; 703 st,bank-ioport = <11>; 704 status = "disabled"; 705 }; 706 }; 707 }; 708}; 709