1 /* 2 * Copyright (C) 2022, STMicroelectronics - All Rights Reserved 3 * 4 * SPDX-License-Identifier: BSD-3-Clause 5 */ 6 7 #include <common/debug.h> 8 #include <drivers/delay_timer.h> 9 #include <drivers/st/stm32mp_ddr.h> 10 #include <drivers/st/stm32mp_ddrctrl_regs.h> 11 #include <drivers/st/stm32mp_pmic.h> 12 #include <lib/mmio.h> 13 14 #include <platform_def.h> 15 16 #define INVALID_OFFSET 0xFFU 17 18 static uintptr_t get_base_addr(const struct stm32mp_ddr_priv *priv, enum stm32mp_ddr_base_type base) 19 { 20 if (base == DDRPHY_BASE) { 21 return (uintptr_t)priv->phy; 22 } else { 23 return (uintptr_t)priv->ctl; 24 } 25 } 26 27 void stm32mp_ddr_set_reg(const struct stm32mp_ddr_priv *priv, enum stm32mp_ddr_reg_type type, 28 const void *param, const struct stm32mp_ddr_reg_info *ddr_registers) 29 { 30 unsigned int i; 31 unsigned int value; 32 enum stm32mp_ddr_base_type base = ddr_registers[type].base; 33 uintptr_t base_addr = get_base_addr(priv, base); 34 const struct stm32mp_ddr_reg_desc *desc = ddr_registers[type].desc; 35 36 VERBOSE("init %s\n", ddr_registers[type].name); 37 for (i = 0; i < ddr_registers[type].size; i++) { 38 uintptr_t ptr = base_addr + desc[i].offset; 39 40 if (desc[i].par_offset == INVALID_OFFSET) { 41 ERROR("invalid parameter offset for %s", desc[i].name); 42 panic(); 43 } else { 44 value = *((uint32_t *)((uintptr_t)param + 45 desc[i].par_offset)); 46 mmio_write_32(ptr, value); 47 } 48 } 49 } 50 51 /* Start quasi dynamic register update */ 52 void stm32mp_ddr_start_sw_done(struct stm32mp_ddrctl *ctl) 53 { 54 mmio_clrbits_32((uintptr_t)&ctl->swctl, DDRCTRL_SWCTL_SW_DONE); 55 VERBOSE("[0x%lx] swctl = 0x%x\n", 56 (uintptr_t)&ctl->swctl, mmio_read_32((uintptr_t)&ctl->swctl)); 57 } 58 59 /* Wait quasi dynamic register update */ 60 void stm32mp_ddr_wait_sw_done_ack(struct stm32mp_ddrctl *ctl) 61 { 62 uint64_t timeout; 63 uint32_t swstat; 64 65 mmio_setbits_32((uintptr_t)&ctl->swctl, DDRCTRL_SWCTL_SW_DONE); 66 VERBOSE("[0x%lx] swctl = 0x%x\n", 67 (uintptr_t)&ctl->swctl, mmio_read_32((uintptr_t)&ctl->swctl)); 68 69 timeout = timeout_init_us(TIMEOUT_US_1S); 70 do { 71 swstat = mmio_read_32((uintptr_t)&ctl->swstat); 72 VERBOSE("[0x%lx] swstat = 0x%x ", 73 (uintptr_t)&ctl->swstat, swstat); 74 if (timeout_elapsed(timeout)) { 75 panic(); 76 } 77 } while ((swstat & DDRCTRL_SWSTAT_SW_DONE_ACK) == 0U); 78 79 VERBOSE("[0x%lx] swstat = 0x%x\n", 80 (uintptr_t)&ctl->swstat, swstat); 81 } 82 83 void stm32mp_ddr_enable_axi_port(struct stm32mp_ddrctl *ctl) 84 { 85 /* Enable uMCTL2 AXI port 0 */ 86 mmio_setbits_32((uintptr_t)&ctl->pctrl_0, DDRCTRL_PCTRL_N_PORT_EN); 87 VERBOSE("[0x%lx] pctrl_0 = 0x%x\n", (uintptr_t)&ctl->pctrl_0, 88 mmio_read_32((uintptr_t)&ctl->pctrl_0)); 89 90 #if STM32MP_DDR_DUAL_AXI_PORT 91 /* Enable uMCTL2 AXI port 1 */ 92 mmio_setbits_32((uintptr_t)&ctl->pctrl_1, DDRCTRL_PCTRL_N_PORT_EN); 93 VERBOSE("[0x%lx] pctrl_1 = 0x%x\n", (uintptr_t)&ctl->pctrl_1, 94 mmio_read_32((uintptr_t)&ctl->pctrl_1)); 95 #endif 96 97 } 98 99 int stm32mp_board_ddr_power_init(enum ddr_type ddr_type) 100 { 101 if (dt_pmic_status() > 0) { 102 return pmic_ddr_power_init(ddr_type); 103 } 104 105 return 0; 106 } 107