fix(bl1): harden FWU copy/auth overflow checks

Use full-size overflow checks so invalid image source/size
values can’t wrap and slip past validation during copy/auth,
preventing out-of-range memory

fix(bl1): harden FWU copy/auth overflow checks

Use full-size overflow checks so invalid image source/size
values can’t wrap and slip past validation during copy/auth,
preventing out-of-range memory access.

Change-Id: Ie49793dd13e68f044c2ae78f33fcb1326d2853b4
Signed-off-by: Manish V Badarkhe <Manish.Badarkhe@arm.com>

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fix(cpus): unconstrain WORKAROUND_CVE_2025_0647

Conditional flag enables are strongly discouraged in TF-A because they
cause cyclic dependencies that we are not equipped to deal with. On a
real plat

fix(cpus): unconstrain WORKAROUND_CVE_2025_0647

Conditional flag enables are strongly discouraged in TF-A because they
cause cyclic dependencies that we are not equipped to deal with. On a
real platform, ARM_ARCH_{MAJOR, MINOR} should be set in platform.mk but
WORKAROUND_CVE_2025_0647 gets its value before platform.mk is evaluated.

Further, WORKAROUND_CVE_2025_0647 is only present on cores the feature
set of which is known ahead of time. Using ARM_ARCH_{MAJOR, MINOR} is
redundant and incorrect (as it sidesteps the feature detection
mechanism).

This patch solves both of these issues by making
WORKAROUND_CVE_2025_0647 unconstrained by ARM_ARCH_{MAJOR, MINOR} and
making it buildable on a v8.0 target. Running the workaround will only
happen on affected cores which, by definition, all implement armv8.5 so
doing any checks in unnecessary.

Change-Id: Ia164077f09b552d42b558ada4f6036cabbd34f64
Signed-off-by: Boyan Karatotev <boyan.karatotev@arm.com>

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Merge "fix(bl1): clear loaded ID on pre-image load failure" into integration

refactor(bl1): drop ENABLE_RME check

Starting BL2 in EL3 is not tied to ENABLE_RME but to the boot flow.
In an RME-enabled boot flow, BL2 runs at EL3 and boots BL31. Therefore,
BL2_RUNS_AT_EL3 shoul

refactor(bl1): drop ENABLE_RME check

Starting BL2 in EL3 is not tied to ENABLE_RME but to the boot flow.
In an RME-enabled boot flow, BL2 runs at EL3 and boots BL31. Therefore,
BL2_RUNS_AT_EL3 should be used to handle the transition to the next boot
image.

This change prepares the codebase for later patches that add feature
detection support for RME.

Signed-off-by: Arunachalam Ganapathy <arunachalam.ganapathy@arm.com>
Change-Id: Ic19b73f1edf5b5ccbd530c662c91e1d38a01fa36

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fix(bl1): clear loaded ID on pre-image load failure

if bl1_plat_handle_pre_image_load() fails, remove the previously
marked loaded ID before returning -EPERM to avoid stale BL1-FWU state.

Change-Id

fix(bl1): clear loaded ID on pre-image load failure

if bl1_plat_handle_pre_image_load() fails, remove the previously
marked loaded ID before returning -EPERM to avoid stale BL1-FWU state.

Change-Id: I6421fd764ec3d3e9ce896e4339921149fec118c6
Signed-off-by: Manish V Badarkhe <Manish.Badarkhe@arm.com>

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feat(crypto): enable the runtime instrumentation for crypto extension

Add runtime instrumentation for the authentication process in BL1
and BL2, to measure the speedup of the authentication after
en

feat(crypto): enable the runtime instrumentation for crypto extension

Add runtime instrumentation for the authentication process in BL1
and BL2, to measure the speedup of the authentication after
enabling the crypto extension.

Change-Id: Ieea927e7e8bd0d109525f28b06510acf0ab62e5c
Signed-off-by: Xialin Liu <xialin.liu@arm.com>

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feat(crypto): enable access to SIMD crypto in BL1 and BL2

Disable the floating point register traps in image auth and
loading in BL1 and BL2 to allow the access to SIMD crypto
extension during the b

feat(crypto): enable access to SIMD crypto in BL1 and BL2

Disable the floating point register traps in image auth and
loading in BL1 and BL2 to allow the access to SIMD crypto
extension during the booting process.

Change-Id: I9c20715d54f5d2988aa706e91e1a657dcd06dfc2
Signed-off-by: Xialin Liu <xialin.liu@arm.com>

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fix(security): add workaround for CVE-2025-0647

This workaround fixes an issue with the CPP RCTX instruction by
issuing an instruction patch sequence to trap uses of the CPP RCTX
instruction from EL

fix(security): add workaround for CVE-2025-0647

This workaround fixes an issue with the CPP RCTX instruction by
issuing an instruction patch sequence to trap uses of the CPP RCTX
instruction from EL0, EL1, and EL2 to EL3 and perform a workaround
procedure using the implementation defined trap handler to ensure
the correct behavior of the system. In addition, it includes an EL3
API to be used if EL3 firmware needs to use the CPP RCTX instruction.
This saves the overhead of exception handling, and EL3 does not
generically support trapping EL3->EL3, and adding support for that
is not trivial due to the implications for context management.

The issue affects the following CPUs:

C1-Premium
C1-Ultra
Cortex-A710
Cortex-X2
Cortex-X3
Cortex-X4
Cortex-X925
Neoverse N2
Neoverse V2
Neoverse V3
Neoverse V3AE (handled same as V3 CPU in TF-A CPU-Lib)

Arm Security Bulletin Document:
https://developer.arm.com/documentation/111546

Change-Id: I5e7589afbeb69ebb79c01bec80e29f572aff3d89
Signed-off-by: John Powell <john.powell@arm.com>
Signed-off-by: Govindraj Raja <govindraj.raja@arm.com>

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feat(el3-runtime): translate EL3 handled exceptions to C and always call prepare_el3_entry

Exception handling in BL31 is tricky business and to satisfy the varying
requirements of the different code

feat(el3-runtime): translate EL3 handled exceptions to C and always call prepare_el3_entry

Exception handling in BL31 is tricky business and to satisfy the varying
requirements of the different code paths it has thus far largely been
written in assembly. However, assembly is extremely tedious to read and
modify. Similar to context management, it is desirable to have as much
as possible in C. C code is generally easier to follow and can enable
the compiler to do more optimisations on surrounding code.

Most exceptions that BL31 deals with are the synchronous exceptions and
those are processed within BL31. They already get prepared for EL3 entry
and after the initial dispatch end up in C. So the dispatch can also be
converted in C. Interrupt exceptions are very similar so are converted
too. Finally, asynchronous external aborts share some code with
synchronous external aborts and may end up being processed deeper in
BL31. So they can safely be prepared for EL3 entry too and converted to
C so that they can share code properly.

The IMP DEF exceptions are not part of this refactor as their speed may
be important. There is currently little that uses them, but they can be
converted to C too once their use expands and usage allows it.

This refactor allows to expand the responsibilities of
prepare_el3_entry(). Its role is already to prepare context for
executing within EL3 but with this patch EL3 execution is synonymous
with C runtime execution. So it's given the responsibility of saving
spsr and elr as well as putting the runtime stack in.

When a synchronous exception happens, the only possible paths are to
enter the C EL3 runtime, exiting via el3_exit(), or to panic. In the EL3
runtime case, we always need prepare_el3_entry() and the runtime stack,
whereas in the panic case, this doesn't matter as we will never return.
So hoist the prepare_el3_entry() call and the changing of the stacks as
early as possible and make the rest of the code agnostic of this.

This patch also gets rid of smc_prohibited. It is an optimisation by
skipping prepare_el3_entry() when a bad smc call happens. However, speed
doesn't matter in this case as this is an erroneous case.

Change-Id: I411af9d17ef4046a736b1f4f5f8fbc9c28e66106
Signed-off-by: Boyan Karatotev <boyan.karatotev@arm.com>

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feat(cpufeat): enable USE_SPINLOCK_CAS to FEAT_STATE_CHECKED

The FEAT_LSE enablement predates the FEAT_STATE framework and has never
been converted. Since the introduction of USE_SPINLOCK_CAS we've

feat(cpufeat): enable USE_SPINLOCK_CAS to FEAT_STATE_CHECKED

The FEAT_LSE enablement predates the FEAT_STATE framework and has never
been converted. Since the introduction of USE_SPINLOCK_CAS we've gained
lots of quality of life features that allow for better feature
enablement. This patch converts USE_SPINLOCK_CAS to tri-state and adds
it to FEATURE_DETECTION to align with all other features.

Instead of introducing the assembly checking for tri-state, this patch
translates all locking routines to C inline assembly and uses the
standard C helpers. The main benefit is that this gives greater
visibility to the compiler about what the functions are doing and lets
it optimise better. Namely, it is able to allocate registers itself and
inline the functions when LTO is enabled.

An unsuccessful attempt was made to use the instructions directly and
have even flow control in C. This, however, made code very complicated
and less efficient in the tight loops of the spinlock.

The last use of ARM_ARCH_AT_LEAST goes away with this change and so this
macro is removed. It has now been fully superseded by the FEAT_STATE
framework.

This change exposes a limitation - RME_GPT_BITLOCK_BLOCK requires
USE_SPINLOCK_CAS. This patch does not address this in any way but makes
the relationship explicit.

Change-Id: I580081549aceded2dca3e0f4564ee7510a7e56ae
Signed-off-by: Boyan Karatotev <boyan.karatotev@arm.com>

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fix(bl1): use per-world context correctly

Currently, the configuration with BL1 and BL2 at SEL1 will transition
via el3_exit which will restore per-world context. However, that context
is never writ

fix(bl1): use per-world context correctly

Currently, the configuration with BL1 and BL2 at SEL1 will transition
via el3_exit which will restore per-world context. However, that context
is never written to and so zeroes end up in registers, which is not
necessarily correct.

This patch gets BL1 to call cm_manage_extensions_per_world() whenever
BL2 runs in a lower EL. This allows the per-world registers to have the
reset values we intend. An accompanying call to
cm_manage_extensions_el3() is also added for completeness.

Doing this shows a small deficiency in cptr_el3 - bits TFP and TCPAC
change a lot. This patch makes them consistent by always setting TCPAC
and TFP to 0 which unconditionally enable access to CPTR_EL2 and FPCR by
default as they are always accessible. Other places that manipulate the
TFP bit are removed.

A nice side effect of all of this is that we're now in a position to
enable and use any architectural extension in BL2.

Change-Id: I070d62bbf8e9d9b472caf7e2c931c303523be308
Signed-off-by: Boyan Karatotev <boyan.karatotev@arm.com>

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feat(build): setting CRYPTO_LIB via CRYPTO_SUPPORT

Setting CRYPTO_LIB based on CRYPTO_SUPPORT via the
CRYPTO_SUPPORT macro to be called by component-specific makefiles.

Signed-off-by: Lauren Wehrme

feat(build): setting CRYPTO_LIB via CRYPTO_SUPPORT

Setting CRYPTO_LIB based on CRYPTO_SUPPORT via the
CRYPTO_SUPPORT macro to be called by component-specific makefiles.

Signed-off-by: Lauren Wehrmeister <lauren.wehrmeister@arm.com>
Change-Id: Ib400e4668c60c24bb4399de6a320b5c16205affb

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feat(build): set CRYPTO_SUPPORT macro per BL

Moving the setting of CRYPTO_SUPPORT from the main Makefile to
individual component makefiles using the new build macro
make_defines for each BL-specific

feat(build): set CRYPTO_SUPPORT macro per BL

Moving the setting of CRYPTO_SUPPORT from the main Makefile to
individual component makefiles using the new build macro
make_defines for each BL-specific CPPFLAGS.

Rework romlib build command to use CRYPTO_LIB to determine mbedtls need
instead of CRYPTO_SUPPORT. If CRYPTO_SUPPORT is set for any component,
then CRYPTO_LIB will be filled, romlib can use this instead.

Add a convenience makefile macro for setting CRYPTO_SUPPORT from
component specific makefiles, have components call the macro based on
whether authenication verification (NEED_AUTH) and/or hash calculation
(NEED_HASH) is required for the specific boot stage.

Signed-off-by: Lauren Wehrmeister <lauren.wehrmeister@arm.com>
Change-Id: I7e81fede74fb9c04694b022e8eebed460616565c

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Merge changes Id711e387,I531a2ee1,Ic5b48514,I81f5f663,I6c529c13, ... into integration

* changes:
refactor(romlib): absorb WRAPPER_FLAGS into LDFLAGS
fix(build): simplify the -target options
fe

Merge changes Id711e387,I531a2ee1,Ic5b48514,I81f5f663,I6c529c13, ... into integration

* changes:
refactor(romlib): absorb WRAPPER_FLAGS into LDFLAGS
fix(build): simplify the -target options
feat(build): allow full LTO builds with clang
refactor(build): make sorting of sections generic
feat(build): use clang as a linker
fix(build): correctly detect that an option is missing with ld_option
feat(build): pass cflags to the linker when LTO is enabled

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refactor(bl1): simplify context getting and setting

BL1 has no need to support cm_set_context() as that is only needed by
runtime services which BL1 doesn't provide. So the context can be
simplified

refactor(bl1): simplify context getting and setting

BL1 has no need to support cm_set_context() as that is only needed by
runtime services which BL1 doesn't provide. So the context can be
simplified to make it easier to understand.

Change-Id: Iea14d49c973436afad40cd41d1159b2abf51c65d
Signed-off-by: Boyan Karatotev <boyan.karatotev@arm.com>

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refactor(build): make sorting of sections generic

All BLs define essentially the same sequence for sorting of sections.
Make that generic so it applies more easily.

Change-Id: I81f5f6635232bd43d999

refactor(build): make sorting of sections generic

All BLs define essentially the same sequence for sorting of sections.
Make that generic so it applies more easily.

Change-Id: I81f5f6635232bd43d999c8054e290a6437c26c71
Signed-off-by: Boyan Karatotev <boyan.karatotev@arm.com>

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feat(build): use clang as a linker

To support LTO, the gcc binary is used as a compiler, assembler, and
linker. Do the same for clang and enable LTO builds with it as a side
effect.

This simplifies

feat(build): use clang as a linker

To support LTO, the gcc binary is used as a compiler, assembler, and
linker. Do the same for clang and enable LTO builds with it as a side
effect.

This simplifies code quite a bit as the gcc/clang different is much
smaller. Support for ld/lld (if overriden with LD) is maintained.

This is a good time to convert tabs to spaces to conform to make's
expectations on syntax.

Change-Id: I6c529c1393f7e9e8046ed537f871fc3ad91d599a
Signed-off-by: Boyan Karatotev <boyan.karatotev@arm.com>

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fix(cm): do not save SCR_EL3 on external aborts

SCR_EL3 is static. For non-root worlds, once initialised by
cm_setup_context(), its value is immutable and only restored by
el3_exit(). For the root w

fix(cm): do not save SCR_EL3 on external aborts

SCR_EL3 is static. For non-root worlds, once initialised by
cm_setup_context(), its value is immutable and only restored by
el3_exit(). For the root world (or EL3 when that's not a thing)
setup_el3_execution_context() (via prepare_el3_entry()) will write a
different static value in, with the expectation that el3_exit() will
wipe it. As such saving scr_el3 in the case of a double fault is not
necessary, and even harmful as the wrong (root's) value will get written
in.

Change-Id: Ibf5b3a809fc0208a98ded20fe8d50c7405f808b9
Signed-off-by: Boyan Karatotev <boyan.karatotev@arm.com>

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refactor: unify blx_setup() and blx_main()

All BLs have a bl_setup() for things that need to happen early, a fall
back into assembly and then bl_main() for the main functionality. This
was necessary

refactor: unify blx_setup() and blx_main()

All BLs have a bl_setup() for things that need to happen early, a fall
back into assembly and then bl_main() for the main functionality. This
was necessary in order to fiddle with PAuth related things that tend to
break C calls. Since then PAuth's enablement has seen a lot of
refactoring and this is now worked around cleanly so the distinction can
be removed. The only tradeoff is that this requires pauth to not be used
for the top-level main function.

There are two main benefits to doing this: First, code is easier to
understand as it's all together and the entrypoint is smaller. Second,
the compiler gets to see more of the code and apply optimisations
(importantly LTO).

Change-Id: Iddb93551115a2048988017547eb7b8db441dbd37
Signed-off-by: Boyan Karatotev <boyan.karatotev@arm.com>

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fix(el3-runtime): typecast operands to match data type

This corrects the MISRA violation C2012-10.3:
The value of an expression shall not be assigned to an object with a
narrower essential type or o

fix(el3-runtime): typecast operands to match data type

This corrects the MISRA violation C2012-10.3:
The value of an expression shall not be assigned to an object with a
narrower essential type or of a different essential type category.
Replaced usage of 'unsigned int' with 'size_t' to ensure type
consistency and prevent assignment to a narrower or different
essential type.

Change-Id: I79501e216a04753ebd005d64375357b9332440d9
Signed-off-by: Nithin G <nithing@amd.com>
Signed-off-by: Maheedhar Bollapalli <maheedharsai.bollapalli@amd.com>

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feat(bl): adding psa crypto - crypto_mod_finish()

Adding call to crypto_mod_finish() at the end of crypto usage in the
bl mains. This is currently used for psa crytpo to destroy the
psa_key_ids in t

feat(bl): adding psa crypto - crypto_mod_finish()

Adding call to crypto_mod_finish() at the end of crypto usage in the
bl mains. This is currently used for psa crytpo to destroy the
psa_key_ids in the psa key store, but could be expanded if required
later.

Signed-off-by: Lauren Wehrmeister <lauren.wehrmeister@arm.com>
Change-Id: I3dba9fe87b6bb64b629dda9d6c4653b116e7ee62

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perf(cpufeat): centralise PAuth key saving

prepare_el3_entry() is meant to be the one-stop shop for all the context
we must fiddle with to enter EL3 proper. However, PAuth is the one
exception, happ

perf(cpufeat): centralise PAuth key saving

prepare_el3_entry() is meant to be the one-stop shop for all the context
we must fiddle with to enter EL3 proper. However, PAuth is the one
exception, happening right after. Absorb it into prepare_el3_entry(),
handling the BL1/BL31 difference.

This is a good time to also move the key saving into the enable
function, also to centralise. With this it becomes apparent that saving
keys just before CPU_SUSPEND is redundant as they will be reinitialised
when the core wakes up.

Note that the key loading, now in save_gp_pmcr_pauth_regs, does not end
in an isb. The effects of the key change are not needed until the isb
in the caller, so this isb is not needed.

Change-Id: Idd286bea91140c106ab4c933c5c44b0bc2050ca2
Signed-off-by: Boyan Karatotev <boyan.karatotev@arm.com>

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chore(cpufeat): remove PAuth presence checks

TF-A operates a policy that features must be correctly configured per
each platform. There is a tool to assist in making sure that this is the
case - FEA

chore(cpufeat): remove PAuth presence checks

TF-A operates a policy that features must be correctly configured per
each platform. There is a tool to assist in making sure that this is the
case - FEATURE_DETECTION. So performing these checks in common code is
not the right place for this. Remove them and rely on FEATURE_DETECTION.

Change-Id: If3c25dcd7bc880f1f085bc6bb5270d8d1c4caf43
Signed-off-by: Boyan Karatotev <boyan.karatotev@arm.com>

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fix(bl1): prevent null pointer dereference

Added an assertion to ensure ptr is not NULL before
dereferencing it. This prevents potential null pointer
dereference issues detected by Coverity.

Change

fix(bl1): prevent null pointer dereference

Added an assertion to ensure ptr is not NULL before
dereferencing it. This prevents potential null pointer
dereference issues detected by Coverity.

Change-Id: I2e3325cd7cbdf141959bacd6135461be24ae6169
Signed-off-by: Manish V Badarkhe <Manish.Badarkhe@arm.com>

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