1/* 2 * Copyright (c) 2016-2025, Arm Limited and Contributors. All rights reserved. 3 * 4 * SPDX-License-Identifier: BSD-3-Clause 5 */ 6 7#include <arch.h> 8#include <asm_macros.S> 9#include <common/bl_common.h> 10#include <cortex_a35.h> 11#include <cpu_macros.S> 12#include <plat_macros.S> 13 14cpu_reset_prologue cortex_a35 15 /* --------------------------------------------- 16 * Disable L1 data cache and unified L2 cache 17 * --------------------------------------------- 18 */ 19func cortex_a35_disable_dcache 20 sysreg_bit_clear sctlr_el3, SCTLR_C_BIT 21 isb 22 ret 23endfunc cortex_a35_disable_dcache 24 25 /* --------------------------------------------- 26 * Disable intra-cluster coherency 27 * --------------------------------------------- 28 */ 29func cortex_a35_disable_smp 30 sysreg_bit_clear CORTEX_A35_CPUECTLR_EL1, CORTEX_A35_CPUECTLR_SMPEN_BIT 31 isb 32 dsb sy 33 ret 34endfunc cortex_a35_disable_smp 35 36workaround_reset_start cortex_a35, ERRATUM(855472), ERRATA_A35_855472 37 sysreg_bit_set CORTEX_A35_CPUACTLR_EL1, CORTEX_A35_CPUACTLR_EL1_ENDCCASCI 38workaround_reset_end cortex_a35, ERRATUM(855472) 39 40check_erratum_ls cortex_a35, ERRATUM(855472), CPU_REV(0, 0) 41 42 /* ------------------------------------------------- 43 * The CPU Ops reset function for Cortex-A35. 44 * ------------------------------------------------- 45 */ 46cpu_reset_func_start cortex_a35 47 /* --------------------------------------------- 48 * Enable the SMP bit. 49 * --------------------------------------------- 50 */ 51 sysreg_bit_set CORTEX_A35_CPUECTLR_EL1, CORTEX_A35_CPUECTLR_SMPEN_BIT 52cpu_reset_func_end cortex_a35 53 54func cortex_a35_core_pwr_dwn 55 mov x18, x30 56 57 /* --------------------------------------------- 58 * Turn off caches. 59 * --------------------------------------------- 60 */ 61 bl cortex_a35_disable_dcache 62 63 /* --------------------------------------------- 64 * Flush L1 caches. 65 * --------------------------------------------- 66 */ 67 mov x0, #DCCISW 68 bl dcsw_op_level1 69 70 /* --------------------------------------------- 71 * Come out of intra cluster coherency 72 * --------------------------------------------- 73 */ 74 mov x30, x18 75 b cortex_a35_disable_smp 76endfunc cortex_a35_core_pwr_dwn 77 78func cortex_a35_cluster_pwr_dwn 79 mov x18, x30 80 81 /* --------------------------------------------- 82 * Turn off caches. 83 * --------------------------------------------- 84 */ 85 bl cortex_a35_disable_dcache 86 87 /* --------------------------------------------- 88 * Flush L1 caches. 89 * --------------------------------------------- 90 */ 91 mov x0, #DCCISW 92 bl dcsw_op_level1 93 94 /* --------------------------------------------- 95 * Disable the optional ACP. 96 * --------------------------------------------- 97 */ 98 bl plat_disable_acp 99 100 /* --------------------------------------------- 101 * Flush L2 caches. 102 * --------------------------------------------- 103 */ 104 mov x0, #DCCISW 105 bl dcsw_op_level2 106 107 /* --------------------------------------------- 108 * Come out of intra cluster coherency 109 * --------------------------------------------- 110 */ 111 mov x30, x18 112 b cortex_a35_disable_smp 113endfunc cortex_a35_cluster_pwr_dwn 114 115 /* --------------------------------------------- 116 * This function provides cortex_a35 specific 117 * register information for crash reporting. 118 * It needs to return with x6 pointing to 119 * a list of register names in ascii and 120 * x8 - x15 having values of registers to be 121 * reported. 122 * --------------------------------------------- 123 */ 124.section .rodata.cortex_a35_regs, "aS" 125cortex_a35_regs: /* The ascii list of register names to be reported */ 126 .asciz "cpuectlr_el1", "" 127 128func cortex_a35_cpu_reg_dump 129 adr x6, cortex_a35_regs 130 mrs x8, CORTEX_A35_CPUECTLR_EL1 131 ret 132endfunc cortex_a35_cpu_reg_dump 133 134declare_cpu_ops cortex_a35, CORTEX_A35_MIDR, \ 135 cortex_a35_reset_func, \ 136 cortex_a35_core_pwr_dwn, \ 137 cortex_a35_cluster_pwr_dwn 138