1/* 2 * Copyright (c) 2021-2025, Arm Limited. All rights reserved. 3 * 4 * SPDX-License-Identifier: BSD-3-Clause 5 */ 6 7#include <arch.h> 8#include <asm_macros.S> 9#include <common/bl_common.h> 10#include <neoverse_v2.h> 11#include <cpu_macros.S> 12#include <plat_macros.S> 13#include "wa_cve_2022_23960_bhb_vector.S" 14 15/* Hardware handled coherency */ 16#if HW_ASSISTED_COHERENCY == 0 17#error "Neoverse V2 must be compiled with HW_ASSISTED_COHERENCY enabled" 18#endif 19 20/* 64-bit only core */ 21#if CTX_INCLUDE_AARCH32_REGS == 1 22#error "Neoverse V2 supports only AArch64. Compile with CTX_INCLUDE_AARCH32_REGS=0" 23#endif 24 25cpu_reset_prologue neoverse_v2 26 27workaround_reset_start neoverse_v2, ERRATUM(2618597), ERRATA_V2_2618597 28 /* Disable retention control for WFI and WFE. */ 29 mrs x0, NEOVERSE_V2_CPUPWRCTLR_EL1 30 bfi x0, xzr, #NEOVERSE_V2_CPUPWRCTLR_EL1_WFI_RET_CTRL_SHIFT, \ 31 #NEOVERSE_V2_CPUPWRCTLR_EL1_WFI_RET_CTRL_WIDTH 32 bfi x0, xzr, #NEOVERSE_V2_CPUPWRCTLR_EL1_WFE_RET_CTRL_SHIFT, \ 33 #NEOVERSE_V2_CPUPWRCTLR_EL1_WFE_RET_CTRL_WIDTH 34 msr NEOVERSE_V2_CPUPWRCTLR_EL1, x0 35workaround_reset_end neoverse_v2, ERRATUM(2618597) 36 37check_erratum_ls neoverse_v2, ERRATUM(2618597), CPU_REV(0, 1) 38 39workaround_reset_start neoverse_v2, ERRATUM(2662553), ERRATA_V2_2662553 40 sysreg_bitfield_insert NEOVERSE_V2_CPUECTLR2_EL1, NEOVERSE_V2_CPUECTLR2_EL1_TXREQ_STATIC_FULL, \ 41 NEOVERSE_V2_CPUECTLR2_EL1_TXREQ_LSB, NEOVERSE_V2_CPUECTLR2_EL1_TXREQ_WIDTH 42workaround_reset_end neoverse_v2, ERRATUM(2662553) 43 44check_erratum_ls neoverse_v2, ERRATUM(2662553), CPU_REV(0, 1) 45 46workaround_reset_start neoverse_v2, ERRATUM(2719105), ERRATA_V2_2719105 47 sysreg_bit_set NEOVERSE_V2_CPUACTLR2_EL1, NEOVERSE_V2_CPUACTLR2_EL1_BIT_0 48workaround_reset_end neoverse_v2, ERRATUM(2719105) 49 50check_erratum_ls neoverse_v2, ERRATUM(2719105), CPU_REV(0, 1) 51 52workaround_reset_start neoverse_v2, ERRATUM(2743011), ERRATA_V2_2743011 53 sysreg_bit_set NEOVERSE_V2_CPUACTLR5_EL1, NEOVERSE_V2_CPUACTLR5_EL1_BIT_55 54 sysreg_bit_clear NEOVERSE_V2_CPUACTLR5_EL1, NEOVERSE_V2_CPUACTLR5_EL1_BIT_56 55workaround_reset_end neoverse_v2, ERRATUM(2743011) 56 57check_erratum_ls neoverse_v2, ERRATUM(2743011), CPU_REV(0, 1) 58 59workaround_reset_start neoverse_v2, ERRATUM(2779510), ERRATA_V2_2779510 60 sysreg_bit_set NEOVERSE_V2_CPUACTLR3_EL1, NEOVERSE_V2_CPUACTLR3_EL1_BIT_47 61workaround_reset_end neoverse_v2, ERRATUM(2779510) 62 63check_erratum_ls neoverse_v2, ERRATUM(2779510), CPU_REV(0, 1) 64 65workaround_runtime_start neoverse_v2, ERRATUM(2801372), ERRATA_V2_2801372 66 /* dsb before isb of power down sequence */ 67 dsb sy 68workaround_runtime_end neoverse_v2, ERRATUM(2801372), ERRATA_V2_2801372 69 70check_erratum_ls neoverse_v2, ERRATUM(2801372), CPU_REV(0, 1) 71 72workaround_reset_start neoverse_v2, CVE(2022,23960), WORKAROUND_CVE_2022_23960 73#if IMAGE_BL31 74 /* 75 * The Neoverse-V2 generic vectors are overridden to apply errata 76 * mitigation on exception entry from lower ELs. 77 */ 78 override_vector_table wa_cve_vbar_neoverse_v2 79#endif /* IMAGE_BL31 */ 80workaround_reset_end neoverse_v2, CVE(2022,23960) 81 82check_erratum_chosen neoverse_v2, CVE(2022, 23960), WORKAROUND_CVE_2022_23960 83 84/* Disable hardware page aggregation. Enables mitigation for `CVE-2024-5660` */ 85workaround_reset_start neoverse_v2, CVE(2024, 5660), WORKAROUND_CVE_2024_5660 86 sysreg_bit_set NEOVERSE_V2_CPUECTLR_EL1, BIT(46) 87workaround_reset_end neoverse_v2, CVE(2024, 5660) 88 89check_erratum_ls neoverse_v2, CVE(2024, 5660), CPU_REV(0, 2) 90 91#if WORKAROUND_CVE_2022_23960 92 wa_cve_2022_23960_bhb_vector_table NEOVERSE_V2_BHB_LOOP_COUNT, neoverse_v2 93#endif /* WORKAROUND_CVE_2022_23960 */ 94 95workaround_reset_start neoverse_v2, CVE(2024, 7881), WORKAROUND_CVE_2024_7881 96 /* --------------------------------- 97 * Sets BIT41 of CPUACTLR6_EL1 which 98 * disables L1 Data cache prefetcher 99 * --------------------------------- 100 */ 101 sysreg_bit_set NEOVERSE_V2_CPUACTLR6_EL1, BIT(41) 102workaround_reset_end neoverse_v2, CVE(2024, 7881) 103 104check_erratum_chosen neoverse_v2, CVE(2024, 7881), WORKAROUND_CVE_2024_7881 105 106 /* ---------------------------------------------------- 107 * HW will do the cache maintenance while powering down 108 * ---------------------------------------------------- 109 */ 110func neoverse_v2_core_pwr_dwn 111 /* --------------------------------------------------- 112 * Enable CPU power down bit in power control register 113 * --------------------------------------------------- 114 */ 115 sysreg_bit_set NEOVERSE_V2_CPUPWRCTLR_EL1, NEOVERSE_V2_CPUPWRCTLR_EL1_CORE_PWRDN_BIT 116 apply_erratum neoverse_v2, ERRATUM(2801372), ERRATA_V2_2801372, NO_GET_CPU_REV 117 118 isb 119 ret 120endfunc neoverse_v2_core_pwr_dwn 121 122cpu_reset_func_start neoverse_v2 123 /* Disable speculative loads */ 124 msr SSBS, xzr 125 126#if NEOVERSE_Vx_EXTERNAL_LLC 127 /* Some systems may have External LLC, core needs to be made aware */ 128 sysreg_bit_set NEOVERSE_V2_CPUECTLR_EL1, NEOVERSE_V2_CPUECTLR_EL1_EXTLLC_BIT 129#endif 130cpu_reset_func_end neoverse_v2 131 132 /* --------------------------------------------- 133 * This function provides Neoverse V2- 134 * specific register information for crash 135 * reporting. It needs to return with x6 136 * pointing to a list of register names in ascii 137 * and x8 - x15 having values of registers to be 138 * reported. 139 * --------------------------------------------- 140 */ 141.section .rodata.neoverse_v2_regs, "aS" 142neoverse_v2_regs: /* The ascii list of register names to be reported */ 143 .asciz "cpuectlr_el1", "" 144 145func neoverse_v2_cpu_reg_dump 146 adr x6, neoverse_v2_regs 147 mrs x8, NEOVERSE_V2_CPUECTLR_EL1 148 ret 149endfunc neoverse_v2_cpu_reg_dump 150 151declare_cpu_ops_wa_4 neoverse_v2, NEOVERSE_V2_MIDR, \ 152 neoverse_v2_reset_func, \ 153 CPU_NO_EXTRA1_FUNC, \ 154 CPU_NO_EXTRA2_FUNC, \ 155 CPU_NO_EXTRA3_FUNC, \ 156 check_erratum_neoverse_v2_7881, \ 157 neoverse_v2_core_pwr_dwn 158