1/* 2 * Copyright (c) 2019-2025, Arm Limited. All rights reserved. 3 * 4 * SPDX-License-Identifier: BSD-3-Clause 5 */ 6 7#include <arch.h> 8#include <asm_macros.S> 9#include <common/bl_common.h> 10#include <cortex_a76ae.h> 11#include <cpu_macros.S> 12#include "wa_cve_2022_23960_bhb_vector.S" 13 14/* Hardware handled coherency */ 15#if HW_ASSISTED_COHERENCY == 0 16#error "Cortex-A76AE must be compiled with HW_ASSISTED_COHERENCY enabled" 17#endif 18 19/* 64-bit only core */ 20#if CTX_INCLUDE_AARCH32_REGS == 1 21#error "Cortex-A76AE supports only AArch64. Compile with CTX_INCLUDE_AARCH32_REGS=0" 22#endif 23 24cpu_reset_prologue cortex_a76ae 25 26#if WORKAROUND_CVE_2022_23960 27 wa_cve_2022_23960_bhb_vector_table CORTEX_A76AE_BHB_LOOP_COUNT, cortex_a76ae 28#endif /* WORKAROUND_CVE_2022_23960 */ 29 30check_erratum_chosen cortex_a76ae, CVE(2022, 23960), WORKAROUND_CVE_2022_23960 31 32workaround_reset_start cortex_a76ae, CVE(2022, 23960), WORKAROUND_CVE_2022_23960 33#if IMAGE_BL31 34 /* 35 * The Cortex-A76ae generic vectors are overridden to apply errata 36 * mitigation on exception entry from lower ELs. 37 */ 38 override_vector_table wa_cve_vbar_cortex_a76ae 39 isb 40#endif /* IMAGE_BL31 */ 41workaround_reset_end cortex_a76ae, CVE(2022, 23960) 42 43cpu_reset_func_start cortex_a76ae 44cpu_reset_func_end cortex_a76ae 45 46 /* ---------------------------------------------------- 47 * HW will do the cache maintenance while powering down 48 * ---------------------------------------------------- 49 */ 50func cortex_a76ae_core_pwr_dwn 51 sysreg_bit_set CORTEX_A76AE_CPUPWRCTLR_EL1, CORTEX_A76AE_CORE_PWRDN_EN_MASK 52 isb 53 ret 54endfunc cortex_a76ae_core_pwr_dwn 55 56 /* --------------------------------------------- 57 * This function provides cortex_a76ae specific 58 * register information for crash reporting. 59 * It needs to return with x6 pointing to 60 * a list of register names in ascii and 61 * x8 - x15 having values of registers to be 62 * reported. 63 * --------------------------------------------- 64 */ 65.section .rodata.cortex_a76ae_regs, "aS" 66cortex_a76ae_regs: /* The ASCII list of register names to be reported */ 67 .asciz "cpuectlr_el1", "" 68 69func cortex_a76ae_cpu_reg_dump 70 adr x6, cortex_a76ae_regs 71 mrs x8, CORTEX_A76AE_CPUECTLR_EL1 72 ret 73endfunc cortex_a76ae_cpu_reg_dump 74 75declare_cpu_ops cortex_a76ae, CORTEX_A76AE_MIDR, cortex_a76ae_reset_func, \ 76 cortex_a76ae_core_pwr_dwn 77