1/* 2 * Copyright (c) 2022-2025, Arm Limited. All rights reserved. 3 * 4 * SPDX-License-Identifier: BSD-3-Clause 5 */ 6 7#include <arch.h> 8#include <asm_macros.S> 9#include <common/bl_common.h> 10#include <neoverse_v3.h> 11#include <cpu_macros.S> 12#include <plat_macros.S> 13#include "wa_cve_2022_23960_bhb_vector.S" 14 15/* Hardware handled coherency */ 16#if HW_ASSISTED_COHERENCY == 0 17#error "Neoverse V3 must be compiled with HW_ASSISTED_COHERENCY enabled" 18#endif 19 20/* 64-bit only core */ 21#if CTX_INCLUDE_AARCH32_REGS == 1 22#error "Neoverse V3 supports only AArch64. Compile with CTX_INCLUDE_AARCH32_REGS=0" 23#endif 24 25.global check_erratum_neoverse_v3_3701767 26 27add_erratum_entry neoverse_v3, ERRATUM(3701767), ERRATA_V3_3701767, NO_APPLY_AT_RESET 28 29check_erratum_ls neoverse_v3, ERRATUM(3701767), CPU_REV(0, 2) 30 31workaround_reset_start neoverse_v3, ERRATUM(2970647), ERRATA_V3_2970647 32 /* Add ISB before MRS reads of MPIDR_EL1/MIDR_EL1 */ 33 ldr x0, =0x1 34 msr S3_6_c15_c8_0, x0 /* msr CPUPSELR_EL3, X0 */ 35 ldr x0, =0xd5380000 36 msr S3_6_c15_c8_2, x0 /* msr CPUPOR_EL3, X0 */ 37 ldr x0, =0xFFFFFF40 38 msr S3_6_c15_c8_3,x0 /* msr CPUPMR_EL3, X0 */ 39 ldr x0, =0x000080010033f 40 msr S3_6_c15_c8_1, x0 /* msr CPUPCR_EL3, X0 */ 41 isb 42workaround_reset_end neoverse_v3, ERRATUM(2970647) 43 44check_erratum_ls neoverse_v3, ERRATUM(2970647), CPU_REV(0, 0) 45 46#if WORKAROUND_CVE_2022_23960 47 wa_cve_2022_23960_bhb_vector_table NEOVERSE_V3_BHB_LOOP_COUNT, neoverse_v3 48#endif /* WORKAROUND_CVE_2022_23960 */ 49 50/* Disable hardware page aggregation. Enables mitigation for `CVE-2024-5660` */ 51workaround_reset_start neoverse_v3, CVE(2024, 5660), WORKAROUND_CVE_2024_5660 52 sysreg_bit_set NEOVERSE_V3_CPUECTLR_EL1, BIT(46) 53workaround_reset_end neoverse_v3, CVE(2024, 5660) 54 55check_erratum_ls neoverse_v3, CVE(2024, 5660), CPU_REV(0, 1) 56 57workaround_reset_start neoverse_v3, CVE(2022,23960), WORKAROUND_CVE_2022_23960 58#if IMAGE_BL31 59 /* 60 * The Neoverse V3 generic vectors are overridden to apply errata 61 * mitigation on exception entry from lower ELs. 62 */ 63 override_vector_table wa_cve_vbar_neoverse_v3 64 65#endif /* IMAGE_BL31 */ 66workaround_reset_end neoverse_v3, CVE(2022,23960) 67 68check_erratum_chosen neoverse_v3, CVE(2022, 23960), WORKAROUND_CVE_2022_23960 69 70workaround_reset_start neoverse_v3, CVE(2024, 7881), WORKAROUND_CVE_2024_7881 71 /* --------------------------------- 72 * Sets BIT41 of CPUACTLR6_EL1 which 73 * disables L1 Data cache prefetcher 74 * --------------------------------- 75 */ 76 sysreg_bit_set NEOVERSE_V3_CPUACTLR6_EL1, BIT(41) 77workaround_reset_end neoverse_v3, CVE(2024, 7881) 78 79check_erratum_chosen neoverse_v3, CVE(2024, 7881), WORKAROUND_CVE_2024_7881 80 81 /* --------------------------------------------- 82 * HW will do the cache maintenance while powering down 83 * --------------------------------------------- 84 */ 85func neoverse_v3_core_pwr_dwn 86 /* --------------------------------------------- 87 * Enable CPU power down bit in power control register 88 * --------------------------------------------- 89 */ 90 sysreg_bit_set NEOVERSE_V3_CPUPWRCTLR_EL1, \ 91 NEOVERSE_V3_CPUPWRCTLR_EL1_CORE_PWRDN_BIT 92 93 isb 94 ret 95endfunc neoverse_v3_core_pwr_dwn 96 97cpu_reset_func_start neoverse_v3 98 /* Disable speculative loads */ 99 msr SSBS, xzr 100cpu_reset_func_end neoverse_v3 101 102 /* --------------------------------------------- 103 * This function provides Neoverse V3 specific 104 * register information for crash reporting. 105 * It needs to return with x6 pointing to 106 * a list of register names in ascii and 107 * x8 - x15 having values of registers to be 108 * reported. 109 * --------------------------------------------- 110 */ 111.section .rodata.neoverse_v3_regs, "aS" 112neoverse_v3_regs: /* The ascii list of register names to be reported */ 113 .asciz "cpuectlr_el1", "" 114 115func neoverse_v3_cpu_reg_dump 116 adr x6, neoverse_v3_regs 117 mrs x8, NEOVERSE_V3_CPUECTLR_EL1 118 ret 119endfunc neoverse_v3_cpu_reg_dump 120 121declare_cpu_ops neoverse_v3, NEOVERSE_V3_VNAE_MIDR, \ 122 neoverse_v3_reset_func, \ 123 neoverse_v3_core_pwr_dwn 124 125declare_cpu_ops_wa_4 neoverse_v3, NEOVERSE_V3_MIDR, \ 126 neoverse_v3_reset_func, \ 127 CPU_NO_EXTRA1_FUNC, \ 128 CPU_NO_EXTRA2_FUNC, \ 129 CPU_NO_EXTRA3_FUNC, \ 130 check_erratum_neoverse_v3_7881, \ 131 neoverse_v3_core_pwr_dwn 132