1 /* 2 * Copyright (c) 2020-2025, Arm Limited and Contributors. All rights reserved. 3 * 4 * SPDX-License-Identifier: BSD-3-Clause 5 */ 6 7 #include <assert.h> 8 9 #include <libfdt.h> 10 #include <tc_plat.h> 11 12 #include <arch_helpers.h> 13 #include <common/bl_common.h> 14 #include <common/debug.h> 15 #include <drivers/arm/css/css_mhu_doorbell.h> 16 #include <drivers/arm/css/scmi.h> 17 #include <drivers/arm/sbsa.h> 18 #include <lib/fconf/fconf.h> 19 #include <lib/fconf/fconf_dyn_cfg_getter.h> 20 #include <plat/arm/common/plat_arm.h> 21 #include <plat/common/platform.h> 22 23 #ifdef PLATFORM_TEST_TFM_TESTSUITE 24 #include <psa/crypto_platform.h> 25 #include <psa/crypto_types.h> 26 #include <psa/crypto_values.h> 27 #endif /* PLATFORM_TEST_TFM_TESTSUITE */ 28 #include <psa/error.h> 29 30 #include <plat/common/platform.h> 31 #include <tc_rse_comms.h> 32 33 #ifdef PLATFORM_TEST_TFM_TESTSUITE 34 /* 35 * We pretend using an external RNG (through MBEDTLS_PSA_CRYPTO_EXTERNAL_RNG 36 * mbedTLS config option) so we need to provide an implementation of 37 * mbedtls_psa_external_get_random(). Provide a fake one, since we do not 38 * actually use any of external RNG and this function is only needed during 39 * the execution of TF-M testsuite during exporting the public part of the 40 * delegated attestation key. 41 */ 42 psa_status_t mbedtls_psa_external_get_random( 43 mbedtls_psa_external_random_context_t *context, 44 uint8_t *output, size_t output_size, 45 size_t *output_length) 46 { 47 for (size_t i = 0U; i < output_size; i++) { 48 output[i] = (uint8_t)(read_cntpct_el0() & 0xFFU); 49 } 50 51 *output_length = output_size; 52 53 return PSA_SUCCESS; 54 } 55 #endif /* PLATFORM_TEST_TFM_TESTSUITE */ 56 57 static scmi_channel_plat_info_t tc_scmi_plat_info = { 58 .scmi_mbx_mem = CSS_SCMI_PAYLOAD_BASE, 59 .db_reg_addr = PLAT_CSS_MHU_BASE + MHU_V3_SENDER_REG_SET(0), 60 .db_preserve_mask = 0xfffffffe, 61 .db_modify_mask = 0x1, 62 .ring_doorbell = &mhu_ring_doorbell, 63 }; 64 65 /* the bottom 3 AMU group 1 counters */ 66 #define MPMM_GEARS ((1 << 0) | (1 << 1) | (1 << 2)) 67 68 uint16_t plat_amu_aux_enables[PLATFORM_CORE_COUNT] = { 69 MPMM_GEARS, MPMM_GEARS, MPMM_GEARS, MPMM_GEARS, 70 MPMM_GEARS, MPMM_GEARS, MPMM_GEARS, MPMM_GEARS, 71 #if PLATFORM_CORE_COUNT == 14 72 MPMM_GEARS, MPMM_GEARS, MPMM_GEARS, MPMM_GEARS, 73 MPMM_GEARS, MPMM_GEARS 74 #endif 75 }; 76 77 #if (TARGET_PLATFORM == 3) || (TARGET_PLATFORM == 4) 78 static void enable_ns_mcn_pmu(void) 79 { 80 /* 81 * Enable non-secure access to MCN PMU registers 82 */ 83 for (int i = 0; i < MCN_INSTANCES; i++) { 84 uintptr_t mcn_scr = MCN_MICROARCH_BASE_ADDR(i) + 85 MCN_SCR_OFFSET; 86 mmio_setbits_32(mcn_scr, 1 << MCN_SCR_PMU_BIT); 87 } 88 } 89 #endif /* (TARGET_PLATFORM == 3) || (TARGET_PLATFORM == 4) */ 90 91 #if TARGET_PLATFORM == 3 92 static void set_mcn_slc_alloc_mode(void) 93 { 94 /* 95 * SLC WRALLOCMODE and RDALLOCMODE are configured by default to 96 * 0b01 (always alloc), configure both to 0b10 (use bus signal 97 * attribute from interface). 98 */ 99 for (int i = 0; i < MCN_INSTANCES; i++) { 100 uintptr_t slccfg_ctl_ns = MCN_MPAM_NS_BASE_ADDR(i) + 101 MPAM_SLCCFG_CTL_OFFSET; 102 uintptr_t slccfg_ctl_s = MCN_MPAM_S_BASE_ADDR(i) + 103 MPAM_SLCCFG_CTL_OFFSET; 104 105 mmio_clrsetbits_32(slccfg_ctl_ns, 106 (SLC_RDALLOCMODE_MASK | SLC_WRALLOCMODE_MASK), 107 (SLC_ALLOC_BUS_SIGNAL_ATTR << SLC_RDALLOCMODE_SHIFT) | 108 (SLC_ALLOC_BUS_SIGNAL_ATTR << SLC_WRALLOCMODE_SHIFT)); 109 mmio_clrsetbits_32(slccfg_ctl_s, 110 (SLC_RDALLOCMODE_MASK | SLC_WRALLOCMODE_MASK), 111 (SLC_ALLOC_BUS_SIGNAL_ATTR << SLC_RDALLOCMODE_SHIFT) | 112 (SLC_ALLOC_BUS_SIGNAL_ATTR << SLC_WRALLOCMODE_SHIFT)); 113 } 114 } 115 #endif 116 117 void bl31_platform_setup(void) 118 { 119 psa_status_t status; 120 121 tc_bl31_common_platform_setup(); 122 #if (TARGET_PLATFORM == 3) || (TARGET_PLATFORM == 4) 123 enable_ns_mcn_pmu(); 124 #endif /* (TARGET_PLATFORM == 3) || (TARGET_PLATFORM == 4) */ 125 #if TARGET_PLATFORM == 3 126 set_mcn_slc_alloc_mode(); 127 plat_arm_ni_setup(NCI_BASE_ADDR); 128 #endif 129 130 /* Initialise RSE communication channel */ 131 status = plat_rse_comms_init(); 132 if (status != PSA_SUCCESS) { 133 ERROR("Failed to initialize RSE communication channel - psa_status = %d\n", status); 134 } 135 } 136 137 scmi_channel_plat_info_t *plat_css_get_scmi_info(unsigned int channel_id __unused) 138 { 139 140 return &tc_scmi_plat_info; 141 142 } 143 144 void bl31_early_platform_setup2(u_register_t arg0, u_register_t arg1, 145 u_register_t arg2, u_register_t arg3) 146 { 147 /* Initialize the console to provide early debug support */ 148 arm_console_boot_init(); 149 150 arm_bl31_early_platform_setup(arg0, arg1, arg2, arg3); 151 152 #if !TRANSFER_LIST 153 /* Fill the properties struct with the info from the config dtb */ 154 fconf_populate("FW_CONFIG", arg1); 155 #endif 156 } 157 158 #ifdef PLATFORM_TESTS 159 static __dead2 void tc_run_platform_tests(void) 160 { 161 int tests_failed; 162 163 printf("\nStarting platform tests...\n"); 164 165 #ifdef PLATFORM_TEST_NV_COUNTERS 166 tests_failed = nv_counter_test(); 167 #elif PLATFORM_TEST_ROTPK 168 tests_failed = rotpk_test(); 169 #elif PLATFORM_TEST_TFM_TESTSUITE 170 tests_failed = run_platform_tests(); 171 #endif 172 173 printf("Platform tests %s.\n", 174 (tests_failed != 0) ? "failed" : "succeeded"); 175 176 /* Suspend booting, no matter the tests outcome. */ 177 printf("Suspend booting...\n"); 178 plat_error_handler(-1); 179 } 180 #endif 181 182 void tc_bl31_common_platform_setup(void) 183 { 184 arm_bl31_platform_setup(); 185 186 #ifdef PLATFORM_TESTS 187 tc_run_platform_tests(); 188 #endif 189 } 190 191 const plat_psci_ops_t *plat_arm_psci_override_pm_ops(plat_psci_ops_t *ops) 192 { 193 return css_scmi_override_pm_ops(ops); 194 } 195 196 void __init bl31_plat_arch_setup(void) 197 { 198 arm_bl31_plat_arch_setup(); 199 200 /* 201 * When TRANSFER_LIST is enabled, HW_CONFIG is included in Transfer List 202 * as an entry with the tag TL_TAG_FDT. In this case, the configuration 203 * is already available, so the fconf_populate mechanism is not needed. 204 * The code block below is only required when TRANSFER_LIST is not used. 205 */ 206 #if !TRANSFER_LIST 207 /* HW_CONFIG was also loaded by BL2 */ 208 const struct dyn_cfg_dtb_info_t *hw_config_info; 209 210 hw_config_info = FCONF_GET_PROPERTY(dyn_cfg, dtb, HW_CONFIG_ID); 211 assert(hw_config_info != NULL); 212 213 fconf_populate("HW_CONFIG", hw_config_info->config_addr); 214 #endif 215 } 216 217 #if defined(SPD_spmd) && (SPMC_AT_EL3 == 0) 218 void tc_bl31_plat_runtime_setup(void) 219 { 220 /* Start secure watchdog timer. */ 221 plat_arm_secure_wdt_start(); 222 223 arm_bl31_plat_runtime_setup(); 224 } 225 226 void bl31_plat_runtime_setup(void) 227 { 228 tc_bl31_plat_runtime_setup(); 229 } 230 231 /* 232 * Platform handler for Group0 secure interrupt. 233 */ 234 int plat_spmd_handle_group0_interrupt(uint32_t intid) 235 { 236 /* Trusted Watchdog timer is the only source of Group0 interrupt now. */ 237 if (intid == SBSA_SECURE_WDOG_INTID) { 238 /* Refresh the timer. */ 239 plat_arm_secure_wdt_refresh(); 240 241 return 0; 242 } 243 244 return -1; 245 } 246 #endif /*defined(SPD_spmd) && (SPMC_AT_EL3 == 0)*/ 247