1 /* 2 * Copyright (c) 2013-2025, Arm Limited and Contributors. All rights reserved. 3 * Copyright (c) 2022, NVIDIA Corporation. All rights reserved. 4 * 5 * SPDX-License-Identifier: BSD-3-Clause 6 */ 7 8 #include <assert.h> 9 #include <stdbool.h> 10 #include <string.h> 11 12 #include <platform_def.h> 13 14 #include <arch.h> 15 #include <arch_helpers.h> 16 #include <arch_features.h> 17 #include <bl31/interrupt_mgmt.h> 18 #include <common/bl_common.h> 19 #include <common/debug.h> 20 #include <context.h> 21 #include <drivers/arm/gicv3.h> 22 #include <lib/cpus/cpu_ops.h> 23 #include <lib/cpus/errata.h> 24 #include <lib/el3_runtime/context_mgmt.h> 25 #include <lib/el3_runtime/cpu_data.h> 26 #include <lib/el3_runtime/pubsub_events.h> 27 #include <lib/extensions/amu.h> 28 #include <lib/extensions/brbe.h> 29 #include <lib/extensions/debug_v8p9.h> 30 #include <lib/extensions/fgt2.h> 31 #include <lib/extensions/fpmr.h> 32 #include <lib/extensions/mpam.h> 33 #include <lib/extensions/pauth.h> 34 #include <lib/extensions/pmuv3.h> 35 #include <lib/extensions/sme.h> 36 #include <lib/extensions/spe.h> 37 #include <lib/extensions/sve.h> 38 #include <lib/extensions/sysreg128.h> 39 #include <lib/extensions/sys_reg_trace.h> 40 #include <lib/extensions/tcr2.h> 41 #include <lib/extensions/trbe.h> 42 #include <lib/extensions/trf.h> 43 #include <lib/utils.h> 44 45 #if ENABLE_FEAT_TWED 46 /* Make sure delay value fits within the range(0-15) */ 47 CASSERT(((TWED_DELAY & ~SCR_TWEDEL_MASK) == 0U), assert_twed_delay_value_check); 48 #endif /* ENABLE_FEAT_TWED */ 49 50 per_world_context_t per_world_context[CPU_DATA_CONTEXT_NUM]; 51 52 static void manage_extensions_nonsecure(cpu_context_t *ctx); 53 static void manage_extensions_secure(cpu_context_t *ctx); 54 55 #if ((IMAGE_BL1) || (IMAGE_BL31 && (!CTX_INCLUDE_EL2_REGS))) 56 static void setup_el1_context(cpu_context_t *ctx, const struct entry_point_info *ep) 57 { 58 u_register_t sctlr_elx, actlr_elx; 59 60 /* 61 * Initialise SCTLR_EL1 to the reset value corresponding to the target 62 * execution state setting all fields rather than relying on the hw. 63 * Some fields have architecturally UNKNOWN reset values and these are 64 * set to zero. 65 * 66 * SCTLR.EE: Endianness is taken from the entrypoint attributes. 67 * 68 * SCTLR.M, SCTLR.C and SCTLR.I: These fields must be zero (as 69 * required by PSCI specification) 70 */ 71 sctlr_elx = (EP_GET_EE(ep->h.attr) != 0U) ? SCTLR_EE_BIT : 0UL; 72 if (GET_RW(ep->spsr) == MODE_RW_64) { 73 sctlr_elx |= SCTLR_EL1_RES1; 74 } else { 75 /* 76 * If the target execution state is AArch32 then the following 77 * fields need to be set. 78 * 79 * SCTRL_EL1.nTWE: Set to one so that EL0 execution of WFE 80 * instructions are not trapped to EL1. 81 * 82 * SCTLR_EL1.nTWI: Set to one so that EL0 execution of WFI 83 * instructions are not trapped to EL1. 84 * 85 * SCTLR_EL1.CP15BEN: Set to one to enable EL0 execution of the 86 * CP15DMB, CP15DSB, and CP15ISB instructions. 87 */ 88 sctlr_elx |= SCTLR_AARCH32_EL1_RES1 | SCTLR_CP15BEN_BIT 89 | SCTLR_NTWI_BIT | SCTLR_NTWE_BIT; 90 } 91 92 /* 93 * If workaround of errata 764081 for Cortex-A75 is used then set 94 * SCTLR_EL1.IESB to enable Implicit Error Synchronization Barrier. 95 */ 96 if (errata_a75_764081_applies()) { 97 sctlr_elx |= SCTLR_IESB_BIT; 98 } 99 100 /* Store the initialised SCTLR_EL1 value in the cpu_context */ 101 write_ctx_sctlr_el1_reg_errata(ctx, sctlr_elx); 102 103 /* 104 * Base the context ACTLR_EL1 on the current value, as it is 105 * implementation defined. The context restore process will write 106 * the value from the context to the actual register and can cause 107 * problems for processor cores that don't expect certain bits to 108 * be zero. 109 */ 110 actlr_elx = read_actlr_el1(); 111 write_el1_ctx_common(get_el1_sysregs_ctx(ctx), actlr_el1, actlr_elx); 112 } 113 #endif /* (IMAGE_BL1) || (IMAGE_BL31 && (!CTX_INCLUDE_EL2_REGS)) */ 114 115 /****************************************************************************** 116 * This function performs initializations that are specific to SECURE state 117 * and updates the cpu context specified by 'ctx'. 118 *****************************************************************************/ 119 static void setup_secure_context(cpu_context_t *ctx, const struct entry_point_info *ep) 120 { 121 u_register_t scr_el3; 122 el3_state_t *state; 123 124 state = get_el3state_ctx(ctx); 125 scr_el3 = read_ctx_reg(state, CTX_SCR_EL3); 126 127 #if defined(IMAGE_BL31) && !defined(SPD_spmd) 128 /* 129 * SCR_EL3.IRQ, SCR_EL3.FIQ: Enable the physical FIQ and IRQ routing as 130 * indicated by the interrupt routing model for BL31. 131 */ 132 scr_el3 |= get_scr_el3_from_routing_model(SECURE); 133 #endif 134 135 /* Allow access to Allocation Tags when FEAT_MTE2 is implemented and enabled. */ 136 if (is_feat_mte2_supported()) { 137 scr_el3 |= SCR_ATA_BIT; 138 } 139 140 write_ctx_reg(state, CTX_SCR_EL3, scr_el3); 141 142 /* 143 * Initialize EL1 context registers unless SPMC is running 144 * at S-EL2. 145 */ 146 #if (!SPMD_SPM_AT_SEL2) 147 setup_el1_context(ctx, ep); 148 #endif 149 150 manage_extensions_secure(ctx); 151 } 152 153 #if ENABLE_RME && IMAGE_BL31 154 /****************************************************************************** 155 * This function performs initializations that are specific to REALM state 156 * and updates the cpu context specified by 'ctx'. 157 * 158 * NOTE: any changes to this function must be verified by an RMMD maintainer. 159 *****************************************************************************/ 160 static void setup_realm_context(cpu_context_t *ctx, const struct entry_point_info *ep) 161 { 162 u_register_t scr_el3; 163 el3_state_t *state; 164 el2_sysregs_t *el2_ctx; 165 166 state = get_el3state_ctx(ctx); 167 scr_el3 = read_ctx_reg(state, CTX_SCR_EL3); 168 el2_ctx = get_el2_sysregs_ctx(ctx); 169 170 scr_el3 |= SCR_NS_BIT | SCR_NSE_BIT; 171 172 write_el2_ctx_common(el2_ctx, spsr_el2, SPSR_EL2_REALM); 173 174 /* CSV2 version 2 and above */ 175 if (is_feat_csv2_2_supported()) { 176 /* Enable access to the SCXTNUM_ELx registers. */ 177 scr_el3 |= SCR_EnSCXT_BIT; 178 } 179 180 if (is_feat_sctlr2_supported()) { 181 /* Set the SCTLR2En bit in SCR_EL3 to enable access to 182 * SCTLR2_ELx registers. 183 */ 184 scr_el3 |= SCR_SCTLR2En_BIT; 185 } 186 187 if (is_feat_d128_supported()) { 188 /* 189 * Set the D128En bit in SCR_EL3 to enable access to 128-bit 190 * versions of TTBR0_EL1, TTBR1_EL1, RCWMASK_EL1, RCWSMASK_EL1, 191 * PAR_EL1 and TTBR1_EL2, TTBR0_EL2 and VTTBR_EL2 registers. 192 */ 193 scr_el3 |= SCR_D128En_BIT; 194 } 195 196 write_ctx_reg(state, CTX_SCR_EL3, scr_el3); 197 198 if (is_feat_fgt2_supported()) { 199 fgt2_enable(ctx); 200 } 201 202 if (is_feat_debugv8p9_supported()) { 203 debugv8p9_extended_bp_wp_enable(ctx); 204 } 205 206 if (is_feat_brbe_supported()) { 207 brbe_enable(ctx); 208 } 209 210 /* 211 * Enable access to TPIDR2_EL0 if SME/SME2 is enabled for Non Secure world. 212 */ 213 if (is_feat_sme_supported()) { 214 sme_enable(ctx); 215 } 216 217 if (is_feat_spe_supported()) { 218 spe_disable_realm(ctx); 219 } 220 221 if (is_feat_trbe_supported()) { 222 trbe_disable_realm(ctx); 223 } 224 } 225 #endif /* ENABLE_RME && IMAGE_BL31 */ 226 227 /****************************************************************************** 228 * This function performs initializations that are specific to NON-SECURE state 229 * and updates the cpu context specified by 'ctx'. 230 *****************************************************************************/ 231 static void setup_ns_context(cpu_context_t *ctx, const struct entry_point_info *ep) 232 { 233 u_register_t scr_el3; 234 el3_state_t *state; 235 236 state = get_el3state_ctx(ctx); 237 scr_el3 = read_ctx_reg(state, CTX_SCR_EL3); 238 239 /* SCR_NS: Set the NS bit */ 240 scr_el3 |= SCR_NS_BIT; 241 242 /* Allow access to Allocation Tags when FEAT_MTE2 is implemented and enabled. */ 243 if (is_feat_mte2_supported()) { 244 scr_el3 |= SCR_ATA_BIT; 245 } 246 247 /* 248 * Pointer Authentication feature, if present, is always enabled by 249 * default for Non secure lower exception levels. We do not have an 250 * explicit flag to set it. To prevent the leakage between the worlds 251 * during world switch, we enable it only for the non-secure world. 252 * 253 * CTX_INCLUDE_PAUTH_REGS flag, is explicitly used to enable for lower 254 * exception levels of secure and realm worlds. 255 * 256 * If the Secure/realm world wants to use pointer authentication, 257 * CTX_INCLUDE_PAUTH_REGS must be explicitly set to 1, in which case 258 * it will be enabled globally for all the contexts. 259 * 260 * SCR_EL3.API: Set to one to not trap any PAuth instructions at ELs 261 * other than EL3 262 * 263 * SCR_EL3.APK: Set to one to not trap any PAuth key values at ELs other 264 * than EL3 265 */ 266 if (!is_ctx_pauth_supported()) { 267 scr_el3 |= SCR_API_BIT | SCR_APK_BIT; 268 } 269 270 #if HANDLE_EA_EL3_FIRST_NS 271 /* SCR_EL3.EA: Route External Abort and SError Interrupt to EL3. */ 272 scr_el3 |= SCR_EA_BIT; 273 #endif 274 275 #if RAS_TRAP_NS_ERR_REC_ACCESS 276 /* 277 * SCR_EL3.TERR: Trap Error record accesses. Accesses to the RAS ERR 278 * and RAS ERX registers from EL1 and EL2(from any security state) 279 * are trapped to EL3. 280 * Set here to trap only for NS EL1/EL2 281 */ 282 scr_el3 |= SCR_TERR_BIT; 283 #endif 284 285 /* CSV2 version 2 and above */ 286 if (is_feat_csv2_2_supported()) { 287 /* Enable access to the SCXTNUM_ELx registers. */ 288 scr_el3 |= SCR_EnSCXT_BIT; 289 } 290 291 #ifdef IMAGE_BL31 292 /* 293 * SCR_EL3.IRQ, SCR_EL3.FIQ: Enable the physical FIQ and IRQ routing as 294 * indicated by the interrupt routing model for BL31. 295 */ 296 scr_el3 |= get_scr_el3_from_routing_model(NON_SECURE); 297 #endif 298 299 if (is_feat_the_supported()) { 300 /* Set the RCWMASKEn bit in SCR_EL3 to enable access to 301 * RCWMASK_EL1 and RCWSMASK_EL1 registers. 302 */ 303 scr_el3 |= SCR_RCWMASKEn_BIT; 304 } 305 306 if (is_feat_sctlr2_supported()) { 307 /* Set the SCTLR2En bit in SCR_EL3 to enable access to 308 * SCTLR2_ELx registers. 309 */ 310 scr_el3 |= SCR_SCTLR2En_BIT; 311 } 312 313 if (is_feat_d128_supported()) { 314 /* Set the D128En bit in SCR_EL3 to enable access to 128-bit 315 * versions of TTBR0_EL1, TTBR1_EL1, RCWMASK_EL1, RCWSMASK_EL1, 316 * PAR_EL1 and TTBR1_EL2, TTBR0_EL2 and VTTBR_EL2 registers. 317 */ 318 scr_el3 |= SCR_D128En_BIT; 319 } 320 321 if (is_feat_fpmr_supported()) { 322 /* Set the EnFPM bit in SCR_EL3 to enable access to FPMR 323 * register. 324 */ 325 scr_el3 |= SCR_EnFPM_BIT; 326 } 327 328 write_ctx_reg(state, CTX_SCR_EL3, scr_el3); 329 330 /* Initialize EL2 context registers */ 331 #if (CTX_INCLUDE_EL2_REGS && IMAGE_BL31) 332 if (is_feat_hcx_supported()) { 333 /* 334 * Initialize register HCRX_EL2 with its init value. 335 * As the value of HCRX_EL2 is UNKNOWN on reset, there is a 336 * chance that this can lead to unexpected behavior in lower 337 * ELs that have not been updated since the introduction of 338 * this feature if not properly initialized, especially when 339 * it comes to those bits that enable/disable traps. 340 */ 341 write_el2_ctx_hcx(get_el2_sysregs_ctx(ctx), hcrx_el2, 342 HCRX_EL2_INIT_VAL); 343 } 344 345 if (is_feat_fgt_supported()) { 346 /* 347 * Initialize HFG*_EL2 registers with a default value so legacy 348 * systems unaware of FEAT_FGT do not get trapped due to their lack 349 * of initialization for this feature. 350 */ 351 write_el2_ctx_fgt(get_el2_sysregs_ctx(ctx), hfgitr_el2, 352 HFGITR_EL2_INIT_VAL); 353 write_el2_ctx_fgt(get_el2_sysregs_ctx(ctx), hfgrtr_el2, 354 HFGRTR_EL2_INIT_VAL); 355 write_el2_ctx_fgt(get_el2_sysregs_ctx(ctx), hfgwtr_el2, 356 HFGWTR_EL2_INIT_VAL); 357 } 358 #else 359 /* Initialize EL1 context registers */ 360 setup_el1_context(ctx, ep); 361 #endif /* (CTX_INCLUDE_EL2_REGS && IMAGE_BL31) */ 362 363 manage_extensions_nonsecure(ctx); 364 } 365 366 /******************************************************************************* 367 * The following function performs initialization of the cpu_context 'ctx' 368 * for first use that is common to all security states, and sets the 369 * initial entrypoint state as specified by the entry_point_info structure. 370 * 371 * The EE and ST attributes are used to configure the endianness and secure 372 * timer availability for the new execution context. 373 ******************************************************************************/ 374 static void setup_context_common(cpu_context_t *ctx, const entry_point_info_t *ep) 375 { 376 u_register_t scr_el3; 377 u_register_t mdcr_el3; 378 el3_state_t *state; 379 gp_regs_t *gp_regs; 380 381 state = get_el3state_ctx(ctx); 382 383 /* Clear any residual register values from the context */ 384 zeromem(ctx, sizeof(*ctx)); 385 386 /* 387 * The lower-EL context is zeroed so that no stale values leak to a world. 388 * It is assumed that an all-zero lower-EL context is good enough for it 389 * to boot correctly. However, there are very few registers where this 390 * is not true and some values need to be recreated. 391 */ 392 #if (CTX_INCLUDE_EL2_REGS && IMAGE_BL31) 393 el2_sysregs_t *el2_ctx = get_el2_sysregs_ctx(ctx); 394 395 /* 396 * These bits are set in the gicv3 driver. Losing them (especially the 397 * SRE bit) is problematic for all worlds. Henceforth recreate them. 398 */ 399 u_register_t icc_sre_el2_val = ICC_SRE_DIB_BIT | ICC_SRE_DFB_BIT | 400 ICC_SRE_EN_BIT | ICC_SRE_SRE_BIT; 401 write_el2_ctx_common(el2_ctx, icc_sre_el2, icc_sre_el2_val); 402 403 /* 404 * The actlr_el2 register can be initialized in platform's reset handler 405 * and it may contain access control bits (e.g. CLUSTERPMUEN bit). 406 */ 407 write_el2_ctx_common(el2_ctx, actlr_el2, read_actlr_el2()); 408 #endif /* (CTX_INCLUDE_EL2_REGS && IMAGE_BL31) */ 409 410 /* Start with a clean SCR_EL3 copy as all relevant values are set */ 411 scr_el3 = SCR_RESET_VAL; 412 413 /* 414 * SCR_EL3.TWE: Set to zero so that execution of WFE instructions at 415 * EL2, EL1 and EL0 are not trapped to EL3. 416 * 417 * SCR_EL3.TWI: Set to zero so that execution of WFI instructions at 418 * EL2, EL1 and EL0 are not trapped to EL3. 419 * 420 * SCR_EL3.SMD: Set to zero to enable SMC calls at EL1 and above, from 421 * both Security states and both Execution states. 422 * 423 * SCR_EL3.SIF: Set to one to disable secure instruction execution from 424 * Non-secure memory. 425 */ 426 scr_el3 &= ~(SCR_TWE_BIT | SCR_TWI_BIT | SCR_SMD_BIT); 427 428 scr_el3 |= SCR_SIF_BIT; 429 430 /* 431 * SCR_EL3.RW: Set the execution state, AArch32 or AArch64, for next 432 * Exception level as specified by SPSR. 433 */ 434 if (GET_RW(ep->spsr) == MODE_RW_64) { 435 scr_el3 |= SCR_RW_BIT; 436 } 437 438 /* 439 * SCR_EL3.ST: Traps Secure EL1 accesses to the Counter-timer Physical 440 * Secure timer registers to EL3, from AArch64 state only, if specified 441 * by the entrypoint attributes. If SEL2 is present and enabled, the ST 442 * bit always behaves as 1 (i.e. secure physical timer register access 443 * is not trapped) 444 */ 445 if (EP_GET_ST(ep->h.attr) != 0U) { 446 scr_el3 |= SCR_ST_BIT; 447 } 448 449 /* 450 * If FEAT_HCX is enabled, enable access to HCRX_EL2 by setting 451 * SCR_EL3.HXEn. 452 */ 453 if (is_feat_hcx_supported()) { 454 scr_el3 |= SCR_HXEn_BIT; 455 } 456 457 /* 458 * If FEAT_LS64_ACCDATA is enabled, enable access to ACCDATA_EL1 by 459 * setting SCR_EL3.ADEn and allow the ST64BV0 instruction by setting 460 * SCR_EL3.EnAS0. 461 */ 462 if (is_feat_ls64_accdata_supported()) { 463 scr_el3 |= SCR_ADEn_BIT | SCR_EnAS0_BIT; 464 } 465 466 /* 467 * If FEAT_RNG_TRAP is enabled, all reads of the RNDR and RNDRRS 468 * registers are trapped to EL3. 469 */ 470 if (is_feat_rng_trap_supported()) { 471 scr_el3 |= SCR_TRNDR_BIT; 472 } 473 474 #if FAULT_INJECTION_SUPPORT 475 /* Enable fault injection from lower ELs */ 476 scr_el3 |= SCR_FIEN_BIT; 477 #endif 478 479 /* 480 * Enable Pointer Authentication globally for all the worlds. 481 * 482 * SCR_EL3.API: Set to one to not trap any PAuth instructions at ELs 483 * other than EL3 484 * 485 * SCR_EL3.APK: Set to one to not trap any PAuth key values at ELs other 486 * than EL3 487 */ 488 if (is_ctx_pauth_supported()) { 489 scr_el3 |= SCR_API_BIT | SCR_APK_BIT; 490 } 491 492 /* 493 * SCR_EL3.PIEN: Enable permission indirection and overlay 494 * registers for AArch64 if present. 495 */ 496 if (is_feat_sxpie_supported() || is_feat_sxpoe_supported()) { 497 scr_el3 |= SCR_PIEN_BIT; 498 } 499 500 /* 501 * SCR_EL3.GCSEn: Enable GCS registers for AArch64 if present. 502 */ 503 if ((is_feat_gcs_supported()) && (GET_RW(ep->spsr) == MODE_RW_64)) { 504 scr_el3 |= SCR_GCSEn_BIT; 505 } 506 507 /* 508 * SCR_EL3.HCE: Enable HVC instructions if next execution state is 509 * AArch64 and next EL is EL2, or if next execution state is AArch32 and 510 * next mode is Hyp. 511 * SCR_EL3.FGTEn: Enable Fine Grained Virtualization Traps under the 512 * same conditions as HVC instructions and when the processor supports 513 * ARMv8.6-FGT. 514 * SCR_EL3.ECVEn: Enable Enhanced Counter Virtualization (ECV) 515 * CNTPOFF_EL2 register under the same conditions as HVC instructions 516 * and when the processor supports ECV. 517 */ 518 if (((GET_RW(ep->spsr) == MODE_RW_64) && (GET_EL(ep->spsr) == MODE_EL2)) 519 || ((GET_RW(ep->spsr) != MODE_RW_64) 520 && (GET_M32(ep->spsr) == MODE32_hyp))) { 521 scr_el3 |= SCR_HCE_BIT; 522 523 if (is_feat_fgt_supported()) { 524 scr_el3 |= SCR_FGTEN_BIT; 525 } 526 527 if (is_feat_ecv_supported()) { 528 scr_el3 |= SCR_ECVEN_BIT; 529 } 530 } 531 532 /* Enable WFE trap delay in SCR_EL3 if supported and configured */ 533 if (is_feat_twed_supported()) { 534 /* Set delay in SCR_EL3 */ 535 scr_el3 &= ~(SCR_TWEDEL_MASK << SCR_TWEDEL_SHIFT); 536 scr_el3 |= ((TWED_DELAY & SCR_TWEDEL_MASK) 537 << SCR_TWEDEL_SHIFT); 538 539 /* Enable WFE delay */ 540 scr_el3 |= SCR_TWEDEn_BIT; 541 } 542 543 #if IMAGE_BL31 && defined(SPD_spmd) && SPMD_SPM_AT_SEL2 544 /* Enable S-EL2 if FEAT_SEL2 is implemented for all the contexts. */ 545 if (is_feat_sel2_supported()) { 546 scr_el3 |= SCR_EEL2_BIT; 547 } 548 #endif /* (IMAGE_BL31 && defined(SPD_spmd) && SPMD_SPM_AT_SEL2) */ 549 550 if (is_feat_mec_supported()) { 551 scr_el3 |= SCR_MECEn_BIT; 552 } 553 554 /* 555 * Populate EL3 state so that we've the right context 556 * before doing ERET 557 */ 558 write_ctx_reg(state, CTX_SCR_EL3, scr_el3); 559 write_ctx_reg(state, CTX_ELR_EL3, ep->pc); 560 write_ctx_reg(state, CTX_SPSR_EL3, ep->spsr); 561 562 /* Start with a clean MDCR_EL3 copy as all relevant values are set */ 563 mdcr_el3 = MDCR_EL3_RESET_VAL; 564 565 /* --------------------------------------------------------------------- 566 * Initialise MDCR_EL3, setting all fields rather than relying on hw. 567 * Some fields are architecturally UNKNOWN on reset. 568 * 569 * MDCR_EL3.SDD: Set to one to disable AArch64 Secure self-hosted debug. 570 * Debug exceptions, other than Breakpoint Instruction exceptions, are 571 * disabled from all ELs in Secure state. 572 * 573 * MDCR_EL3.SPD32: Set to 0b10 to disable AArch32 Secure self-hosted 574 * privileged debug from S-EL1. 575 * 576 * MDCR_EL3.TDOSA: Set to zero so that EL2 and EL2 System register 577 * access to the powerdown debug registers do not trap to EL3. 578 * 579 * MDCR_EL3.TDA: Set to zero to allow EL0, EL1 and EL2 access to the 580 * debug registers, other than those registers that are controlled by 581 * MDCR_EL3.TDOSA. 582 */ 583 mdcr_el3 |= ((MDCR_SDD_BIT | MDCR_SPD32(MDCR_SPD32_DISABLE)) 584 & ~(MDCR_TDA_BIT | MDCR_TDOSA_BIT)) ; 585 write_ctx_reg(state, CTX_MDCR_EL3, mdcr_el3); 586 587 #if IMAGE_BL31 588 /* Enable FEAT_TRF for Non-Secure and prohibit for Secure state. */ 589 if (is_feat_trf_supported()) { 590 trf_enable(ctx); 591 } 592 593 if (is_feat_tcr2_supported()) { 594 tcr2_enable(ctx); 595 } 596 597 pmuv3_enable(ctx); 598 599 #if CTX_INCLUDE_EL2_REGS 600 /* 601 * Initialize SCTLR_EL2 context register with reset value. 602 */ 603 write_el2_ctx_common(get_el2_sysregs_ctx(ctx), sctlr_el2, SCTLR_EL2_RES1); 604 #endif /* CTX_INCLUDE_EL2_REGS */ 605 #endif /* IMAGE_BL31 */ 606 607 /* 608 * Store the X0-X7 value from the entrypoint into the context 609 * Use memcpy as we are in control of the layout of the structures 610 */ 611 gp_regs = get_gpregs_ctx(ctx); 612 memcpy((void *)gp_regs, (void *)&ep->args, sizeof(aapcs64_params_t)); 613 } 614 615 /******************************************************************************* 616 * Context management library initialization routine. This library is used by 617 * runtime services to share pointers to 'cpu_context' structures for secure 618 * non-secure and realm states. Management of the structures and their associated 619 * memory is not done by the context management library e.g. the PSCI service 620 * manages the cpu context used for entry from and exit to the non-secure state. 621 * The Secure payload dispatcher service manages the context(s) corresponding to 622 * the secure state. It also uses this library to get access to the non-secure 623 * state cpu context pointers. 624 * Lastly, this library provides the API to make SP_EL3 point to the cpu context 625 * which will be used for programming an entry into a lower EL. The same context 626 * will be used to save state upon exception entry from that EL. 627 ******************************************************************************/ 628 void __init cm_init(void) 629 { 630 /* 631 * The context management library has only global data to initialize, but 632 * that will be done when the BSS is zeroed out. 633 */ 634 } 635 636 /******************************************************************************* 637 * This is the high-level function used to initialize the cpu_context 'ctx' for 638 * first use. It performs initializations that are common to all security states 639 * and initializations specific to the security state specified in 'ep' 640 ******************************************************************************/ 641 void cm_setup_context(cpu_context_t *ctx, const entry_point_info_t *ep) 642 { 643 size_t security_state; 644 645 assert(ctx != NULL); 646 647 /* 648 * Perform initializations that are common 649 * to all security states 650 */ 651 setup_context_common(ctx, ep); 652 653 security_state = GET_SECURITY_STATE(ep->h.attr); 654 655 /* Perform security state specific initializations */ 656 switch (security_state) { 657 case SECURE: 658 setup_secure_context(ctx, ep); 659 break; 660 #if ENABLE_RME && IMAGE_BL31 661 case REALM: 662 setup_realm_context(ctx, ep); 663 break; 664 #endif 665 case NON_SECURE: 666 setup_ns_context(ctx, ep); 667 break; 668 default: 669 ERROR("Invalid security state\n"); 670 panic(); 671 break; 672 } 673 } 674 675 /******************************************************************************* 676 * Enable architecture extensions for EL3 execution. This function only updates 677 * registers in-place which are expected to either never change or be 678 * overwritten by el3_exit. Expects the core_pos of the current core as argument. 679 ******************************************************************************/ 680 #if IMAGE_BL31 681 void cm_manage_extensions_el3(unsigned int my_idx) 682 { 683 if (is_feat_sve_supported()) { 684 sve_init_el3(); 685 } 686 687 if (is_feat_amu_supported()) { 688 amu_init_el3(my_idx); 689 } 690 691 if (is_feat_sme_supported()) { 692 sme_init_el3(); 693 } 694 695 if (is_feat_fgwte3_supported()) { 696 write_fgwte3_el3(FGWTE3_EL3_EARLY_INIT_VAL); 697 } 698 699 if (is_feat_mpam_supported()) { 700 mpam_init_el3(); 701 } 702 703 pmuv3_init_el3(); 704 } 705 706 /****************************************************************************** 707 * Function to initialise the registers with the RESET values in the context 708 * memory, which are maintained per world. 709 ******************************************************************************/ 710 static void cm_el3_arch_init_per_world(per_world_context_t *per_world_ctx) 711 { 712 /* 713 * Initialise CPTR_EL3, setting all fields rather than relying on hw. 714 * 715 * CPTR_EL3.TFP: Set to zero so that accesses to the V- or Z- registers 716 * by Advanced SIMD, floating-point or SVE instructions (if 717 * implemented) do not trap to EL3. 718 * 719 * CPTR_EL3.TCPAC: Set to zero so that accesses to CPACR_EL1, 720 * CPTR_EL2,CPACR, or HCPTR do not trap to EL3. 721 */ 722 uint64_t cptr_el3 = CPTR_EL3_RESET_VAL & ~(TCPAC_BIT | TFP_BIT); 723 724 per_world_ctx->ctx_cptr_el3 = cptr_el3; 725 726 /* 727 * Initialize MPAM3_EL3 to its default reset value 728 * 729 * MPAM3_EL3_RESET_VAL sets the MPAM3_EL3.TRAPLOWER bit that forces 730 * all lower ELn MPAM3_EL3 register access to, trap to EL3 731 */ 732 733 per_world_ctx->ctx_mpam3_el3 = MPAM3_EL3_RESET_VAL; 734 } 735 736 /******************************************************************************* 737 * Initialise per_world_context for Non-Secure world. 738 * This function enables the architecture extensions, which have same value 739 * across the cores for the non-secure world. 740 ******************************************************************************/ 741 static void manage_extensions_nonsecure_per_world(void) 742 { 743 cm_el3_arch_init_per_world(&per_world_context[CPU_CONTEXT_NS]); 744 745 if (is_feat_sme_supported()) { 746 sme_enable_per_world(&per_world_context[CPU_CONTEXT_NS]); 747 } 748 749 if (is_feat_sve_supported()) { 750 sve_enable_per_world(&per_world_context[CPU_CONTEXT_NS]); 751 } 752 753 if (is_feat_amu_supported()) { 754 amu_enable_per_world(&per_world_context[CPU_CONTEXT_NS]); 755 } 756 757 if (is_feat_sys_reg_trace_supported()) { 758 sys_reg_trace_enable_per_world(&per_world_context[CPU_CONTEXT_NS]); 759 } 760 761 if (is_feat_mpam_supported()) { 762 mpam_enable_per_world(&per_world_context[CPU_CONTEXT_NS]); 763 } 764 765 if (is_feat_fpmr_supported()) { 766 fpmr_enable_per_world(&per_world_context[CPU_CONTEXT_NS]); 767 } 768 } 769 770 /******************************************************************************* 771 * Initialise per_world_context for Secure world. 772 * This function enables the architecture extensions, which have same value 773 * across the cores for the secure world. 774 ******************************************************************************/ 775 static void manage_extensions_secure_per_world(void) 776 { 777 cm_el3_arch_init_per_world(&per_world_context[CPU_CONTEXT_SECURE]); 778 779 if (is_feat_sme_supported()) { 780 781 if (ENABLE_SME_FOR_SWD) { 782 /* 783 * Enable SME, SVE, FPU/SIMD in secure context, SPM must ensure 784 * SME, SVE, and FPU/SIMD context properly managed. 785 */ 786 sme_enable_per_world(&per_world_context[CPU_CONTEXT_SECURE]); 787 } else { 788 /* 789 * Disable SME, SVE, FPU/SIMD in secure context so non-secure 790 * world can safely use the associated registers. 791 */ 792 sme_disable_per_world(&per_world_context[CPU_CONTEXT_SECURE]); 793 } 794 } 795 if (is_feat_sve_supported()) { 796 if (ENABLE_SVE_FOR_SWD) { 797 /* 798 * Enable SVE and FPU in secure context, SPM must ensure 799 * that the SVE and FPU register contexts are properly managed. 800 */ 801 sve_enable_per_world(&per_world_context[CPU_CONTEXT_SECURE]); 802 } else { 803 /* 804 * Disable SVE and FPU in secure context so non-secure world 805 * can safely use them. 806 */ 807 sve_disable_per_world(&per_world_context[CPU_CONTEXT_SECURE]); 808 } 809 } 810 811 /* NS can access this but Secure shouldn't */ 812 if (is_feat_sys_reg_trace_supported()) { 813 sys_reg_trace_disable_per_world(&per_world_context[CPU_CONTEXT_SECURE]); 814 } 815 } 816 817 static void manage_extensions_realm_per_world(void) 818 { 819 #if ENABLE_RME 820 cm_el3_arch_init_per_world(&per_world_context[CPU_CONTEXT_REALM]); 821 822 if (is_feat_sve_supported()) { 823 /* 824 * Enable SVE and FPU in realm context when it is enabled for NS. 825 * Realm manager must ensure that the SVE and FPU register 826 * contexts are properly managed. 827 */ 828 sve_enable_per_world(&per_world_context[CPU_CONTEXT_REALM]); 829 } 830 831 /* NS can access this but Realm shouldn't */ 832 if (is_feat_sys_reg_trace_supported()) { 833 sys_reg_trace_disable_per_world(&per_world_context[CPU_CONTEXT_REALM]); 834 } 835 836 /* 837 * If SME/SME2 is supported and enabled for NS world, then disable trapping 838 * of SME instructions for Realm world. RMM will save/restore required 839 * registers that are shared with SVE/FPU so that Realm can use FPU or SVE. 840 */ 841 if (is_feat_sme_supported()) { 842 sme_enable_per_world(&per_world_context[CPU_CONTEXT_REALM]); 843 } 844 845 /* 846 * If FEAT_MPAM is supported and enabled, then disable trapping access 847 * to the MPAM registers for Realm world. Instead, RMM will configure 848 * the access to be trapped by itself so it can inject undefined aborts 849 * back to the Realm. 850 */ 851 if (is_feat_mpam_supported()) { 852 mpam_enable_per_world(&per_world_context[CPU_CONTEXT_REALM]); 853 } 854 #endif /* ENABLE_RME */ 855 } 856 857 void cm_manage_extensions_per_world(void) 858 { 859 manage_extensions_nonsecure_per_world(); 860 manage_extensions_secure_per_world(); 861 manage_extensions_realm_per_world(); 862 } 863 #endif /* IMAGE_BL31 */ 864 865 /******************************************************************************* 866 * Enable architecture extensions on first entry to Non-secure world. 867 ******************************************************************************/ 868 static void manage_extensions_nonsecure(cpu_context_t *ctx) 869 { 870 #if IMAGE_BL31 871 /* NOTE: registers are not context switched */ 872 if (is_feat_amu_supported()) { 873 amu_enable(ctx); 874 } 875 876 if (is_feat_sme_supported()) { 877 sme_enable(ctx); 878 } 879 880 if (is_feat_fgt2_supported()) { 881 fgt2_enable(ctx); 882 } 883 884 if (is_feat_debugv8p9_supported()) { 885 debugv8p9_extended_bp_wp_enable(ctx); 886 } 887 888 if (is_feat_spe_supported()) { 889 spe_enable_ns(ctx); 890 } 891 892 if (is_feat_trbe_supported()) { 893 if (check_if_trbe_disable_affected_core()) { 894 trbe_disable_ns(ctx); 895 } else { 896 trbe_enable_ns(ctx); 897 } 898 } 899 900 if (is_feat_brbe_supported()) { 901 brbe_enable(ctx); 902 } 903 #endif /* IMAGE_BL31 */ 904 } 905 906 #if INIT_UNUSED_NS_EL2 907 /******************************************************************************* 908 * Enable architecture extensions in-place at EL2 on first entry to Non-secure 909 * world when EL2 is empty and unused. 910 ******************************************************************************/ 911 static void manage_extensions_nonsecure_el2_unused(void) 912 { 913 #if IMAGE_BL31 914 if (is_feat_spe_supported()) { 915 spe_init_el2_unused(); 916 } 917 918 if (is_feat_amu_supported()) { 919 amu_init_el2_unused(); 920 } 921 922 if (is_feat_mpam_supported()) { 923 mpam_init_el2_unused(); 924 } 925 926 if (is_feat_trbe_supported()) { 927 trbe_init_el2_unused(); 928 } 929 930 if (is_feat_sys_reg_trace_supported()) { 931 sys_reg_trace_init_el2_unused(); 932 } 933 934 if (is_feat_trf_supported()) { 935 trf_init_el2_unused(); 936 } 937 938 pmuv3_init_el2_unused(); 939 940 if (is_feat_sve_supported()) { 941 sve_init_el2_unused(); 942 } 943 944 if (is_feat_sme_supported()) { 945 sme_init_el2_unused(); 946 } 947 948 if (is_feat_mops_supported() && is_feat_hcx_supported()) { 949 write_hcrx_el2(read_hcrx_el2() | HCRX_EL2_MSCEn_BIT); 950 } 951 952 if (is_feat_pauth_supported()) { 953 pauth_enable_el2(); 954 } 955 #endif /* IMAGE_BL31 */ 956 } 957 #endif /* INIT_UNUSED_NS_EL2 */ 958 959 /******************************************************************************* 960 * Enable architecture extensions on first entry to Secure world. 961 ******************************************************************************/ 962 static void manage_extensions_secure(cpu_context_t *ctx) 963 { 964 #if IMAGE_BL31 965 if (is_feat_sme_supported()) { 966 if (ENABLE_SME_FOR_SWD) { 967 /* 968 * Enable SME, SVE, FPU/SIMD in secure context, secure manager 969 * must ensure SME, SVE, and FPU/SIMD context properly managed. 970 */ 971 sme_init_el3(); 972 sme_enable(ctx); 973 } else { 974 /* 975 * Disable SME, SVE, FPU/SIMD in secure context so non-secure 976 * world can safely use the associated registers. 977 */ 978 sme_disable(ctx); 979 } 980 } 981 982 if (is_feat_spe_supported()) { 983 spe_disable_secure(ctx); 984 } 985 986 if (is_feat_trbe_supported()) { 987 trbe_disable_secure(ctx); 988 } 989 #endif /* IMAGE_BL31 */ 990 } 991 992 /******************************************************************************* 993 * The following function initializes the cpu_context for the current CPU 994 * for first use, and sets the initial entrypoint state as specified by the 995 * entry_point_info structure. 996 ******************************************************************************/ 997 void cm_init_my_context(const entry_point_info_t *ep) 998 { 999 cpu_context_t *ctx; 1000 ctx = cm_get_context(GET_SECURITY_STATE(ep->h.attr)); 1001 cm_setup_context(ctx, ep); 1002 } 1003 1004 /* EL2 present but unused, need to disable safely. SCTLR_EL2 can be ignored */ 1005 static void init_nonsecure_el2_unused(cpu_context_t *ctx) 1006 { 1007 #if INIT_UNUSED_NS_EL2 1008 u_register_t hcr_el2 = HCR_RESET_VAL; 1009 u_register_t mdcr_el2; 1010 u_register_t scr_el3; 1011 1012 scr_el3 = read_ctx_reg(get_el3state_ctx(ctx), CTX_SCR_EL3); 1013 1014 /* Set EL2 register width: Set HCR_EL2.RW to match SCR_EL3.RW */ 1015 if ((scr_el3 & SCR_RW_BIT) != 0U) { 1016 hcr_el2 |= HCR_RW_BIT; 1017 } 1018 1019 write_hcr_el2(hcr_el2); 1020 1021 /* 1022 * Initialise CPTR_EL2 setting all fields rather than relying on the hw. 1023 * All fields have architecturally UNKNOWN reset values. 1024 */ 1025 write_cptr_el2(CPTR_EL2_RESET_VAL); 1026 1027 /* 1028 * Initialise CNTHCTL_EL2. All fields are architecturally UNKNOWN on 1029 * reset and are set to zero except for field(s) listed below. 1030 * 1031 * CNTHCTL_EL2.EL1PTEN: Set to one to disable traps to Hyp mode of 1032 * Non-secure EL0 and EL1 accesses to the physical timer registers. 1033 * 1034 * CNTHCTL_EL2.EL1PCTEN: Set to one to disable traps to Hyp mode of 1035 * Non-secure EL0 and EL1 accesses to the physical counter registers. 1036 */ 1037 write_cnthctl_el2(CNTHCTL_RESET_VAL | EL1PCEN_BIT | EL1PCTEN_BIT); 1038 1039 /* 1040 * Initialise CNTVOFF_EL2 to zero as it resets to an architecturally 1041 * UNKNOWN value. 1042 */ 1043 write_cntvoff_el2(0); 1044 1045 /* 1046 * Set VPIDR_EL2 and VMPIDR_EL2 to match MIDR_EL1 and MPIDR_EL1 1047 * respectively. 1048 */ 1049 write_vpidr_el2(read_midr_el1()); 1050 write_vmpidr_el2(read_mpidr_el1()); 1051 1052 /* 1053 * Initialise VTTBR_EL2. All fields are architecturally UNKNOWN on reset. 1054 * 1055 * VTTBR_EL2.VMID: Set to zero. Even though EL1&0 stage 2 address 1056 * translation is disabled, cache maintenance operations depend on the 1057 * VMID. 1058 * 1059 * VTTBR_EL2.BADDR: Set to zero as EL1&0 stage 2 address translation is 1060 * disabled. 1061 */ 1062 write_vttbr_el2(VTTBR_RESET_VAL & 1063 ~((VTTBR_VMID_MASK << VTTBR_VMID_SHIFT) | 1064 (VTTBR_BADDR_MASK << VTTBR_BADDR_SHIFT))); 1065 1066 /* 1067 * Initialise MDCR_EL2, setting all fields rather than relying on hw. 1068 * Some fields are architecturally UNKNOWN on reset. 1069 * 1070 * MDCR_EL2.TDRA: Set to zero so that Non-secure EL0 and EL1 System 1071 * register accesses to the Debug ROM registers are not trapped to EL2. 1072 * 1073 * MDCR_EL2.TDOSA: Set to zero so that Non-secure EL1 System register 1074 * accesses to the powerdown debug registers are not trapped to EL2. 1075 * 1076 * MDCR_EL2.TDA: Set to zero so that System register accesses to the 1077 * debug registers do not trap to EL2. 1078 * 1079 * MDCR_EL2.TDE: Set to zero so that debug exceptions are not routed to 1080 * EL2. 1081 */ 1082 mdcr_el2 = MDCR_EL2_RESET_VAL & 1083 ~(MDCR_EL2_TDRA_BIT | MDCR_EL2_TDOSA_BIT | MDCR_EL2_TDA_BIT | 1084 MDCR_EL2_TDE_BIT); 1085 1086 write_mdcr_el2(mdcr_el2); 1087 1088 /* 1089 * Initialise HSTR_EL2. All fields are architecturally UNKNOWN on reset. 1090 * 1091 * HSTR_EL2.T<n>: Set all these fields to zero so that Non-secure EL0 or 1092 * EL1 accesses to System registers do not trap to EL2. 1093 */ 1094 write_hstr_el2(HSTR_EL2_RESET_VAL & ~(HSTR_EL2_T_MASK)); 1095 1096 /* 1097 * Initialise CNTHP_CTL_EL2. All fields are architecturally UNKNOWN on 1098 * reset. 1099 * 1100 * CNTHP_CTL_EL2:ENABLE: Set to zero to disable the EL2 physical timer 1101 * and prevent timer interrupts. 1102 */ 1103 write_cnthp_ctl_el2(CNTHP_CTL_RESET_VAL & ~(CNTHP_CTL_ENABLE_BIT)); 1104 1105 manage_extensions_nonsecure_el2_unused(); 1106 #endif /* INIT_UNUSED_NS_EL2 */ 1107 } 1108 1109 /******************************************************************************* 1110 * Prepare the CPU system registers for first entry into realm, secure, or 1111 * normal world. 1112 * 1113 * If execution is requested to EL2 or hyp mode, SCTLR_EL2 is initialized 1114 * If execution is requested to non-secure EL1 or svc mode, and the CPU supports 1115 * EL2 then EL2 is disabled by configuring all necessary EL2 registers. 1116 * For all entries, the EL1 registers are initialized from the cpu_context 1117 ******************************************************************************/ 1118 void cm_prepare_el3_exit(size_t security_state) 1119 { 1120 u_register_t sctlr_el2, scr_el3; 1121 cpu_context_t *ctx = cm_get_context(security_state); 1122 1123 assert(ctx != NULL); 1124 1125 if (security_state == NON_SECURE) { 1126 uint64_t el2_implemented = el_implemented(2); 1127 1128 scr_el3 = read_ctx_reg(get_el3state_ctx(ctx), 1129 CTX_SCR_EL3); 1130 1131 if (el2_implemented != EL_IMPL_NONE) { 1132 1133 /* 1134 * If context is not being used for EL2, initialize 1135 * HCRX_EL2 with its init value here. 1136 */ 1137 if (is_feat_hcx_supported()) { 1138 write_hcrx_el2(HCRX_EL2_INIT_VAL); 1139 } 1140 1141 /* 1142 * Initialize Fine-grained trap registers introduced 1143 * by FEAT_FGT so all traps are initially disabled when 1144 * switching to EL2 or a lower EL, preventing undesired 1145 * behavior. 1146 */ 1147 if (is_feat_fgt_supported()) { 1148 /* 1149 * Initialize HFG*_EL2 registers with a default 1150 * value so legacy systems unaware of FEAT_FGT 1151 * do not get trapped due to their lack of 1152 * initialization for this feature. 1153 */ 1154 write_hfgitr_el2(HFGITR_EL2_INIT_VAL); 1155 write_hfgrtr_el2(HFGRTR_EL2_INIT_VAL); 1156 write_hfgwtr_el2(HFGWTR_EL2_INIT_VAL); 1157 } 1158 1159 /* Condition to ensure EL2 is being used. */ 1160 if ((scr_el3 & SCR_HCE_BIT) != 0U) { 1161 /* Initialize SCTLR_EL2 register with reset value. */ 1162 sctlr_el2 = SCTLR_EL2_RES1; 1163 1164 /* 1165 * If workaround of errata 764081 for Cortex-A75 1166 * is used then set SCTLR_EL2.IESB to enable 1167 * Implicit Error Synchronization Barrier. 1168 */ 1169 if (errata_a75_764081_applies()) { 1170 sctlr_el2 |= SCTLR_IESB_BIT; 1171 } 1172 1173 write_sctlr_el2(sctlr_el2); 1174 } else { 1175 /* 1176 * (scr_el3 & SCR_HCE_BIT==0) 1177 * EL2 implemented but unused. 1178 */ 1179 init_nonsecure_el2_unused(ctx); 1180 } 1181 } 1182 1183 if (is_feat_fgwte3_supported()) { 1184 /* 1185 * TCR_EL3 and ACTLR_EL3 could be overwritten 1186 * by platforms and hence is locked a bit late. 1187 */ 1188 write_fgwte3_el3(FGWTE3_EL3_LATE_INIT_VAL); 1189 } 1190 } 1191 #if (!CTX_INCLUDE_EL2_REGS) 1192 /* Restore EL1 system registers, only when CTX_INCLUDE_EL2_REGS=0 */ 1193 cm_el1_sysregs_context_restore(security_state); 1194 #endif 1195 cm_set_next_eret_context(security_state); 1196 } 1197 1198 #if (CTX_INCLUDE_EL2_REGS && IMAGE_BL31) 1199 1200 static void el2_sysregs_context_save_fgt(el2_sysregs_t *ctx) 1201 { 1202 write_el2_ctx_fgt(ctx, hdfgrtr_el2, read_hdfgrtr_el2()); 1203 if (is_feat_amu_supported()) { 1204 write_el2_ctx_fgt(ctx, hafgrtr_el2, read_hafgrtr_el2()); 1205 } 1206 write_el2_ctx_fgt(ctx, hdfgwtr_el2, read_hdfgwtr_el2()); 1207 write_el2_ctx_fgt(ctx, hfgitr_el2, read_hfgitr_el2()); 1208 write_el2_ctx_fgt(ctx, hfgrtr_el2, read_hfgrtr_el2()); 1209 write_el2_ctx_fgt(ctx, hfgwtr_el2, read_hfgwtr_el2()); 1210 } 1211 1212 static void el2_sysregs_context_restore_fgt(el2_sysregs_t *ctx) 1213 { 1214 write_hdfgrtr_el2(read_el2_ctx_fgt(ctx, hdfgrtr_el2)); 1215 if (is_feat_amu_supported()) { 1216 write_hafgrtr_el2(read_el2_ctx_fgt(ctx, hafgrtr_el2)); 1217 } 1218 write_hdfgwtr_el2(read_el2_ctx_fgt(ctx, hdfgwtr_el2)); 1219 write_hfgitr_el2(read_el2_ctx_fgt(ctx, hfgitr_el2)); 1220 write_hfgrtr_el2(read_el2_ctx_fgt(ctx, hfgrtr_el2)); 1221 write_hfgwtr_el2(read_el2_ctx_fgt(ctx, hfgwtr_el2)); 1222 } 1223 1224 static void el2_sysregs_context_save_fgt2(el2_sysregs_t *ctx) 1225 { 1226 write_el2_ctx_fgt2(ctx, hdfgrtr2_el2, read_hdfgrtr2_el2()); 1227 write_el2_ctx_fgt2(ctx, hdfgwtr2_el2, read_hdfgwtr2_el2()); 1228 write_el2_ctx_fgt2(ctx, hfgitr2_el2, read_hfgitr2_el2()); 1229 write_el2_ctx_fgt2(ctx, hfgrtr2_el2, read_hfgrtr2_el2()); 1230 write_el2_ctx_fgt2(ctx, hfgwtr2_el2, read_hfgwtr2_el2()); 1231 } 1232 1233 static void el2_sysregs_context_restore_fgt2(el2_sysregs_t *ctx) 1234 { 1235 write_hdfgrtr2_el2(read_el2_ctx_fgt2(ctx, hdfgrtr2_el2)); 1236 write_hdfgwtr2_el2(read_el2_ctx_fgt2(ctx, hdfgwtr2_el2)); 1237 write_hfgitr2_el2(read_el2_ctx_fgt2(ctx, hfgitr2_el2)); 1238 write_hfgrtr2_el2(read_el2_ctx_fgt2(ctx, hfgrtr2_el2)); 1239 write_hfgwtr2_el2(read_el2_ctx_fgt2(ctx, hfgwtr2_el2)); 1240 } 1241 1242 static void el2_sysregs_context_save_mpam(el2_sysregs_t *ctx) 1243 { 1244 u_register_t mpam_idr = read_mpamidr_el1(); 1245 1246 write_el2_ctx_mpam(ctx, mpam2_el2, read_mpam2_el2()); 1247 1248 /* 1249 * The context registers that we intend to save would be part of the 1250 * PE's system register frame only if MPAMIDR_EL1.HAS_HCR == 1. 1251 */ 1252 if ((mpam_idr & MPAMIDR_HAS_HCR_BIT) == 0U) { 1253 return; 1254 } 1255 1256 /* 1257 * MPAMHCR_EL2, MPAMVPMV_EL2 and MPAMVPM0_EL2 are always present if 1258 * MPAMIDR_HAS_HCR_BIT == 1. 1259 */ 1260 write_el2_ctx_mpam(ctx, mpamhcr_el2, read_mpamhcr_el2()); 1261 write_el2_ctx_mpam(ctx, mpamvpm0_el2, read_mpamvpm0_el2()); 1262 write_el2_ctx_mpam(ctx, mpamvpmv_el2, read_mpamvpmv_el2()); 1263 1264 /* 1265 * The number of MPAMVPM registers is implementation defined, their 1266 * number is stored in the MPAMIDR_EL1 register. 1267 */ 1268 switch ((mpam_idr >> MPAMIDR_EL1_VPMR_MAX_SHIFT) & MPAMIDR_EL1_VPMR_MAX_MASK) { 1269 case 7: 1270 write_el2_ctx_mpam(ctx, mpamvpm7_el2, read_mpamvpm7_el2()); 1271 __fallthrough; 1272 case 6: 1273 write_el2_ctx_mpam(ctx, mpamvpm6_el2, read_mpamvpm6_el2()); 1274 __fallthrough; 1275 case 5: 1276 write_el2_ctx_mpam(ctx, mpamvpm5_el2, read_mpamvpm5_el2()); 1277 __fallthrough; 1278 case 4: 1279 write_el2_ctx_mpam(ctx, mpamvpm4_el2, read_mpamvpm4_el2()); 1280 __fallthrough; 1281 case 3: 1282 write_el2_ctx_mpam(ctx, mpamvpm3_el2, read_mpamvpm3_el2()); 1283 __fallthrough; 1284 case 2: 1285 write_el2_ctx_mpam(ctx, mpamvpm2_el2, read_mpamvpm2_el2()); 1286 __fallthrough; 1287 case 1: 1288 write_el2_ctx_mpam(ctx, mpamvpm1_el2, read_mpamvpm1_el2()); 1289 break; 1290 } 1291 } 1292 1293 static void el2_sysregs_context_restore_mpam(el2_sysregs_t *ctx) 1294 { 1295 u_register_t mpam_idr = read_mpamidr_el1(); 1296 1297 write_mpam2_el2(read_el2_ctx_mpam(ctx, mpam2_el2)); 1298 1299 if ((mpam_idr & MPAMIDR_HAS_HCR_BIT) == 0U) { 1300 return; 1301 } 1302 1303 write_mpamhcr_el2(read_el2_ctx_mpam(ctx, mpamhcr_el2)); 1304 write_mpamvpm0_el2(read_el2_ctx_mpam(ctx, mpamvpm0_el2)); 1305 write_mpamvpmv_el2(read_el2_ctx_mpam(ctx, mpamvpmv_el2)); 1306 1307 switch ((mpam_idr >> MPAMIDR_EL1_VPMR_MAX_SHIFT) & MPAMIDR_EL1_VPMR_MAX_MASK) { 1308 case 7: 1309 write_mpamvpm7_el2(read_el2_ctx_mpam(ctx, mpamvpm7_el2)); 1310 __fallthrough; 1311 case 6: 1312 write_mpamvpm6_el2(read_el2_ctx_mpam(ctx, mpamvpm6_el2)); 1313 __fallthrough; 1314 case 5: 1315 write_mpamvpm5_el2(read_el2_ctx_mpam(ctx, mpamvpm5_el2)); 1316 __fallthrough; 1317 case 4: 1318 write_mpamvpm4_el2(read_el2_ctx_mpam(ctx, mpamvpm4_el2)); 1319 __fallthrough; 1320 case 3: 1321 write_mpamvpm3_el2(read_el2_ctx_mpam(ctx, mpamvpm3_el2)); 1322 __fallthrough; 1323 case 2: 1324 write_mpamvpm2_el2(read_el2_ctx_mpam(ctx, mpamvpm2_el2)); 1325 __fallthrough; 1326 case 1: 1327 write_mpamvpm1_el2(read_el2_ctx_mpam(ctx, mpamvpm1_el2)); 1328 break; 1329 } 1330 } 1331 1332 /* --------------------------------------------------------------------------- 1333 * The following registers are not added: 1334 * ICH_AP0R<n>_EL2 1335 * ICH_AP1R<n>_EL2 1336 * ICH_LR<n>_EL2 1337 * 1338 * NOTE: For a system with S-EL2 present but not enabled, accessing 1339 * ICC_SRE_EL2 is undefined from EL3. To workaround this change the 1340 * SCR_EL3.NS = 1 before accessing this register. 1341 * --------------------------------------------------------------------------- 1342 */ 1343 static void el2_sysregs_context_save_gic(el2_sysregs_t *ctx, uint32_t security_state) 1344 { 1345 u_register_t scr_el3 = read_scr_el3(); 1346 1347 #if defined(SPD_spmd) && SPMD_SPM_AT_SEL2 1348 write_el2_ctx_common(ctx, icc_sre_el2, read_icc_sre_el2()); 1349 #else 1350 write_scr_el3(scr_el3 | SCR_NS_BIT); 1351 isb(); 1352 1353 write_el2_ctx_common(ctx, icc_sre_el2, read_icc_sre_el2()); 1354 1355 write_scr_el3(scr_el3); 1356 isb(); 1357 #endif 1358 write_el2_ctx_common(ctx, ich_hcr_el2, read_ich_hcr_el2()); 1359 1360 if (errata_ich_vmcr_el2_applies()) { 1361 if (security_state == SECURE) { 1362 write_scr_el3(scr_el3 & ~SCR_NS_BIT); 1363 } else { 1364 write_scr_el3(scr_el3 | SCR_NS_BIT); 1365 } 1366 isb(); 1367 } 1368 1369 write_el2_ctx_common(ctx, ich_vmcr_el2, read_ich_vmcr_el2()); 1370 1371 if (errata_ich_vmcr_el2_applies()) { 1372 write_scr_el3(scr_el3); 1373 isb(); 1374 } 1375 } 1376 1377 static void el2_sysregs_context_restore_gic(el2_sysregs_t *ctx, uint32_t security_state) 1378 { 1379 u_register_t scr_el3 = read_scr_el3(); 1380 1381 #if defined(SPD_spmd) && SPMD_SPM_AT_SEL2 1382 write_icc_sre_el2(read_el2_ctx_common(ctx, icc_sre_el2)); 1383 #else 1384 write_scr_el3(scr_el3 | SCR_NS_BIT); 1385 isb(); 1386 1387 write_icc_sre_el2(read_el2_ctx_common(ctx, icc_sre_el2)); 1388 1389 write_scr_el3(scr_el3); 1390 isb(); 1391 #endif 1392 write_ich_hcr_el2(read_el2_ctx_common(ctx, ich_hcr_el2)); 1393 1394 if (errata_ich_vmcr_el2_applies()) { 1395 if (security_state == SECURE) { 1396 write_scr_el3(scr_el3 & ~SCR_NS_BIT); 1397 } else { 1398 write_scr_el3(scr_el3 | SCR_NS_BIT); 1399 } 1400 isb(); 1401 } 1402 1403 write_ich_vmcr_el2(read_el2_ctx_common(ctx, ich_vmcr_el2)); 1404 1405 if (errata_ich_vmcr_el2_applies()) { 1406 write_scr_el3(scr_el3); 1407 isb(); 1408 } 1409 } 1410 1411 /* ----------------------------------------------------- 1412 * The following registers are not added: 1413 * AMEVCNTVOFF0<n>_EL2 1414 * AMEVCNTVOFF1<n>_EL2 1415 * ----------------------------------------------------- 1416 */ 1417 static void el2_sysregs_context_save_common(el2_sysregs_t *ctx) 1418 { 1419 write_el2_ctx_common(ctx, actlr_el2, read_actlr_el2()); 1420 write_el2_ctx_common(ctx, afsr0_el2, read_afsr0_el2()); 1421 write_el2_ctx_common(ctx, afsr1_el2, read_afsr1_el2()); 1422 write_el2_ctx_common(ctx, amair_el2, read_amair_el2()); 1423 write_el2_ctx_common(ctx, cnthctl_el2, read_cnthctl_el2()); 1424 write_el2_ctx_common(ctx, cntvoff_el2, read_cntvoff_el2()); 1425 write_el2_ctx_common(ctx, cptr_el2, read_cptr_el2()); 1426 if (CTX_INCLUDE_AARCH32_REGS) { 1427 write_el2_ctx_common(ctx, dbgvcr32_el2, read_dbgvcr32_el2()); 1428 } 1429 write_el2_ctx_common(ctx, elr_el2, read_elr_el2()); 1430 write_el2_ctx_common(ctx, esr_el2, read_esr_el2()); 1431 write_el2_ctx_common(ctx, far_el2, read_far_el2()); 1432 write_el2_ctx_common(ctx, hacr_el2, read_hacr_el2()); 1433 write_el2_ctx_common(ctx, hcr_el2, read_hcr_el2()); 1434 write_el2_ctx_common(ctx, hpfar_el2, read_hpfar_el2()); 1435 write_el2_ctx_common(ctx, hstr_el2, read_hstr_el2()); 1436 write_el2_ctx_common(ctx, mair_el2, read_mair_el2()); 1437 write_el2_ctx_common(ctx, mdcr_el2, read_mdcr_el2()); 1438 write_el2_ctx_common(ctx, sctlr_el2, read_sctlr_el2()); 1439 write_el2_ctx_common(ctx, spsr_el2, read_spsr_el2()); 1440 write_el2_ctx_common(ctx, sp_el2, read_sp_el2()); 1441 write_el2_ctx_common(ctx, tcr_el2, read_tcr_el2()); 1442 write_el2_ctx_common(ctx, tpidr_el2, read_tpidr_el2()); 1443 write_el2_ctx_common(ctx, vbar_el2, read_vbar_el2()); 1444 write_el2_ctx_common(ctx, vmpidr_el2, read_vmpidr_el2()); 1445 write_el2_ctx_common(ctx, vpidr_el2, read_vpidr_el2()); 1446 write_el2_ctx_common(ctx, vtcr_el2, read_vtcr_el2()); 1447 1448 write_el2_ctx_common_sysreg128(ctx, ttbr0_el2, read_ttbr0_el2()); 1449 write_el2_ctx_common_sysreg128(ctx, vttbr_el2, read_vttbr_el2()); 1450 } 1451 1452 static void el2_sysregs_context_restore_common(el2_sysregs_t *ctx) 1453 { 1454 write_actlr_el2(read_el2_ctx_common(ctx, actlr_el2)); 1455 write_afsr0_el2(read_el2_ctx_common(ctx, afsr0_el2)); 1456 write_afsr1_el2(read_el2_ctx_common(ctx, afsr1_el2)); 1457 write_amair_el2(read_el2_ctx_common(ctx, amair_el2)); 1458 write_cnthctl_el2(read_el2_ctx_common(ctx, cnthctl_el2)); 1459 write_cntvoff_el2(read_el2_ctx_common(ctx, cntvoff_el2)); 1460 write_cptr_el2(read_el2_ctx_common(ctx, cptr_el2)); 1461 if (CTX_INCLUDE_AARCH32_REGS) { 1462 write_dbgvcr32_el2(read_el2_ctx_common(ctx, dbgvcr32_el2)); 1463 } 1464 write_elr_el2(read_el2_ctx_common(ctx, elr_el2)); 1465 write_esr_el2(read_el2_ctx_common(ctx, esr_el2)); 1466 write_far_el2(read_el2_ctx_common(ctx, far_el2)); 1467 write_hacr_el2(read_el2_ctx_common(ctx, hacr_el2)); 1468 write_hcr_el2(read_el2_ctx_common(ctx, hcr_el2)); 1469 write_hpfar_el2(read_el2_ctx_common(ctx, hpfar_el2)); 1470 write_hstr_el2(read_el2_ctx_common(ctx, hstr_el2)); 1471 write_mair_el2(read_el2_ctx_common(ctx, mair_el2)); 1472 write_mdcr_el2(read_el2_ctx_common(ctx, mdcr_el2)); 1473 write_sctlr_el2(read_el2_ctx_common(ctx, sctlr_el2)); 1474 write_spsr_el2(read_el2_ctx_common(ctx, spsr_el2)); 1475 write_sp_el2(read_el2_ctx_common(ctx, sp_el2)); 1476 write_tcr_el2(read_el2_ctx_common(ctx, tcr_el2)); 1477 write_tpidr_el2(read_el2_ctx_common(ctx, tpidr_el2)); 1478 write_ttbr0_el2(read_el2_ctx_common(ctx, ttbr0_el2)); 1479 write_vbar_el2(read_el2_ctx_common(ctx, vbar_el2)); 1480 write_vmpidr_el2(read_el2_ctx_common(ctx, vmpidr_el2)); 1481 write_vpidr_el2(read_el2_ctx_common(ctx, vpidr_el2)); 1482 write_vtcr_el2(read_el2_ctx_common(ctx, vtcr_el2)); 1483 write_vttbr_el2(read_el2_ctx_common(ctx, vttbr_el2)); 1484 } 1485 1486 /******************************************************************************* 1487 * Save EL2 sysreg context 1488 ******************************************************************************/ 1489 void cm_el2_sysregs_context_save(uint32_t security_state) 1490 { 1491 cpu_context_t *ctx; 1492 el2_sysregs_t *el2_sysregs_ctx; 1493 1494 ctx = cm_get_context(security_state); 1495 assert(ctx != NULL); 1496 1497 el2_sysregs_ctx = get_el2_sysregs_ctx(ctx); 1498 1499 el2_sysregs_context_save_common(el2_sysregs_ctx); 1500 el2_sysregs_context_save_gic(el2_sysregs_ctx, security_state); 1501 1502 if (is_feat_mte2_supported()) { 1503 write_el2_ctx_mte2(el2_sysregs_ctx, tfsr_el2, read_tfsr_el2()); 1504 } 1505 1506 if (is_feat_mpam_supported()) { 1507 el2_sysregs_context_save_mpam(el2_sysregs_ctx); 1508 } 1509 1510 if (is_feat_fgt_supported()) { 1511 el2_sysregs_context_save_fgt(el2_sysregs_ctx); 1512 } 1513 1514 if (is_feat_fgt2_supported()) { 1515 el2_sysregs_context_save_fgt2(el2_sysregs_ctx); 1516 } 1517 1518 if (is_feat_ecv_v2_supported()) { 1519 write_el2_ctx_ecv(el2_sysregs_ctx, cntpoff_el2, read_cntpoff_el2()); 1520 } 1521 1522 if (is_feat_vhe_supported()) { 1523 write_el2_ctx_vhe(el2_sysregs_ctx, contextidr_el2, 1524 read_contextidr_el2()); 1525 write_el2_ctx_vhe_sysreg128(el2_sysregs_ctx, ttbr1_el2, read_ttbr1_el2()); 1526 } 1527 1528 if (is_feat_ras_supported()) { 1529 write_el2_ctx_ras(el2_sysregs_ctx, vdisr_el2, read_vdisr_el2()); 1530 write_el2_ctx_ras(el2_sysregs_ctx, vsesr_el2, read_vsesr_el2()); 1531 } 1532 1533 if (is_feat_nv2_supported()) { 1534 write_el2_ctx_neve(el2_sysregs_ctx, vncr_el2, read_vncr_el2()); 1535 } 1536 1537 if (is_feat_trf_supported()) { 1538 write_el2_ctx_trf(el2_sysregs_ctx, trfcr_el2, read_trfcr_el2()); 1539 } 1540 1541 if (is_feat_csv2_2_supported()) { 1542 write_el2_ctx_csv2_2(el2_sysregs_ctx, scxtnum_el2, 1543 read_scxtnum_el2()); 1544 } 1545 1546 if (is_feat_hcx_supported()) { 1547 write_el2_ctx_hcx(el2_sysregs_ctx, hcrx_el2, read_hcrx_el2()); 1548 } 1549 1550 if (is_feat_tcr2_supported()) { 1551 write_el2_ctx_tcr2(el2_sysregs_ctx, tcr2_el2, read_tcr2_el2()); 1552 } 1553 1554 if (is_feat_sxpie_supported()) { 1555 write_el2_ctx_sxpie(el2_sysregs_ctx, pire0_el2, read_pire0_el2()); 1556 write_el2_ctx_sxpie(el2_sysregs_ctx, pir_el2, read_pir_el2()); 1557 } 1558 1559 if (is_feat_sxpoe_supported()) { 1560 write_el2_ctx_sxpoe(el2_sysregs_ctx, por_el2, read_por_el2()); 1561 } 1562 1563 if (is_feat_brbe_supported()) { 1564 write_el2_ctx_brbe(el2_sysregs_ctx, brbcr_el2, read_brbcr_el2()); 1565 } 1566 1567 if (is_feat_s2pie_supported()) { 1568 write_el2_ctx_s2pie(el2_sysregs_ctx, s2pir_el2, read_s2pir_el2()); 1569 } 1570 1571 if (is_feat_gcs_supported()) { 1572 write_el2_ctx_gcs(el2_sysregs_ctx, gcscr_el2, read_gcscr_el2()); 1573 write_el2_ctx_gcs(el2_sysregs_ctx, gcspr_el2, read_gcspr_el2()); 1574 } 1575 1576 if (is_feat_sctlr2_supported()) { 1577 write_el2_ctx_sctlr2(el2_sysregs_ctx, sctlr2_el2, read_sctlr2_el2()); 1578 } 1579 } 1580 1581 /******************************************************************************* 1582 * Restore EL2 sysreg context 1583 ******************************************************************************/ 1584 void cm_el2_sysregs_context_restore(uint32_t security_state) 1585 { 1586 cpu_context_t *ctx; 1587 el2_sysregs_t *el2_sysregs_ctx; 1588 1589 ctx = cm_get_context(security_state); 1590 assert(ctx != NULL); 1591 1592 el2_sysregs_ctx = get_el2_sysregs_ctx(ctx); 1593 1594 el2_sysregs_context_restore_common(el2_sysregs_ctx); 1595 el2_sysregs_context_restore_gic(el2_sysregs_ctx, security_state); 1596 1597 if (is_feat_mte2_supported()) { 1598 write_tfsr_el2(read_el2_ctx_mte2(el2_sysregs_ctx, tfsr_el2)); 1599 } 1600 1601 if (is_feat_mpam_supported()) { 1602 el2_sysregs_context_restore_mpam(el2_sysregs_ctx); 1603 } 1604 1605 if (is_feat_fgt_supported()) { 1606 el2_sysregs_context_restore_fgt(el2_sysregs_ctx); 1607 } 1608 1609 if (is_feat_fgt2_supported()) { 1610 el2_sysregs_context_restore_fgt2(el2_sysregs_ctx); 1611 } 1612 1613 if (is_feat_ecv_v2_supported()) { 1614 write_cntpoff_el2(read_el2_ctx_ecv(el2_sysregs_ctx, cntpoff_el2)); 1615 } 1616 1617 if (is_feat_vhe_supported()) { 1618 write_contextidr_el2(read_el2_ctx_vhe(el2_sysregs_ctx, 1619 contextidr_el2)); 1620 write_ttbr1_el2(read_el2_ctx_vhe(el2_sysregs_ctx, ttbr1_el2)); 1621 } 1622 1623 if (is_feat_ras_supported()) { 1624 write_vdisr_el2(read_el2_ctx_ras(el2_sysregs_ctx, vdisr_el2)); 1625 write_vsesr_el2(read_el2_ctx_ras(el2_sysregs_ctx, vsesr_el2)); 1626 } 1627 1628 if (is_feat_nv2_supported()) { 1629 write_vncr_el2(read_el2_ctx_neve(el2_sysregs_ctx, vncr_el2)); 1630 } 1631 1632 if (is_feat_trf_supported()) { 1633 write_trfcr_el2(read_el2_ctx_trf(el2_sysregs_ctx, trfcr_el2)); 1634 } 1635 1636 if (is_feat_csv2_2_supported()) { 1637 write_scxtnum_el2(read_el2_ctx_csv2_2(el2_sysregs_ctx, 1638 scxtnum_el2)); 1639 } 1640 1641 if (is_feat_hcx_supported()) { 1642 write_hcrx_el2(read_el2_ctx_hcx(el2_sysregs_ctx, hcrx_el2)); 1643 } 1644 1645 if (is_feat_tcr2_supported()) { 1646 write_tcr2_el2(read_el2_ctx_tcr2(el2_sysregs_ctx, tcr2_el2)); 1647 } 1648 1649 if (is_feat_sxpie_supported()) { 1650 write_pire0_el2(read_el2_ctx_sxpie(el2_sysregs_ctx, pire0_el2)); 1651 write_pir_el2(read_el2_ctx_sxpie(el2_sysregs_ctx, pir_el2)); 1652 } 1653 1654 if (is_feat_sxpoe_supported()) { 1655 write_por_el2(read_el2_ctx_sxpoe(el2_sysregs_ctx, por_el2)); 1656 } 1657 1658 if (is_feat_s2pie_supported()) { 1659 write_s2pir_el2(read_el2_ctx_s2pie(el2_sysregs_ctx, s2pir_el2)); 1660 } 1661 1662 if (is_feat_gcs_supported()) { 1663 write_gcscr_el2(read_el2_ctx_gcs(el2_sysregs_ctx, gcscr_el2)); 1664 write_gcspr_el2(read_el2_ctx_gcs(el2_sysregs_ctx, gcspr_el2)); 1665 } 1666 1667 if (is_feat_sctlr2_supported()) { 1668 write_sctlr2_el2(read_el2_ctx_sctlr2(el2_sysregs_ctx, sctlr2_el2)); 1669 } 1670 1671 if (is_feat_brbe_supported()) { 1672 write_brbcr_el2(read_el2_ctx_brbe(el2_sysregs_ctx, brbcr_el2)); 1673 } 1674 } 1675 #endif /* (CTX_INCLUDE_EL2_REGS && IMAGE_BL31) */ 1676 1677 /******************************************************************************* 1678 * This function is used to exit to Non-secure world. If CTX_INCLUDE_EL2_REGS 1679 * is enabled, it restores EL1 and EL2 sysreg contexts instead of directly 1680 * updating EL1 and EL2 registers. Otherwise, it calls the generic 1681 * cm_prepare_el3_exit function. 1682 ******************************************************************************/ 1683 void cm_prepare_el3_exit_ns(void) 1684 { 1685 #if (CTX_INCLUDE_EL2_REGS && IMAGE_BL31) 1686 #if ENABLE_ASSERTIONS 1687 cpu_context_t *ctx = cm_get_context(NON_SECURE); 1688 assert(ctx != NULL); 1689 1690 /* Assert that EL2 is used. */ 1691 u_register_t scr_el3 = read_ctx_reg(get_el3state_ctx(ctx), CTX_SCR_EL3); 1692 assert(((scr_el3 & SCR_HCE_BIT) != 0UL) && 1693 (el_implemented(2U) != EL_IMPL_NONE)); 1694 #endif /* ENABLE_ASSERTIONS */ 1695 1696 /* Restore EL2 sysreg contexts */ 1697 cm_el2_sysregs_context_restore(NON_SECURE); 1698 cm_set_next_eret_context(NON_SECURE); 1699 #else 1700 cm_prepare_el3_exit(NON_SECURE); 1701 #endif /* (CTX_INCLUDE_EL2_REGS && IMAGE_BL31) */ 1702 } 1703 1704 #if ((IMAGE_BL1) || (IMAGE_BL31 && (!CTX_INCLUDE_EL2_REGS))) 1705 /******************************************************************************* 1706 * The next set of six functions are used by runtime services to save and restore 1707 * EL1 context on the 'cpu_context' structure for the specified security state. 1708 ******************************************************************************/ 1709 static void el1_sysregs_context_save(el1_sysregs_t *ctx) 1710 { 1711 write_el1_ctx_common(ctx, spsr_el1, read_spsr_el1()); 1712 write_el1_ctx_common(ctx, elr_el1, read_elr_el1()); 1713 1714 #if (!ERRATA_SPECULATIVE_AT) 1715 write_el1_ctx_common(ctx, sctlr_el1, read_sctlr_el1()); 1716 write_el1_ctx_common(ctx, tcr_el1, read_tcr_el1()); 1717 #endif /* (!ERRATA_SPECULATIVE_AT) */ 1718 1719 write_el1_ctx_common(ctx, cpacr_el1, read_cpacr_el1()); 1720 write_el1_ctx_common(ctx, csselr_el1, read_csselr_el1()); 1721 write_el1_ctx_common(ctx, sp_el1, read_sp_el1()); 1722 write_el1_ctx_common(ctx, esr_el1, read_esr_el1()); 1723 write_el1_ctx_common(ctx, mair_el1, read_mair_el1()); 1724 write_el1_ctx_common(ctx, amair_el1, read_amair_el1()); 1725 write_el1_ctx_common(ctx, actlr_el1, read_actlr_el1()); 1726 write_el1_ctx_common(ctx, tpidr_el1, read_tpidr_el1()); 1727 write_el1_ctx_common(ctx, tpidr_el0, read_tpidr_el0()); 1728 write_el1_ctx_common(ctx, tpidrro_el0, read_tpidrro_el0()); 1729 write_el1_ctx_common(ctx, far_el1, read_far_el1()); 1730 write_el1_ctx_common(ctx, afsr0_el1, read_afsr0_el1()); 1731 write_el1_ctx_common(ctx, afsr1_el1, read_afsr1_el1()); 1732 write_el1_ctx_common(ctx, contextidr_el1, read_contextidr_el1()); 1733 write_el1_ctx_common(ctx, vbar_el1, read_vbar_el1()); 1734 write_el1_ctx_common(ctx, mdccint_el1, read_mdccint_el1()); 1735 write_el1_ctx_common(ctx, mdscr_el1, read_mdscr_el1()); 1736 1737 write_el1_ctx_common_sysreg128(ctx, par_el1, read_par_el1()); 1738 write_el1_ctx_common_sysreg128(ctx, ttbr0_el1, read_ttbr0_el1()); 1739 write_el1_ctx_common_sysreg128(ctx, ttbr1_el1, read_ttbr1_el1()); 1740 1741 if (CTX_INCLUDE_AARCH32_REGS) { 1742 /* Save Aarch32 registers */ 1743 write_el1_ctx_aarch32(ctx, spsr_abt, read_spsr_abt()); 1744 write_el1_ctx_aarch32(ctx, spsr_und, read_spsr_und()); 1745 write_el1_ctx_aarch32(ctx, spsr_irq, read_spsr_irq()); 1746 write_el1_ctx_aarch32(ctx, spsr_fiq, read_spsr_fiq()); 1747 write_el1_ctx_aarch32(ctx, dacr32_el2, read_dacr32_el2()); 1748 write_el1_ctx_aarch32(ctx, ifsr32_el2, read_ifsr32_el2()); 1749 } 1750 1751 if (NS_TIMER_SWITCH) { 1752 /* Save NS Timer registers */ 1753 write_el1_ctx_arch_timer(ctx, cntp_ctl_el0, read_cntp_ctl_el0()); 1754 write_el1_ctx_arch_timer(ctx, cntp_cval_el0, read_cntp_cval_el0()); 1755 write_el1_ctx_arch_timer(ctx, cntv_ctl_el0, read_cntv_ctl_el0()); 1756 write_el1_ctx_arch_timer(ctx, cntv_cval_el0, read_cntv_cval_el0()); 1757 write_el1_ctx_arch_timer(ctx, cntkctl_el1, read_cntkctl_el1()); 1758 } 1759 1760 if (is_feat_mte2_supported()) { 1761 write_el1_ctx_mte2(ctx, tfsre0_el1, read_tfsre0_el1()); 1762 write_el1_ctx_mte2(ctx, tfsr_el1, read_tfsr_el1()); 1763 write_el1_ctx_mte2(ctx, rgsr_el1, read_rgsr_el1()); 1764 write_el1_ctx_mte2(ctx, gcr_el1, read_gcr_el1()); 1765 } 1766 1767 if (is_feat_ras_supported()) { 1768 write_el1_ctx_ras(ctx, disr_el1, read_disr_el1()); 1769 } 1770 1771 if (is_feat_s1pie_supported()) { 1772 write_el1_ctx_s1pie(ctx, pire0_el1, read_pire0_el1()); 1773 write_el1_ctx_s1pie(ctx, pir_el1, read_pir_el1()); 1774 } 1775 1776 if (is_feat_s1poe_supported()) { 1777 write_el1_ctx_s1poe(ctx, por_el1, read_por_el1()); 1778 } 1779 1780 if (is_feat_s2poe_supported()) { 1781 write_el1_ctx_s2poe(ctx, s2por_el1, read_s2por_el1()); 1782 } 1783 1784 if (is_feat_tcr2_supported()) { 1785 write_el1_ctx_tcr2(ctx, tcr2_el1, read_tcr2_el1()); 1786 } 1787 1788 if (is_feat_trf_supported()) { 1789 write_el1_ctx_trf(ctx, trfcr_el1, read_trfcr_el1()); 1790 } 1791 1792 if (is_feat_csv2_2_supported()) { 1793 write_el1_ctx_csv2_2(ctx, scxtnum_el0, read_scxtnum_el0()); 1794 write_el1_ctx_csv2_2(ctx, scxtnum_el1, read_scxtnum_el1()); 1795 } 1796 1797 if (is_feat_gcs_supported()) { 1798 write_el1_ctx_gcs(ctx, gcscr_el1, read_gcscr_el1()); 1799 write_el1_ctx_gcs(ctx, gcscre0_el1, read_gcscre0_el1()); 1800 write_el1_ctx_gcs(ctx, gcspr_el1, read_gcspr_el1()); 1801 write_el1_ctx_gcs(ctx, gcspr_el0, read_gcspr_el0()); 1802 } 1803 1804 if (is_feat_the_supported()) { 1805 write_el1_ctx_the_sysreg128(ctx, rcwmask_el1, read_rcwmask_el1()); 1806 write_el1_ctx_the_sysreg128(ctx, rcwsmask_el1, read_rcwsmask_el1()); 1807 } 1808 1809 if (is_feat_sctlr2_supported()) { 1810 write_el1_ctx_sctlr2(ctx, sctlr2_el1, read_sctlr2_el1()); 1811 } 1812 1813 if (is_feat_ls64_accdata_supported()) { 1814 write_el1_ctx_ls64(ctx, accdata_el1, read_accdata_el1()); 1815 } 1816 } 1817 1818 static void el1_sysregs_context_restore(el1_sysregs_t *ctx) 1819 { 1820 write_spsr_el1(read_el1_ctx_common(ctx, spsr_el1)); 1821 write_elr_el1(read_el1_ctx_common(ctx, elr_el1)); 1822 1823 #if (!ERRATA_SPECULATIVE_AT) 1824 write_sctlr_el1(read_el1_ctx_common(ctx, sctlr_el1)); 1825 write_tcr_el1(read_el1_ctx_common(ctx, tcr_el1)); 1826 #endif /* (!ERRATA_SPECULATIVE_AT) */ 1827 1828 write_cpacr_el1(read_el1_ctx_common(ctx, cpacr_el1)); 1829 write_csselr_el1(read_el1_ctx_common(ctx, csselr_el1)); 1830 write_sp_el1(read_el1_ctx_common(ctx, sp_el1)); 1831 write_esr_el1(read_el1_ctx_common(ctx, esr_el1)); 1832 write_ttbr0_el1(read_el1_ctx_common(ctx, ttbr0_el1)); 1833 write_ttbr1_el1(read_el1_ctx_common(ctx, ttbr1_el1)); 1834 write_mair_el1(read_el1_ctx_common(ctx, mair_el1)); 1835 write_amair_el1(read_el1_ctx_common(ctx, amair_el1)); 1836 write_actlr_el1(read_el1_ctx_common(ctx, actlr_el1)); 1837 write_tpidr_el1(read_el1_ctx_common(ctx, tpidr_el1)); 1838 write_tpidr_el0(read_el1_ctx_common(ctx, tpidr_el0)); 1839 write_tpidrro_el0(read_el1_ctx_common(ctx, tpidrro_el0)); 1840 write_par_el1(read_el1_ctx_common(ctx, par_el1)); 1841 write_far_el1(read_el1_ctx_common(ctx, far_el1)); 1842 write_afsr0_el1(read_el1_ctx_common(ctx, afsr0_el1)); 1843 write_afsr1_el1(read_el1_ctx_common(ctx, afsr1_el1)); 1844 write_contextidr_el1(read_el1_ctx_common(ctx, contextidr_el1)); 1845 write_vbar_el1(read_el1_ctx_common(ctx, vbar_el1)); 1846 write_mdccint_el1(read_el1_ctx_common(ctx, mdccint_el1)); 1847 write_mdscr_el1(read_el1_ctx_common(ctx, mdscr_el1)); 1848 1849 if (CTX_INCLUDE_AARCH32_REGS) { 1850 /* Restore Aarch32 registers */ 1851 write_spsr_abt(read_el1_ctx_aarch32(ctx, spsr_abt)); 1852 write_spsr_und(read_el1_ctx_aarch32(ctx, spsr_und)); 1853 write_spsr_irq(read_el1_ctx_aarch32(ctx, spsr_irq)); 1854 write_spsr_fiq(read_el1_ctx_aarch32(ctx, spsr_fiq)); 1855 write_dacr32_el2(read_el1_ctx_aarch32(ctx, dacr32_el2)); 1856 write_ifsr32_el2(read_el1_ctx_aarch32(ctx, ifsr32_el2)); 1857 } 1858 1859 if (NS_TIMER_SWITCH) { 1860 /* Restore NS Timer registers */ 1861 write_cntp_ctl_el0(read_el1_ctx_arch_timer(ctx, cntp_ctl_el0)); 1862 write_cntp_cval_el0(read_el1_ctx_arch_timer(ctx, cntp_cval_el0)); 1863 write_cntv_ctl_el0(read_el1_ctx_arch_timer(ctx, cntv_ctl_el0)); 1864 write_cntv_cval_el0(read_el1_ctx_arch_timer(ctx, cntv_cval_el0)); 1865 write_cntkctl_el1(read_el1_ctx_arch_timer(ctx, cntkctl_el1)); 1866 } 1867 1868 if (is_feat_mte2_supported()) { 1869 write_tfsre0_el1(read_el1_ctx_mte2(ctx, tfsre0_el1)); 1870 write_tfsr_el1(read_el1_ctx_mte2(ctx, tfsr_el1)); 1871 write_rgsr_el1(read_el1_ctx_mte2(ctx, rgsr_el1)); 1872 write_gcr_el1(read_el1_ctx_mte2(ctx, gcr_el1)); 1873 } 1874 1875 if (is_feat_ras_supported()) { 1876 write_disr_el1(read_el1_ctx_ras(ctx, disr_el1)); 1877 } 1878 1879 if (is_feat_s1pie_supported()) { 1880 write_pire0_el1(read_el1_ctx_s1pie(ctx, pire0_el1)); 1881 write_pir_el1(read_el1_ctx_s1pie(ctx, pir_el1)); 1882 } 1883 1884 if (is_feat_s1poe_supported()) { 1885 write_por_el1(read_el1_ctx_s1poe(ctx, por_el1)); 1886 } 1887 1888 if (is_feat_s2poe_supported()) { 1889 write_s2por_el1(read_el1_ctx_s2poe(ctx, s2por_el1)); 1890 } 1891 1892 if (is_feat_tcr2_supported()) { 1893 write_tcr2_el1(read_el1_ctx_tcr2(ctx, tcr2_el1)); 1894 } 1895 1896 if (is_feat_trf_supported()) { 1897 write_trfcr_el1(read_el1_ctx_trf(ctx, trfcr_el1)); 1898 } 1899 1900 if (is_feat_csv2_2_supported()) { 1901 write_scxtnum_el0(read_el1_ctx_csv2_2(ctx, scxtnum_el0)); 1902 write_scxtnum_el1(read_el1_ctx_csv2_2(ctx, scxtnum_el1)); 1903 } 1904 1905 if (is_feat_gcs_supported()) { 1906 write_gcscr_el1(read_el1_ctx_gcs(ctx, gcscr_el1)); 1907 write_gcscre0_el1(read_el1_ctx_gcs(ctx, gcscre0_el1)); 1908 write_gcspr_el1(read_el1_ctx_gcs(ctx, gcspr_el1)); 1909 write_gcspr_el0(read_el1_ctx_gcs(ctx, gcspr_el0)); 1910 } 1911 1912 if (is_feat_the_supported()) { 1913 write_rcwmask_el1(read_el1_ctx_the(ctx, rcwmask_el1)); 1914 write_rcwsmask_el1(read_el1_ctx_the(ctx, rcwsmask_el1)); 1915 } 1916 1917 if (is_feat_sctlr2_supported()) { 1918 write_sctlr2_el1(read_el1_ctx_sctlr2(ctx, sctlr2_el1)); 1919 } 1920 1921 if (is_feat_ls64_accdata_supported()) { 1922 write_accdata_el1(read_el1_ctx_ls64(ctx, accdata_el1)); 1923 } 1924 } 1925 1926 /******************************************************************************* 1927 * The next couple of functions are used by runtime services to save and restore 1928 * EL1 context on the 'cpu_context' structure for the specified security state. 1929 ******************************************************************************/ 1930 void cm_el1_sysregs_context_save(uint32_t security_state) 1931 { 1932 cpu_context_t *ctx; 1933 1934 ctx = cm_get_context(security_state); 1935 assert(ctx != NULL); 1936 1937 el1_sysregs_context_save(get_el1_sysregs_ctx(ctx)); 1938 1939 #if IMAGE_BL31 1940 if (security_state == SECURE) { 1941 PUBLISH_EVENT(cm_exited_secure_world); 1942 } else { 1943 PUBLISH_EVENT(cm_exited_normal_world); 1944 } 1945 #endif 1946 } 1947 1948 void cm_el1_sysregs_context_restore(uint32_t security_state) 1949 { 1950 cpu_context_t *ctx; 1951 1952 ctx = cm_get_context(security_state); 1953 assert(ctx != NULL); 1954 1955 el1_sysregs_context_restore(get_el1_sysregs_ctx(ctx)); 1956 1957 #if IMAGE_BL31 1958 if (security_state == SECURE) { 1959 PUBLISH_EVENT(cm_entering_secure_world); 1960 } else { 1961 PUBLISH_EVENT(cm_entering_normal_world); 1962 } 1963 #endif 1964 } 1965 1966 #endif /* ((IMAGE_BL1) || (IMAGE_BL31 && (!CTX_INCLUDE_EL2_REGS))) */ 1967 1968 /******************************************************************************* 1969 * This function populates ELR_EL3 member of 'cpu_context' pertaining to the 1970 * given security state with the given entrypoint 1971 ******************************************************************************/ 1972 void cm_set_elr_el3(uint32_t security_state, uintptr_t entrypoint) 1973 { 1974 cpu_context_t *ctx; 1975 el3_state_t *state; 1976 1977 ctx = cm_get_context(security_state); 1978 assert(ctx != NULL); 1979 1980 /* Populate EL3 state so that ERET jumps to the correct entry */ 1981 state = get_el3state_ctx(ctx); 1982 write_ctx_reg(state, CTX_ELR_EL3, entrypoint); 1983 } 1984 1985 /******************************************************************************* 1986 * This function populates ELR_EL3 and SPSR_EL3 members of 'cpu_context' 1987 * pertaining to the given security state 1988 ******************************************************************************/ 1989 void cm_set_elr_spsr_el3(uint32_t security_state, 1990 uintptr_t entrypoint, uint32_t spsr) 1991 { 1992 cpu_context_t *ctx; 1993 el3_state_t *state; 1994 1995 ctx = cm_get_context(security_state); 1996 assert(ctx != NULL); 1997 1998 /* Populate EL3 state so that ERET jumps to the correct entry */ 1999 state = get_el3state_ctx(ctx); 2000 write_ctx_reg(state, CTX_ELR_EL3, entrypoint); 2001 write_ctx_reg(state, CTX_SPSR_EL3, spsr); 2002 } 2003 2004 /******************************************************************************* 2005 * This function updates a single bit in the SCR_EL3 member of the 'cpu_context' 2006 * pertaining to the given security state using the value and bit position 2007 * specified in the parameters. It preserves all other bits. 2008 ******************************************************************************/ 2009 void cm_write_scr_el3_bit(uint32_t security_state, 2010 uint32_t bit_pos, 2011 uint32_t value) 2012 { 2013 cpu_context_t *ctx; 2014 el3_state_t *state; 2015 u_register_t scr_el3; 2016 2017 ctx = cm_get_context(security_state); 2018 assert(ctx != NULL); 2019 2020 /* Ensure that the bit position is a valid one */ 2021 assert(((1UL << bit_pos) & SCR_VALID_BIT_MASK) != 0U); 2022 2023 /* Ensure that the 'value' is only a bit wide */ 2024 assert(value <= 1U); 2025 2026 /* 2027 * Get the SCR_EL3 value from the cpu context, clear the desired bit 2028 * and set it to its new value. 2029 */ 2030 state = get_el3state_ctx(ctx); 2031 scr_el3 = read_ctx_reg(state, CTX_SCR_EL3); 2032 scr_el3 &= ~(1UL << bit_pos); 2033 scr_el3 |= (u_register_t)value << bit_pos; 2034 write_ctx_reg(state, CTX_SCR_EL3, scr_el3); 2035 } 2036 2037 /******************************************************************************* 2038 * This function retrieves SCR_EL3 member of 'cpu_context' pertaining to the 2039 * given security state. 2040 ******************************************************************************/ 2041 u_register_t cm_get_scr_el3(uint32_t security_state) 2042 { 2043 const cpu_context_t *ctx; 2044 const el3_state_t *state; 2045 2046 ctx = cm_get_context(security_state); 2047 assert(ctx != NULL); 2048 2049 /* Populate EL3 state so that ERET jumps to the correct entry */ 2050 state = get_el3state_ctx(ctx); 2051 return read_ctx_reg(state, CTX_SCR_EL3); 2052 } 2053 2054 /******************************************************************************* 2055 * This function is used to program the context that's used for exception 2056 * return. This initializes the SP_EL3 to a pointer to a 'cpu_context' set for 2057 * the required security state 2058 ******************************************************************************/ 2059 void cm_set_next_eret_context(uint32_t security_state) 2060 { 2061 cpu_context_t *ctx; 2062 2063 ctx = cm_get_context(security_state); 2064 assert(ctx != NULL); 2065 2066 cm_set_next_context(ctx); 2067 } 2068