1 /* 2 * Copyright (c) 2021-2025, Arm Limited and Contributors. All rights reserved. 3 * 4 * SPDX-License-Identifier: BSD-3-Clause 5 */ 6 7 #include <assert.h> 8 9 #include <common/debug.h> 10 #include <lib/fconf/fconf.h> 11 #include <lib/fconf/fconf_dyn_cfg_getter.h> 12 13 #include <plat/arm/common/plat_arm.h> 14 #include <platform_def.h> 15 16 void __init bl31_early_platform_setup2(u_register_t arg0, 17 u_register_t arg1, u_register_t arg2, u_register_t arg3) 18 { 19 /* Initialize the console to provide early debug support */ 20 arm_console_boot_init(); 21 22 #if !(TRANSFER_LIST || RESET_TO_BL31 || RESET_TO_BL2) 23 const struct dyn_cfg_dtb_info_t *soc_fw_config_info; 24 25 INFO("BL31 FCONF: FW_CONFIG address = %lx\n", (uintptr_t)arg1); 26 27 /* Fill the properties struct with the info from the config dtb */ 28 fconf_populate("FW_CONFIG", arg1); 29 30 soc_fw_config_info = FCONF_GET_PROPERTY(dyn_cfg, dtb, SOC_FW_CONFIG_ID); 31 if (soc_fw_config_info != NULL) { 32 arg1 = soc_fw_config_info->config_addr; 33 } 34 #endif 35 36 arm_bl31_early_platform_setup(arg0, arg1, arg2, arg3); 37 38 /* 39 * Initialize Interconnect for this cluster during cold boot. 40 * No need for locks as no other CPU is active. 41 */ 42 plat_arm_interconnect_init(); 43 44 /* 45 * Enable Interconnect coherency for the primary CPU's cluster. 46 * Earlier bootloader stages might already do this (e.g. Trusted 47 * Firmware's BL1 does it) but we can't assume so. There is no harm in 48 * executing this code twice anyway. 49 * Platform specific PSCI code will enable coherency for other 50 * clusters. 51 */ 52 plat_arm_interconnect_enter_coherency(); 53 } 54 55 #if !TRANSFER_LIST 56 void __init bl31_plat_arch_setup(void) 57 { 58 arm_bl31_plat_arch_setup(); 59 60 /* HW_CONFIG was also loaded by BL2 */ 61 const struct dyn_cfg_dtb_info_t *hw_config_info; 62 63 hw_config_info = FCONF_GET_PROPERTY(dyn_cfg, dtb, HW_CONFIG_ID); 64 assert(hw_config_info != NULL); 65 66 fconf_populate("HW_CONFIG", hw_config_info->config_addr); 67 } 68 #endif 69