1 /* 2 * Copyright (c) 2025, Mediatek Inc. All rights reserved. 3 * 4 * SPDX-License-Identifier: BSD-3-Clause 5 */ 6 7 #ifndef MT_SPM_TRACE_H 8 #define MT_SPM_TRACE_H 9 10 #include <lib/mmio.h> 11 12 #include <platform_def.h> 13 14 enum mt_spm_sysram_type { 15 MT_SPM_SYSRAM_COMMON, 16 MT_SPM_SYSRAM_SUSPEND, 17 MT_SPM_SYSRAM_LP, 18 }; 19 20 /* SPM trace common type */ 21 enum mt_spm_trace_common_type { 22 MT_SPM_TRACE_COMM_HAED, 23 MT_SPM_TRACE_COMM_FP, 24 MT_SPM_TRACE_COMM_RC_LAST_TIME_H, 25 MT_SPM_TRACE_COMM_RC_LAST_TIME_L, 26 MT_SPM_TRACE_COMM_RC_INFO, 27 MT_SPM_TRACE_COMM_RC_FP, 28 MT_SPM_TRACE_COMM_RC_VALID, 29 }; 30 31 /* SPM trace suspend type */ 32 enum mt_spm_trace_suspend_type { 33 MT_SPM_TRACE_SUSPEND_WAKE_SRC, 34 }; 35 36 /* 37 * SPM sram usage with mcdi sram 38 * start offset : 0x500 39 */ 40 #define MT_SPM_SYSRAM_BASE (MTK_LPM_SRAM_BASE + 0x500) 41 #define MT_SPM_SYSRAM_COMM_BASE MT_SPM_SYSRAM_BASE 42 #define MT_SPM_SYSRAM_COMM_SZ 0x20 43 44 #define MT_SPM_SYSRAM_SUSPEND_BASE (MT_SPM_SYSRAM_BASE + MT_SPM_SYSRAM_COMM_SZ) 45 #define MT_SPM_SYSRAM_SUSPEND_SZ 0xe0 46 47 #define MT_SPM_SYSRAM_LP_BASE \ 48 (MT_SPM_SYSRAM_SUSPEND_BASE + MT_SPM_SYSRAM_SUSPEND_SZ) 49 50 #define MT_SPM_SYSRAM_SLOT(slot) ((slot) << 2u) 51 52 #ifndef MTK_PLAT_SPM_TRACE_UNSUPPORT 53 54 #define MT_SPM_SYSRAM_W(_s, type, val, _sz) \ 55 mt_spm_sysram_write(_s, type, val, _sz) 56 57 #define MT_SPM_SYSRAM_R_U32(addr, val) \ 58 ({ \ 59 unsigned int *r_val = (unsigned int *)val; \ 60 if (r_val) \ 61 *r_val = mmio_read_32(addr); \ 62 }) 63 64 #define MT_SPM_SYSRAM_R(_s, type, val) mt_spm_sysram_read(_s, type, val) 65 66 /* SPM trace common */ 67 #define MT_SPM_TRACE_INIT(_magic) ({ mt_spm_sysram_init(_magic); }) 68 69 #define MT_SPM_TRACE_COMMON_U32_WR(_type, _val) \ 70 ({ \ 71 mmio_write_32( \ 72 (MT_SPM_SYSRAM_COMM_BASE + MT_SPM_SYSRAM_SLOT(_type)), \ 73 _val); \ 74 }) 75 76 #define MT_SPM_TRACE_COMMON_WR(_type, val, _sz) \ 77 ({ \ 78 int ret = MT_SPM_SYSRAM_W(MT_SPM_SYSRAM_COMMON, _type, val, \ 79 _sz); \ 80 ret; \ 81 }) 82 83 #define MT_SPM_TRACE_COMMON_U32_RD(_type, _val) \ 84 ({ \ 85 MT_SPM_SYSRAM_R_U32( \ 86 (MT_SPM_SYSRAM_COMM_BASE + MT_SPM_SYSRAM_SLOT(_type)), \ 87 _val); \ 88 }) 89 90 #define MT_SPM_TRACE_COMMON_RD(_type, _val) \ 91 ({ \ 92 int ret = MT_SPM_SYSRAM_R(MT_SPM_SYSRAM_COMMON, _type, _val); \ 93 ret; \ 94 }) 95 96 /* SPM trace suspend */ 97 #define MT_SPM_TRACE_SUSPEND_U32_WR(_type, _val) \ 98 ({ \ 99 mmio_write_32((MT_SPM_SYSRAM_SUSPEND_BASE + \ 100 MT_SPM_SYSRAM_SLOT(_type)), \ 101 _val); \ 102 }) 103 104 #define MT_SPM_TRACE_SUSPEND_WR(_type, _val, _sz) \ 105 ({ \ 106 int ret = MT_SPM_SYSRAM_W(MT_SPM_SYSRAM_SUSPEND, _type, _val, \ 107 _sz); \ 108 ret; \ 109 }) 110 111 #define MT_SPM_TRACE_SUSPEND_U32_RD(_type, _val) \ 112 ({ \ 113 MT_SPM_SYSRAM_R_U32((MT_SPM_SYSRAM_SUSPEND_BASE + \ 114 MT_SPM_SYSRAM_SLOT(_type)), \ 115 _val); \ 116 }) 117 118 #define MT_SPM_TRACE_SUSPEND_RD(_type, _val) \ 119 ({ \ 120 int ret = MT_SPM_SYSRAM_R(MT_SPM_SYSRAM_SUSPEND, _type, _val); \ 121 ret; \ 122 }) 123 124 /* SPM trace low power */ 125 #define MT_SPM_TRACE_LP_U32_WR(_type, _val) \ 126 ({ \ 127 mmio_write_32( \ 128 (MT_SPM_SYSRAM_LP_BASE + MT_SPM_SYSRAM_SLOT(_type)), \ 129 _val); \ 130 }) 131 132 #define MT_SPM_TRACE_LP_WR(_type, _val, _sz) \ 133 ({ \ 134 int ret = MT_SPM_SYSRAM_W(MT_SPM_SYSRAM_LP, _type, _val, _sz); \ 135 ret; \ 136 }) 137 138 #define MT_SPM_TRACE_LP_U32_RD(_type, _val) \ 139 ({ \ 140 MT_SPM_SYSRAM_R_U32( \ 141 (MT_SPM_SYSRAM_LP_BASE + MT_SPM_SYSRAM_SLOT(_type)), \ 142 _val); \ 143 }) 144 145 #define MT_SPM_TRACE_LP_RD(_type, _val) \ 146 ({ \ 147 int ret = MT_SPM_SYSRAM_R(MT_SPM_SYSRAM_LP, _type, _val); \ 148 ret; \ 149 }) 150 151 #define MT_SPM_TRACE_LP_RINGBUF(_pval, _sz) \ 152 ({ \ 153 int ret = mt_spm_sysram_lp_ringbuf_add(_pval, _sz); \ 154 ret; \ 155 }) 156 157 int mt_spm_sysram_lp_ringbuf_add(const void *val, unsigned int sz); 158 159 int mt_spm_sysram_write(int section, int type, const void *val, 160 unsigned int sz); 161 int mt_spm_sysram_read(int section, int type, void *val); 162 163 int mt_spm_sysram_init(unsigned int magic); 164 #else 165 /* SPM trace common */ 166 #define MT_SPM_TRACE_INIT(_magic) 167 #define MT_SPM_TRACE_COMMON_U32_WR(type, val) 168 #define MT_SPM_TRACE_COMMON_WR(val) 169 #define MT_SPM_TRACE_COMMON_U32_RD(type, val) 170 #define MT_SPM_TRACE_COMMON_RD(val) 171 172 /* SPM trace suspend */ 173 #define MT_SPM_TRACE_SUSPEND_U32_WR(type, val) 174 #define MT_SPM_TRACE_SUSPEND_WR(val) 175 #define MT_SPM_TRACE_SUSPEND_U32_RD(type, val) 176 #define MT_SPM_TRACE_SUSPEND_RD(val) 177 178 /* SPM trace low power */ 179 #define MT_SPM_TRACE_LP_U32_WR(type, val) 180 #define MT_SPM_TRACE_LP_WR(val) 181 #define MT_SPM_TRACE_LP_U32_RD(type, val) 182 #define MT_SPM_TRACE_LP_RD(val) 183 #define MT_SPM_TRACE_LP_RINGBUF(pval, sz) 184 185 #define mt_spm_sysram_lp_ringbuf_add(_val, _sz) 186 #define mt_spm_sysram_write(_s, _type, _val, _sz) 187 #define mt_spm_sysram_read(_s, _type, _val) 188 #define mt_spm_sysram_init(_magic) 189 #endif 190 191 #endif /* MT_SPM_TRACE_H */ 192