1/* 2 * Copyright (c) 2020-2024, Arm Limited. All rights reserved. 3 * 4 * SPDX-License-Identifier: BSD-3-Clause 5 */ 6 7/* If SCMI power domain control is enabled */ 8#if TC_SCMI_PD_CTRL_EN 9#define GPU_SCMI_PD_IDX (PLAT_MAX_CPUS_PER_CLUSTER + 1) 10#define DPU_SCMI_PD_IDX (PLAT_MAX_CPUS_PER_CLUSTER + 2) 11#endif /* TC_SCMI_PD_CTRL_EN */ 12 13/* Use SCMI controlled clocks */ 14#if TC_DPU_USE_SCMI_CLK 15#define DPU_CLK_ATTR1 \ 16 clocks = <&scmi_clk 0>; \ 17 clock-names = "aclk" 18 19#define DPU_CLK_ATTR2 \ 20 clocks = <&scmi_clk 1>; \ 21 clock-names = "pxclk" 22 23#define DPU_CLK_ATTR3 \ 24 clocks = <&scmi_clk 2>; \ 25 clock-names = "pxclk" \ 26/* Use fixed clocks */ 27#else /* !TC_DPU_USE_SCMI_CLK */ 28#define DPU_CLK_ATTR1 \ 29 clocks = <&dpu_aclk>; \ 30 clock-names = "aclk" 31 32#define DPU_CLK_ATTR2 \ 33 clocks = <&dpu_pixel_clk>, <&dpu_aclk>; \ 34 clock-names = "pxclk", "aclk" 35 36#define DPU_CLK_ATTR3 DPU_CLK_ATTR2 37#endif /* !TC_DPU_USE_SCMI_CLK */ 38 39/ { 40 compatible = "arm,tc"; 41 interrupt-parent = <&gic>; 42 #address-cells = <2>; 43 #size-cells = <2>; 44 45 aliases { 46 serial0 = &os_uart; 47 }; 48 49 cpus { 50 #address-cells = <1>; 51 #size-cells = <0>; 52 53 cpu-map { 54 cluster0 { 55 core0 { 56 cpu = <&CPU0>; 57 }; 58 core1 { 59 cpu = <&CPU1>; 60 }; 61 core2 { 62 cpu = <&CPU2>; 63 }; 64 core3 { 65 cpu = <&CPU3>; 66 }; 67 core4 { 68 cpu = <&CPU4>; 69 }; 70 core5 { 71 cpu = <&CPU5>; 72 }; 73 core6 { 74 cpu = <&CPU6>; 75 }; 76 core7 { 77 cpu = <&CPU7>; 78 }; 79 }; 80 }; 81 82 /* 83 * The timings below are just to demonstrate working cpuidle. 84 * These values may be inaccurate. 85 */ 86 idle-states { 87 entry-method = "psci"; 88 89 CPU_SLEEP_0: cpu-sleep-0 { 90 compatible = "arm,idle-state"; 91 arm,psci-suspend-param = <0x0010000>; 92 local-timer-stop; 93 entry-latency-us = <300>; 94 exit-latency-us = <1200>; 95 min-residency-us = <2000>; 96 }; 97 CLUSTER_SLEEP_0: cluster-sleep-0 { 98 compatible = "arm,idle-state"; 99 arm,psci-suspend-param = <0x1010000>; 100 local-timer-stop; 101 entry-latency-us = <400>; 102 exit-latency-us = <1200>; 103 min-residency-us = <2500>; 104 }; 105 }; 106 107 CPU0:cpu@0 { 108 device_type = "cpu"; 109 compatible = "arm,armv8"; 110 reg = <0x0>; 111 enable-method = "psci"; 112 clocks = <&scmi_dvfs 0>; 113 cpu-idle-states = <&CPU_SLEEP_0 &CLUSTER_SLEEP_0>; 114 capacity-dmips-mhz = <LIT_CAPACITY>; 115 }; 116 117 CPU1:cpu@100 { 118 device_type = "cpu"; 119 compatible = "arm,armv8"; 120 reg = <0x100>; 121 enable-method = "psci"; 122 clocks = <&scmi_dvfs 0>; 123 cpu-idle-states = <&CPU_SLEEP_0 &CLUSTER_SLEEP_0>; 124 capacity-dmips-mhz = <LIT_CAPACITY>; 125 }; 126 127 CPU2:cpu@200 { 128 device_type = "cpu"; 129 compatible = "arm,armv8"; 130 reg = <0x200>; 131 enable-method = "psci"; 132 cpu-idle-states = <&CPU_SLEEP_0 &CLUSTER_SLEEP_0>; 133 }; 134 135 CPU3:cpu@300 { 136 device_type = "cpu"; 137 compatible = "arm,armv8"; 138 reg = <0x300>; 139 enable-method = "psci"; 140 cpu-idle-states = <&CPU_SLEEP_0 &CLUSTER_SLEEP_0>; 141 }; 142 143 CPU4:cpu@400 { 144 device_type = "cpu"; 145 compatible = "arm,armv8"; 146 reg = <0x400>; 147 enable-method = "psci"; 148 clocks = <&scmi_dvfs 1>; 149 cpu-idle-states = <&CPU_SLEEP_0 &CLUSTER_SLEEP_0>; 150 capacity-dmips-mhz = <MID_CAPACITY>; 151 }; 152 153 CPU5:cpu@500 { 154 device_type = "cpu"; 155 compatible = "arm,armv8"; 156 reg = <0x500>; 157 enable-method = "psci"; 158 clocks = <&scmi_dvfs 1>; 159 cpu-idle-states = <&CPU_SLEEP_0 &CLUSTER_SLEEP_0>; 160 capacity-dmips-mhz = <MID_CAPACITY>; 161 }; 162 163 CPU6:cpu@600 { 164 device_type = "cpu"; 165 compatible = "arm,armv8"; 166 reg = <0x600>; 167 enable-method = "psci"; 168 cpu-idle-states = <&CPU_SLEEP_0 &CLUSTER_SLEEP_0>; 169 }; 170 171 CPU7:cpu@700 { 172 device_type = "cpu"; 173 compatible = "arm,armv8"; 174 reg = <0x700>; 175 enable-method = "psci"; 176 cpu-idle-states = <&CPU_SLEEP_0 &CLUSTER_SLEEP_0>; 177 }; 178 }; 179 180 reserved-memory { 181 #address-cells = <2>; 182 #size-cells = <2>; 183 ranges; 184 185 linux,cma { 186 compatible = "shared-dma-pool"; 187 reusable; 188 size = <0x0 0x8000000>; 189 linux,cma-default; 190 }; 191 192 optee { 193 compatible = "restricted-dma-pool"; 194 reg = <0x0 TC_NS_OPTEE_BASE 0x0 TC_NS_OPTEE_SIZE>; 195 }; 196 197 }; 198 199 memory { 200 device_type = "memory"; 201 reg = <0x0 TC_NS_DRAM1_BASE 0x0 TC_NS_DRAM1_SIZE>, 202 <HI(PLAT_ARM_DRAM2_BASE) LO(PLAT_ARM_DRAM2_BASE) 203 HI(TC_NS_DRAM2_SIZE) LO(TC_NS_DRAM2_SIZE)>; 204 }; 205 206 psci { 207 compatible = "arm,psci-1.0", "arm,psci-0.2"; 208 method = "smc"; 209 }; 210 211 cpu-pmu-little { 212 compatible = LIT_CPU_PMU_COMPATIBLE; 213 interrupts = <GIC_PPI 7 IRQ_TYPE_LEVEL_HIGH &ppi_partition_little>; 214 status = "okay"; 215 }; 216 217 cpu-pmu-mid { 218 compatible = MID_CPU_PMU_COMPATIBLE; 219 interrupts = <GIC_PPI 7 IRQ_TYPE_LEVEL_HIGH &ppi_partition_mid>; 220 status = "okay"; 221 }; 222 223 cpu-pmu-big { 224 compatible = BIG_CPU_PMU_COMPATIBLE; 225 interrupts = <GIC_PPI 7 IRQ_TYPE_LEVEL_HIGH &ppi_partition_big>; 226 status = "okay"; 227 }; 228 229 sram: sram@6000000 { 230 compatible = "mmio-sram"; 231 reg = <0x0 PLAT_ARM_NSRAM_BASE 0x0 PLAT_ARM_NSRAM_SIZE>; 232 233 #address-cells = <1>; 234 #size-cells = <1>; 235 ranges = <0 0x0 PLAT_ARM_NSRAM_BASE PLAT_ARM_NSRAM_SIZE>; 236 237 cpu_scp_scmi_a2p: scp-shmem@0 { 238 compatible = "arm,scmi-shmem"; 239 reg = <0x0 0x80>; 240 }; 241 }; 242 243 mbox_db_rx: mhu@MHU_RX_ADDR { 244 compatible = MHU_RX_COMPAT; 245 reg = <0x0 ADDRESSIFY(MHU_RX_ADDR) 0x0 MHU_OFFSET>; 246 clocks = <&soc_refclk>; 247 clock-names = "apb_pclk"; 248 #mbox-cells = <MHU_MBOX_CELLS>; 249 interrupts = <GIC_SPI MHU_RX_INT_NUM IRQ_TYPE_LEVEL_HIGH 0>; 250 interrupt-names = MHU_RX_INT_NAME; 251 }; 252 253 mbox_db_tx: mhu@MHU_TX_ADDR { 254 compatible = MHU_TX_COMPAT; 255 reg = <0x0 ADDRESSIFY(MHU_TX_ADDR) 0x0 MHU_OFFSET>; 256 clocks = <&soc_refclk>; 257 clock-names = "apb_pclk"; 258 #mbox-cells = <MHU_MBOX_CELLS>; 259 interrupt-names = MHU_TX_INT_NAME; 260 }; 261 262 firmware { 263 scmi { 264 compatible = "arm,scmi"; 265 mbox-names = "tx", "rx"; 266 #address-cells = <1>; 267 #size-cells = <0>; 268 269#if TC_SCMI_PD_CTRL_EN 270 scmi_devpd: protocol@11 { 271 reg = <0x11>; 272 #power-domain-cells = <1>; 273 }; 274#endif /* TC_SCMI_PD_CTRL_EN */ 275 276 scmi_dvfs: protocol@13 { 277 reg = <0x13>; 278 #clock-cells = <1>; 279 }; 280 281 scmi_clk: protocol@14 { 282 reg = <0x14>; 283 #clock-cells = <1>; 284 }; 285 }; 286 }; 287 288 gic: interrupt-controller@GIC_CTRL_ADDR { 289 compatible = "arm,gic-v3"; 290 #address-cells = <2>; 291 #interrupt-cells = <4>; 292 #size-cells = <2>; 293 ranges; 294 interrupt-controller; 295 reg = <0x0 0x30000000 0 0x10000>, /* GICD */ 296 <0x0 0x30080000 0 GIC_GICR_OFFSET>; /* GICR */ 297 interrupts = <GIC_PPI 0x9 IRQ_TYPE_LEVEL_LOW 0>; 298 }; 299 300 timer { 301 compatible = "arm,armv8-timer"; 302 interrupts = <GIC_PPI 13 IRQ_TYPE_LEVEL_LOW 0>, 303 <GIC_PPI 14 IRQ_TYPE_LEVEL_LOW 0>, 304 <GIC_PPI 11 IRQ_TYPE_LEVEL_LOW 0>, 305 <GIC_PPI 10 IRQ_TYPE_LEVEL_LOW 0>; 306 }; 307 308 spe-pmu-mid { 309 compatible = "arm,statistical-profiling-extension-v1"; 310 interrupts = <GIC_PPI 1 IRQ_TYPE_LEVEL_HIGH &ppi_partition_mid>; 311 status = "disabled"; 312 }; 313 314 spe-pmu-big { 315 compatible = "arm,statistical-profiling-extension-v1"; 316 interrupts = <GIC_PPI 1 IRQ_TYPE_LEVEL_HIGH &ppi_partition_big>; 317 status = "disabled"; 318 }; 319 320 soc_refclk: refclk { 321 compatible = "fixed-clock"; 322 #clock-cells = <0>; 323 clock-frequency = <1000000000>; 324 clock-output-names = "apb_pclk"; 325 }; 326 327 soc_refclk60mhz: refclk60mhz { 328 compatible = "fixed-clock"; 329 #clock-cells = <0>; 330 clock-frequency = <60000000>; 331 clock-output-names = "iofpga_clk"; 332 }; 333 334 soc_uartclk: uartclk { 335 compatible = "fixed-clock"; 336 #clock-cells = <0>; 337 clock-frequency = <TC_UARTCLK>; 338 clock-output-names = "uartclk"; 339 }; 340 341 /* soc_uart0 on FPGA, ap_ns_uart on FVP */ 342 os_uart: serial@2a400000 { 343 compatible = "arm,pl011", "arm,primecell"; 344 reg = <0x0 0x2A400000 0x0 UART_OFFSET>; 345 interrupts = <GIC_SPI 63 IRQ_TYPE_LEVEL_HIGH 0>; 346 clocks = <&soc_uartclk>, <&soc_refclk>; 347 clock-names = "uartclk", "apb_pclk"; 348 status = "okay"; 349 }; 350 351#if !TC_DPU_USE_SCMI_CLK 352 dpu_aclk: dpu_aclk { 353 compatible = "fixed-clock"; 354 #clock-cells = <0>; 355 clock-frequency = <LCD_TIMING_CLK>; 356 clock-output-names = "fpga:dpu_aclk"; 357 }; 358 359 dpu_pixel_clk: dpu-pixel-clk { 360 compatible = "fixed-clock"; 361 #clock-cells = <0>; 362 clock-frequency = <LCD_TIMING_CLK>; 363 clock-output-names = "pxclk"; 364 }; 365#endif /* !TC_DPU_USE_SCMI_CLK */ 366 367#if TC_DPU_USE_SIMPLE_PANEL 368 vpanel { 369 compatible = "panel-dpi"; 370 post-init-providers = <&pl0>; 371 port { 372 lcd_in: endpoint { 373 remote-endpoint = <&dp_pl0_out0>; 374 }; 375 }; 376 377 panel-timing { 378 LCD_TIMING; 379 }; 380 }; 381 382#else 383 vencoder { 384 compatible = "drm,virtual-encoder"; 385 port { 386 lcd_in: endpoint { 387 remote-endpoint = <&dp_pl0_out0>; 388 }; 389 }; 390 391 display-timings { 392 timing-panel { 393 LCD_TIMING; 394 }; 395 }; 396 397 }; 398#endif 399 ethernet: ethernet@ETHERNET_ADDR { 400 reg = <0x0 ADDRESSIFY(ETHERNET_ADDR) 0x0 0x10000>; 401 interrupts = <GIC_SPI ETHERNET_INT IRQ_TYPE_LEVEL_HIGH 0>; 402 403 reg-io-width = <2>; 404 smsc,irq-push-pull; 405 }; 406 407 bp_clock24mhz: clock24mhz { 408 compatible = "fixed-clock"; 409 #clock-cells = <0>; 410 clock-frequency = <24000000>; 411 clock-output-names = "bp:clock24mhz"; 412 }; 413 414 sysreg: sysreg@SYS_REGS_ADDR { 415 compatible = "arm,vexpress-sysreg"; 416 reg = <0x0 ADDRESSIFY(SYS_REGS_ADDR) 0x0 0x1000>; 417 gpio-controller; 418 #gpio-cells = <2>; 419 }; 420 421 fixed_3v3: v2m-3v3 { 422 compatible = "regulator-fixed"; 423 regulator-name = "3V3"; 424 regulator-min-microvolt = <3300000>; 425 regulator-max-microvolt = <3300000>; 426 regulator-always-on; 427 }; 428 429 mmci: mmci@MMC_ADDR { 430 compatible = "arm,pl180", "arm,primecell"; 431 reg = <0x0 ADDRESSIFY(MMC_ADDR) 0x0 0x1000>; 432 interrupts = <GIC_SPI MMC_INT_0 IRQ_TYPE_LEVEL_HIGH 0>, 433 <GIC_SPI MMC_INT_1 IRQ_TYPE_LEVEL_HIGH 0>; 434 wp-gpios = <&sysreg 1 0>; 435 bus-width = <4>; 436 max-frequency = <25000000>; 437 vmmc-supply = <&fixed_3v3>; 438 clocks = <&bp_clock24mhz>, <&bp_clock24mhz>; 439 clock-names = "mclk", "apb_pclk"; 440 }; 441 442 gpu_clk: gpu_clk { 443 compatible = "fixed-clock"; 444 #clock-cells = <0>; 445 clock-frequency = <1000000000>; 446 }; 447 448 gpu_core_clk: gpu_core_clk { 449 compatible = "fixed-clock"; 450 #clock-cells = <0>; 451 clock-frequency = <1000000000>; 452 }; 453 454 gpu: gpu@2d000000 { 455 compatible = "arm,mali-midgard"; 456 reg = <0x0 0x2d000000 0x0 0x200000>; 457 clocks = <&gpu_core_clk>; 458 clock-names = "shadercores"; 459#if TC_SCMI_PD_CTRL_EN 460 power-domains = <&scmi_devpd GPU_SCMI_PD_IDX>; 461 scmi-perf-domain = <3>; 462#endif /* TC_SCMI_PD_CTRL_EN */ 463 464 pbha { 465 int-id-override = <0 0x22>, <2 0x23>, <4 0x23>, <7 0x22>, 466 <8 0x22>, <9 0x22>, <10 0x22>, <11 0x22>, 467 <12 0x22>, <13 0x22>, <16 0x22>, <17 0x32>, 468 <18 0x32>, <19 0x22>, <20 0x22>, <21 0x32>, 469 <22 0x32>, <24 0x22>, <28 0x32>; 470 propagate-bits = <0x0f>; 471 }; 472 }; 473 474 power_model_simple { 475 /* 476 * Numbers used are irrelevant to Titan, 477 * it helps suppressing the kernel warnings. 478 */ 479 compatible = "arm,mali-simple-power-model"; 480 static-coefficient = <2427750>; 481 dynamic-coefficient = <4687>; 482 ts = <20000 2000 (-20) 2>; 483 thermal-zone = ""; 484 }; 485 486 smmu_600: smmu@2ce00000 { 487 compatible = "arm,smmu-v3"; 488 reg = <0 0x2ce00000 0 0x20000>; 489 interrupts = <GIC_SPI 75 IRQ_TYPE_EDGE_RISING 0>, 490 <GIC_SPI 74 IRQ_TYPE_EDGE_RISING 0>, 491 <GIC_SPI 76 IRQ_TYPE_EDGE_RISING 0>, 492 <GIC_SPI 77 IRQ_TYPE_EDGE_RISING 0>; 493 interrupt-names = "eventq", "priq", "cmdq-sync", "gerror"; 494 #iommu-cells = <1>; 495 status = "disabled"; 496 }; 497 498 smmu_700: iommu@3f000000 { 499 #iommu-cells = <1>; 500 compatible = "arm,smmu-v3"; 501 reg = <0x0 0x3f000000 0x0 0x5000000>; 502 interrupts = <GIC_SPI 228 IRQ_TYPE_EDGE_RISING 0>, 503 <GIC_SPI 229 IRQ_TYPE_EDGE_RISING 0>, 504 <GIC_SPI 230 IRQ_TYPE_EDGE_RISING 0>; 505 interrupt-names = "eventq", "cmdq-sync", "gerror"; 506 dma-coherent; 507 status = "disabled"; 508 }; 509 510 smmu_700_dpu: iommu@4002a00000 { 511 #iommu-cells = <1>; 512 compatible = "arm,smmu-v3"; 513 reg = <HI(0x4002a00000) LO(0x4002a00000) 0x0 0x5000000>; 514 interrupts = <GIC_SPI 481 IRQ_TYPE_EDGE_RISING 0>, 515 <GIC_SPI 482 IRQ_TYPE_EDGE_RISING 0>, 516 <GIC_SPI 483 IRQ_TYPE_EDGE_RISING 0>; 517 interrupt-names = "eventq", "cmdq-sync", "gerror"; 518 dma-coherent; 519 status = "disabled"; 520 }; 521 522 dp0: display@DPU_ADDR { 523 #address-cells = <1>; 524 #size-cells = <0>; 525 compatible = "arm,mali-d71"; 526 reg = <HI(ADDRESSIFY(DPU_ADDR)) LO(ADDRESSIFY(DPU_ADDR)) 0 0x20000>; 527 interrupts = <GIC_SPI DPU_IRQ IRQ_TYPE_LEVEL_HIGH 0>; 528 interrupt-names = "DPU"; 529 DPU_CLK_ATTR1; 530 531 pl0: pipeline@0 { 532 reg = <0>; 533 DPU_CLK_ATTR2; 534 pl_id = <0>; 535 ports { 536 #address-cells = <1>; 537 #size-cells = <0>; 538 port@0 { 539 reg = <0>; 540 dp_pl0_out0: endpoint { 541 remote-endpoint = <&lcd_in>; 542 }; 543 }; 544 }; 545 }; 546 547 pl1: pipeline@1 { 548 reg = <1>; 549 DPU_CLK_ATTR3; 550 pl_id = <1>; 551 ports { 552 #address-cells = <1>; 553 #size-cells = <0>; 554 port@0 { 555 reg = <0>; 556 }; 557 }; 558 }; 559 }; 560 561 /* 562 * L3 cache in the DSU is the Memory System Component (MSC) 563 * The MPAM registers are accessed through utility bus in the DSU 564 */ 565 dsu-msc0 { 566 compatible = "arm,mpam-msc"; 567 reg = <DSU_MPAM_ADDR 0x0 0x2000>; 568 }; 569 570 ete0 { 571 compatible = "arm,embedded-trace-extension"; 572 cpu = <&CPU0>; 573 }; 574 575 ete1 { 576 compatible = "arm,embedded-trace-extension"; 577 cpu = <&CPU1>; 578 }; 579 580 ete2 { 581 compatible = "arm,embedded-trace-extension"; 582 cpu = <&CPU2>; 583 }; 584 585 ete3 { 586 compatible = "arm,embedded-trace-extension"; 587 cpu = <&CPU3>; 588 }; 589 590 ete4 { 591 compatible = "arm,embedded-trace-extension"; 592 cpu = <&CPU4>; 593 }; 594 595 ete5 { 596 compatible = "arm,embedded-trace-extension"; 597 cpu = <&CPU5>; 598 }; 599 600 ete6 { 601 compatible = "arm,embedded-trace-extension"; 602 cpu = <&CPU6>; 603 }; 604 605 ete7 { 606 compatible = "arm,embedded-trace-extension"; 607 cpu = <&CPU7>; 608 }; 609 610 trbe { 611 compatible = "arm,trace-buffer-extension"; 612 interrupts = <GIC_PPI 2 IRQ_TYPE_LEVEL_LOW 0>; 613 }; 614 615 trusty { 616 #size-cells = <0x02>; 617 #address-cells = <0x02>; 618 ranges = <0x00>; 619 compatible = "android,trusty-v1"; 620 621 virtio { 622 compatible = "android,trusty-virtio-v1"; 623 }; 624 625 test { 626 compatible = "android,trusty-test-v1"; 627 }; 628 629 log { 630 compatible = "android,trusty-log-v1"; 631 }; 632 633 irq { 634 ipi-range = <0x08 0x0f 0x08>; 635 interrupt-ranges = <0x00 0x0f 0x00 0x10 0x1f 0x01 0x20 0x3f 0x02>; 636 interrupt-templates = <0x01 0x00 0x8001 0x01 0x01 0x04 0x8001 0x01 0x00 0x04>; 637 compatible = "android,trusty-irq-v1"; 638 }; 639 }; 640 641 /* used in U-boot, Linux doesn't care */ 642 arm_ffa { 643 compatible = "arm,ffa"; 644 method = "smc"; 645 }; 646}; 647