1/* 2 * Copyright (c) 2019-2024, Arm Limited. All rights reserved. 3 * 4 * SPDX-License-Identifier: BSD-3-Clause 5 */ 6 7#include <arch.h> 8#include <asm_macros.S> 9#include <common/bl_common.h> 10#include <cortex_a78.h> 11#include <cpu_macros.S> 12#include <plat_macros.S> 13#include "wa_cve_2022_23960_bhb_vector.S" 14 15/* Hardware handled coherency */ 16#if HW_ASSISTED_COHERENCY == 0 17#error "cortex_a78 must be compiled with HW_ASSISTED_COHERENCY enabled" 18#endif 19 20.globl cortex_a78_reset_func 21.globl cortex_a78_core_pwr_dwn 22 23#if WORKAROUND_CVE_2022_23960 24 wa_cve_2022_23960_bhb_vector_table CORTEX_A78_BHB_LOOP_COUNT, cortex_a78 25#endif /* WORKAROUND_CVE_2022_23960 */ 26 27/* Disable hardware page aggregation.Enables mitigation for `CVE-2024-5660` */ 28workaround_reset_start cortex_a78, CVE(2024, 5660), WORKAROUND_CVE_2024_5660 29 sysreg_bit_set CORTEX_A78_CPUECTLR_EL1, BIT(46) 30workaround_reset_end cortex_a78, CVE(2024, 5660) 31 32check_erratum_ls cortex_a78, CVE(2024, 5660), CPU_REV(1, 2) 33 34workaround_reset_start cortex_a78, ERRATUM(1688305), ERRATA_A78_1688305 35 sysreg_bit_set CORTEX_A78_ACTLR2_EL1, CORTEX_A78_ACTLR2_EL1_BIT_1 36workaround_reset_end cortex_a78, ERRATUM(1688305) 37 38check_erratum_ls cortex_a78, ERRATUM(1688305), CPU_REV(1, 0) 39 40workaround_reset_start cortex_a78, ERRATUM(1821534), ERRATA_A78_1821534 41 sysreg_bit_set CORTEX_A78_ACTLR2_EL1, CORTEX_A78_ACTLR2_EL1_BIT_2 42workaround_reset_end cortex_a78, ERRATUM(1821534) 43 44check_erratum_ls cortex_a78, ERRATUM(1821534), CPU_REV(1, 0) 45 46workaround_reset_start cortex_a78, ERRATUM(1941498), ERRATA_A78_1941498 47 sysreg_bit_set CORTEX_A78_CPUECTLR_EL1, CORTEX_A78_CPUECTLR_EL1_BIT_8 48workaround_reset_end cortex_a78, ERRATUM(1941498) 49 50check_erratum_ls cortex_a78, ERRATUM(1941498), CPU_REV(1, 1) 51 52workaround_reset_start cortex_a78, ERRATUM(1951500), ERRATA_A78_1951500 53 msr S3_6_c15_c8_0, xzr 54 ldr x0, =0x10E3900002 55 msr S3_6_c15_c8_2, x0 56 ldr x0, =0x10FFF00083 57 msr S3_6_c15_c8_3, x0 58 ldr x0, =0x2001003FF 59 msr S3_6_c15_c8_1, x0 60 61 mov x0, #1 62 msr S3_6_c15_c8_0, x0 63 ldr x0, =0x10E3800082 64 msr S3_6_c15_c8_2, x0 65 ldr x0, =0x10FFF00083 66 msr S3_6_c15_c8_3, x0 67 ldr x0, =0x2001003FF 68 msr S3_6_c15_c8_1, x0 69 70 mov x0, #2 71 msr S3_6_c15_c8_0, x0 72 ldr x0, =0x10E3800200 73 msr S3_6_c15_c8_2, x0 74 ldr x0, =0x10FFF003E0 75 msr S3_6_c15_c8_3, x0 76 ldr x0, =0x2001003FF 77 msr S3_6_c15_c8_1, x0 78workaround_reset_end cortex_a78, ERRATUM(1951500) 79 80check_erratum_range cortex_a78, ERRATUM(1951500), CPU_REV(1, 0), CPU_REV(1, 1) 81 82workaround_reset_start cortex_a78, ERRATUM(1952683), ERRATA_A78_1952683 83 ldr x0,=0x5 84 msr S3_6_c15_c8_0,x0 85 ldr x0,=0xEEE10A10 86 msr S3_6_c15_c8_2,x0 87 ldr x0,=0xFFEF0FFF 88 msr S3_6_c15_c8_3,x0 89 ldr x0,=0x0010F000 90 msr S3_6_c15_c8_4,x0 91 ldr x0,=0x0010F000 92 msr S3_6_c15_c8_5,x0 93 ldr x0,=0x40000080023ff 94 msr S3_6_c15_c8_1,x0 95 ldr x0,=0x6 96 msr S3_6_c15_c8_0,x0 97 ldr x0,=0xEE640F34 98 msr S3_6_c15_c8_2,x0 99 ldr x0,=0xFFEF0FFF 100 msr S3_6_c15_c8_3,x0 101 ldr x0,=0x40000080023ff 102 msr S3_6_c15_c8_1,x0 103workaround_reset_end cortex_a78, ERRATUM(1952683) 104 105check_erratum_ls cortex_a78, ERRATUM(1952683), CPU_REV(0, 0) 106 107workaround_reset_start cortex_a78, ERRATUM(2132060), ERRATA_A78_2132060 108 /* Apply the workaround. */ 109 mrs x1, CORTEX_A78_CPUECTLR_EL1 110 mov x0, #CORTEX_A78_CPUECTLR_EL1_PF_MODE_CNSRV 111 bfi x1, x0, #CPUECTLR_EL1_PF_MODE_LSB, #CPUECTLR_EL1_PF_MODE_WIDTH 112 msr CORTEX_A78_CPUECTLR_EL1, x1 113workaround_reset_end cortex_a78, ERRATUM(2132060) 114 115check_erratum_ls cortex_a78, ERRATUM(2132060), CPU_REV(1, 2) 116 117workaround_reset_start cortex_a78, ERRATUM(2242635), ERRATA_A78_2242635 118 ldr x0, =0x5 119 msr S3_6_c15_c8_0, x0 /* CPUPSELR_EL3 */ 120 ldr x0, =0x10F600E000 121 msr S3_6_c15_c8_2, x0 /* CPUPOR_EL3 */ 122 ldr x0, =0x10FF80E000 123 msr S3_6_c15_c8_3, x0 /* CPUPMR_EL3 */ 124 ldr x0, =0x80000000003FF 125 msr S3_6_c15_c8_1, x0 /* CPUPCR_EL3 */ 126workaround_reset_end cortex_a78, ERRATUM(2242635) 127 128check_erratum_range cortex_a78, ERRATUM(2242635), CPU_REV(1, 0), CPU_REV(1, 2) 129 130workaround_reset_start cortex_a78, ERRATUM(2376745), ERRATA_A78_2376745 131 sysreg_bit_set CORTEX_A78_ACTLR2_EL1, BIT(0) 132workaround_reset_end cortex_a78, ERRATUM(2376745) 133 134check_erratum_ls cortex_a78, ERRATUM(2376745), CPU_REV(1, 2) 135 136workaround_reset_start cortex_a78, ERRATUM(2395406), ERRATA_A78_2395406 137 sysreg_bit_set CORTEX_A78_ACTLR2_EL1, BIT(40) 138workaround_reset_end cortex_a78, ERRATUM(2395406) 139 140check_erratum_ls cortex_a78, ERRATUM(2395406), CPU_REV(1, 2) 141 142workaround_reset_start cortex_a78, ERRATUM(2742426), ERRATA_A78_2742426 143 /* Apply the workaround */ 144 mrs x1, CORTEX_A78_ACTLR5_EL1 145 bic x1, x1, #BIT(56) 146 orr x1, x1, #BIT(55) 147 msr CORTEX_A78_ACTLR5_EL1, x1 148workaround_reset_end cortex_a78, ERRATUM(2742426) 149 150check_erratum_ls cortex_a78, ERRATUM(2742426), CPU_REV(1, 2) 151 152workaround_runtime_start cortex_a78, ERRATUM(2772019), ERRATA_A78_2772019 153 /* dsb before isb of power down sequence */ 154 dsb sy 155workaround_runtime_end cortex_a78, ERRATUM(2772019) 156 157check_erratum_ls cortex_a78, ERRATUM(2772019), CPU_REV(1, 2) 158 159workaround_reset_start cortex_a78, ERRATUM(2779479), ERRATA_A78_2779479 160 sysreg_bit_set CORTEX_A78_ACTLR3_EL1, BIT(47) 161workaround_reset_end cortex_a78, ERRATUM(2779479) 162 163check_erratum_ls cortex_a78, ERRATUM(2779479), CPU_REV(1, 2) 164 165workaround_reset_start cortex_a78, CVE(2022, 23960), WORKAROUND_CVE_2022_23960 166#if IMAGE_BL31 167 /* 168 * The Cortex-X1 generic vectors are overridden to apply errata 169 * mitigation on exception entry from lower ELs. 170 */ 171 override_vector_table wa_cve_vbar_cortex_a78 172#endif /* IMAGE_BL31 */ 173workaround_reset_end cortex_a78, CVE(2022, 23960) 174 175check_erratum_chosen cortex_a78, CVE(2022, 23960), WORKAROUND_CVE_2022_23960 176 177cpu_reset_func_start cortex_a78 178#if ENABLE_FEAT_AMU 179 /* Make sure accesses from EL0/EL1 and EL2 are not trapped to EL3 */ 180 sysreg_bit_clear actlr_el3, CORTEX_A78_ACTLR_TAM_BIT 181 182 /* Make sure accesses from non-secure EL0/EL1 are not trapped to EL2 */ 183 sysreg_bit_clear actlr_el2, CORTEX_A78_ACTLR_TAM_BIT 184 185 /* Enable group0 counters */ 186 mov x0, #CORTEX_A78_AMU_GROUP0_MASK 187 msr CPUAMCNTENSET0_EL0, x0 188 189 /* Enable group1 counters */ 190 mov x0, #CORTEX_A78_AMU_GROUP1_MASK 191 msr CPUAMCNTENSET1_EL0, x0 192#endif 193cpu_reset_func_end cortex_a78 194 195 /* --------------------------------------------- 196 * HW will do the cache maintenance while powering down 197 * --------------------------------------------- 198 */ 199func cortex_a78_core_pwr_dwn 200 sysreg_bit_set CORTEX_A78_CPUPWRCTLR_EL1, CORTEX_A78_CPUPWRCTLR_EL1_CORE_PWRDN_EN_BIT 201 202 apply_erratum cortex_a78, ERRATUM(2772019), ERRATA_A78_2772019, NO_GET_CPU_REV 203 204 isb 205 ret 206endfunc cortex_a78_core_pwr_dwn 207 208 /* --------------------------------------------- 209 * This function provides cortex_a78 specific 210 * register information for crash reporting. 211 * It needs to return with x6 pointing to 212 * a list of register names in ascii and 213 * x8 - x15 having values of registers to be 214 * reported. 215 * --------------------------------------------- 216 */ 217.section .rodata.cortex_a78_regs, "aS" 218cortex_a78_regs: /* The ascii list of register names to be reported */ 219 .asciz "cpuectlr_el1", "" 220 221func cortex_a78_cpu_reg_dump 222 adr x6, cortex_a78_regs 223 mrs x8, CORTEX_A78_CPUECTLR_EL1 224 ret 225endfunc cortex_a78_cpu_reg_dump 226 227declare_cpu_ops cortex_a78, CORTEX_A78_MIDR, \ 228 cortex_a78_reset_func, \ 229 cortex_a78_core_pwr_dwn 230