1 /* 2 * Copyright (c) 2013-2026, Arm Limited and Contributors. All rights reserved. 3 * 4 * SPDX-License-Identifier: BSD-3-Clause 5 */ 6 7 #include <assert.h> 8 9 #include <platform_def.h> 10 11 #include <arch.h> 12 #include <arch_features.h> 13 #include <arch_helpers.h> 14 #include <bl1/bl1.h> 15 #include <common/bl_common.h> 16 #include <common/build_message.h> 17 #include <common/debug.h> 18 #include <context.h> 19 #include <drivers/auth/auth_mod.h> 20 #include <drivers/auth/crypto_mod.h> 21 #include <drivers/console.h> 22 #include <lib/bootmarker_capture.h> 23 #include <lib/cpus/errata.h> 24 #include <lib/el3_runtime/context_mgmt.h> 25 #include <lib/extensions/pauth.h> 26 #include <lib/pmf/pmf.h> 27 #include <lib/utils.h> 28 #include <plat/common/platform.h> 29 #include <smccc_helpers.h> 30 #include <tools_share/uuid.h> 31 32 #include "bl1_private.h" 33 34 static void bl1_load_bl2(void); 35 36 #if ENABLE_PAUTH 37 uint64_t bl1_apiakey[2]; 38 #endif 39 40 #if ENABLE_RUNTIME_INSTRUMENTATION 41 PMF_REGISTER_SERVICE(bl_svc, PMF_RT_INSTR_SVC_ID, 42 BL_TOTAL_IDS, PMF_DUMP_ENABLE) 43 #endif 44 45 /******************************************************************************* 46 * Setup function for BL1. 47 * Also perform late architectural and platform specific initialization. 48 * It also queries the platform to load and run next BL image. Only called 49 * by the primary cpu after a cold boot. 50 ******************************************************************************/ 51 void __no_pauth bl1_main(void) 52 { 53 unsigned int image_id; 54 55 /* Enable early console if EARLY_CONSOLE flag is enabled */ 56 plat_setup_early_console(); 57 58 /* Perform early platform-specific setup */ 59 bl1_early_platform_setup(); 60 61 /* Perform late platform-specific setup */ 62 bl1_plat_arch_setup(); 63 64 /* Init registers that don't get contexted */ 65 cm_manage_extensions_el3(plat_my_core_pos()); 66 67 /* When BL2 runs in Secure world, it needs a coherent context. */ 68 #if !BL2_RUNS_AT_EL3 69 /* Init per-world context registers. */ 70 cm_manage_extensions_per_world(); 71 #endif 72 73 #if ENABLE_RUNTIME_INSTRUMENTATION 74 PMF_CAPTURE_TIMESTAMP(bl_svc, BL1_ENTRY, PMF_CACHE_MAINT); 75 #endif 76 77 /* Announce our arrival */ 78 NOTICE(FIRMWARE_WELCOME_STR); 79 NOTICE("BL1: %s\n", build_version_string); 80 NOTICE("BL1: %s\n", build_message); 81 82 INFO("BL1: RAM %p - %p\n", (void *)BL1_RAM_BASE, (void *)BL1_RAM_LIMIT); 83 84 print_errata_status(); 85 86 #if ENABLE_ASSERTIONS 87 u_register_t val; 88 /* 89 * Ensure that MMU/Caches and coherency are turned on 90 */ 91 #ifdef __aarch64__ 92 val = read_sctlr_el3(); 93 #else 94 val = read_sctlr(); 95 #endif 96 assert((val & SCTLR_M_BIT) != 0); 97 assert((val & SCTLR_C_BIT) != 0); 98 assert((val & SCTLR_I_BIT) != 0); 99 /* 100 * Check that Cache Writeback Granule (CWG) in CTR_EL0 matches the 101 * provided platform value 102 */ 103 val = (read_ctr_el0() >> CTR_CWG_SHIFT) & CTR_CWG_MASK; 104 /* 105 * If CWG is zero, then no CWG information is available but we can 106 * at least check the platform value is less than the architectural 107 * maximum. 108 */ 109 if (val != 0) 110 assert(CACHE_WRITEBACK_GRANULE == SIZE_FROM_LOG2_WORDS(val)); 111 else 112 assert(CACHE_WRITEBACK_GRANULE <= MAX_CACHE_LINE_SIZE); 113 #endif /* ENABLE_ASSERTIONS */ 114 115 /* Perform remaining generic architectural setup from EL3 */ 116 bl1_arch_setup(); 117 118 crypto_mod_init(); 119 120 /* Initialize authentication module */ 121 auth_mod_init(); 122 123 /* Initialize the measured boot */ 124 bl1_plat_mboot_init(); 125 126 if (is_feat_crypto_supported()) { 127 disable_fpregs_traps_el3(); 128 } 129 130 /* Perform platform setup in BL1. */ 131 bl1_platform_setup(); 132 133 /* Get the image id of next image to load and run. */ 134 image_id = bl1_plat_get_next_image_id(); 135 136 /* 137 * We currently interpret any image id other than 138 * BL2_IMAGE_ID as the start of firmware update. 139 */ 140 if (image_id == BL2_IMAGE_ID) 141 bl1_load_bl2(); 142 else 143 NOTICE("BL1-FWU: *******FWU Process Started*******\n"); 144 145 if (is_feat_crypto_supported()) { 146 enable_fpregs_traps_el3(); 147 } 148 149 /* Teardown the measured boot driver */ 150 bl1_plat_mboot_finish(); 151 152 crypto_mod_finish(); 153 154 bl1_prepare_next_image(image_id); 155 156 #if ENABLE_RUNTIME_INSTRUMENTATION 157 PMF_CAPTURE_TIMESTAMP(bl_svc, BL1_EXIT, PMF_CACHE_MAINT); 158 #endif 159 160 console_flush(); 161 162 /* Disable pointer authentication before jumping to next boot image. */ 163 if (is_feat_pauth_supported()) { 164 pauth_disable_el3(); 165 } 166 } 167 168 /******************************************************************************* 169 * This function locates and loads the BL2 raw binary image in the trusted SRAM. 170 * Called by the primary cpu after a cold boot. 171 * TODO: Add support for alternative image load mechanism e.g using virtio/elf 172 * loader etc. 173 ******************************************************************************/ 174 static void bl1_load_bl2(void) 175 { 176 image_desc_t *desc; 177 image_info_t *info; 178 int err; 179 180 /* Get the image descriptor */ 181 desc = bl1_plat_get_image_desc(BL2_IMAGE_ID); 182 assert(desc != NULL); 183 184 /* Get the image info */ 185 info = &desc->image_info; 186 INFO("BL1: Loading BL2\n"); 187 188 err = bl1_plat_handle_pre_image_load(BL2_IMAGE_ID); 189 if (err != 0) { 190 ERROR("Failure in pre image load handling of BL2 (%d)\n", err); 191 plat_error_handler(err); 192 } 193 194 err = load_auth_image(BL2_IMAGE_ID, info); 195 if (err != 0) { 196 ERROR("Failed to load BL2 firmware.\n"); 197 plat_error_handler(err); 198 } 199 200 /* Allow platform to handle image information. */ 201 err = bl1_plat_handle_post_image_load(BL2_IMAGE_ID); 202 if (err != 0) { 203 ERROR("Failure in post image load handling of BL2 (%d)\n", err); 204 plat_error_handler(err); 205 } 206 207 NOTICE("BL1: Booting BL2\n"); 208 } 209 210 /******************************************************************************* 211 * Function called just before handing over to the next BL to inform the user 212 * about the boot progress. In debug mode, also print details about the BL 213 * image's execution context. 214 ******************************************************************************/ 215 void bl1_print_next_bl_ep_info(const entry_point_info_t *bl_ep_info) 216 { 217 #ifdef __aarch64__ 218 NOTICE("BL1: Booting BL31\n"); 219 #else 220 NOTICE("BL1: Booting BL32\n"); 221 #endif /* __aarch64__ */ 222 print_entry_point_info(bl_ep_info); 223 } 224 225 #if SPIN_ON_BL1_EXIT 226 void print_debug_loop_message(void) 227 { 228 NOTICE("BL1: Debug loop, spinning forever\n"); 229 NOTICE("BL1: Please connect the debugger to continue\n"); 230 } 231 #endif 232 233 /******************************************************************************* 234 * Top level handler for servicing BL1 SMCs. 235 ******************************************************************************/ 236 u_register_t bl1_smc_handler(unsigned int smc_fid, 237 u_register_t x1, 238 u_register_t x2, 239 u_register_t x3, 240 u_register_t x4, 241 void *cookie, 242 void *handle, 243 unsigned int flags) 244 { 245 /* BL1 Service UUID */ 246 DEFINE_SVC_UUID2(bl1_svc_uid, 247 U(0xd46739fd), 0xcb72, 0x9a4d, 0xb5, 0x75, 248 0x67, 0x15, 0xd6, 0xf4, 0xbb, 0x4a); 249 250 251 #if TRUSTED_BOARD_BOOT 252 /* 253 * Dispatch FWU calls to FWU SMC handler and return its return 254 * value 255 */ 256 if (is_fwu_fid(smc_fid)) { 257 return bl1_fwu_smc_handler(smc_fid, x1, x2, x3, x4, cookie, 258 handle, flags); 259 } 260 #endif 261 262 switch (smc_fid) { 263 case BL1_SMC_CALL_COUNT: 264 SMC_RET1(handle, BL1_NUM_SMC_CALLS); 265 266 case BL1_SMC_UID: 267 SMC_UUID_RET(handle, bl1_svc_uid); 268 269 case BL1_SMC_VERSION: 270 SMC_RET1(handle, BL1_SMC_MAJOR_VER | BL1_SMC_MINOR_VER); 271 272 default: 273 WARN("Unimplemented BL1 SMC Call: 0x%x\n", smc_fid); 274 SMC_RET1(handle, SMC_UNK); 275 } 276 } 277 278 #if __aarch64__ 279 u_register_t bl1_smc_wrapper_aarch64(cpu_context_t *ctx) 280 { 281 u_register_t x1, x2, x3, x4; 282 unsigned int smc_fid, flags; 283 gp_regs_t *gpregs = get_gpregs_ctx(ctx); 284 285 smc_fid = read_ctx_reg(gpregs, CTX_GPREG_X0); 286 x1 = read_ctx_reg(gpregs, CTX_GPREG_X1); 287 x2 = read_ctx_reg(gpregs, CTX_GPREG_X2); 288 x3 = read_ctx_reg(gpregs, CTX_GPREG_X3); 289 x4 = read_ctx_reg(gpregs, CTX_GPREG_X4); 290 291 /* Copy SCR_EL3.NS bit to the flag to indicate caller's security */ 292 flags = read_scr_el3() & SCR_NS_BIT; 293 294 return bl1_smc_handler(smc_fid, x1, x2, x3, x4, NULL, ctx, flags); 295 } 296 #else 297 /******************************************************************************* 298 * BL1 SMC wrapper. This function is only used in AArch32 mode to ensure ABI 299 * compliance when invoking bl1_smc_handler. 300 ******************************************************************************/ 301 u_register_t bl1_smc_wrapper_aarch32(uint32_t smc_fid, 302 void *cookie, 303 void *handle, 304 unsigned int flags) 305 { 306 u_register_t x1, x2, x3, x4; 307 308 assert(handle != NULL); 309 310 get_smc_params_from_ctx(handle, x1, x2, x3, x4); 311 return bl1_smc_handler(smc_fid, x1, x2, x3, x4, cookie, handle, flags); 312 } 313 #endif 314