1 /* 2 * Copyright (c) 2020-2022, Intel Corporation. All rights reserved. 3 * Copyright (c) 2025, Altera Corporation. All rights reserved. 4 * 5 * SPDX-License-Identifier: BSD-3-Clause 6 */ 7 8 #include <assert.h> 9 #include <arch.h> 10 #include <arch_helpers.h> 11 #include <common/bl_common.h> 12 #include <drivers/arm/gicv2.h> 13 #include <drivers/ti/uart/uart_16550.h> 14 #include <lib/mmio.h> 15 #include <lib/xlat_tables/xlat_tables.h> 16 17 #include "ccu/ncore_ccu.h" 18 #include "socfpga_mailbox.h" 19 #include "socfpga_private.h" 20 21 static entry_point_info_t bl32_image_ep_info; 22 static entry_point_info_t bl33_image_ep_info; 23 24 entry_point_info_t *bl31_plat_get_next_image_ep_info(uint32_t type) 25 { 26 entry_point_info_t *next_image_info; 27 28 next_image_info = (type == NON_SECURE) ? 29 &bl33_image_ep_info : &bl32_image_ep_info; 30 31 /* None of the images on this platform can have 0x0 as the entrypoint */ 32 if (next_image_info->pc) { 33 return next_image_info; 34 } else { 35 return NULL; 36 } 37 } 38 39 void bl31_early_platform_setup2(u_register_t arg0, u_register_t arg1, 40 u_register_t arg2, u_register_t arg3) 41 { 42 static console_t console; 43 44 mmio_write_64(PLAT_SEC_ENTRY, 0); 45 46 console_16550_register(PLAT_INTEL_UART_BASE, PLAT_UART_CLOCK, 47 PLAT_BAUDRATE, &console); 48 /* 49 * Check params passed from BL31 should not be NULL, 50 */ 51 void *from_bl2 = (void *) arg0; 52 53 bl_params_t *params_from_bl2 = (bl_params_t *)from_bl2; 54 55 assert(params_from_bl2 != NULL); 56 57 /* 58 * Copy BL32 (if populated by BL31) and BL33 entry point information. 59 * They are stored in Secure RAM, in BL31's address space. 60 */ 61 62 if (params_from_bl2->h.type == PARAM_BL_PARAMS && 63 params_from_bl2->h.version >= VERSION_2) { 64 65 bl_params_node_t *bl_params = params_from_bl2->head; 66 67 while (bl_params != NULL) { 68 if (bl_params->image_id == BL33_IMAGE_ID) 69 bl33_image_ep_info = *bl_params->ep_info; 70 71 bl_params = bl_params->next_params_info; 72 } 73 } else { 74 struct socfpga_bl31_params *arg_from_bl2 = 75 (struct socfpga_bl31_params *) from_bl2; 76 77 assert(arg_from_bl2->h.type == PARAM_BL31); 78 assert(arg_from_bl2->h.version >= VERSION_1); 79 80 bl32_image_ep_info = *arg_from_bl2->bl32_ep_info; 81 bl33_image_ep_info = *arg_from_bl2->bl33_ep_info; 82 } 83 SET_SECURITY_STATE(bl33_image_ep_info.h.attr, NON_SECURE); 84 } 85 86 static const interrupt_prop_t s10_interrupt_props[] = { 87 PLAT_INTEL_SOCFPGA_G1S_IRQ_PROPS(GICV2_INTR_GROUP0), 88 PLAT_INTEL_SOCFPGA_G0_IRQ_PROPS(GICV2_INTR_GROUP0) 89 }; 90 91 static unsigned int target_mask_array[PLATFORM_CORE_COUNT]; 92 93 static const gicv2_driver_data_t plat_gicv2_gic_data = { 94 .gicd_base = PLAT_INTEL_SOCFPGA_GICD_BASE, 95 .gicc_base = PLAT_INTEL_SOCFPGA_GICC_BASE, 96 .interrupt_props = s10_interrupt_props, 97 .interrupt_props_num = ARRAY_SIZE(s10_interrupt_props), 98 .target_masks = target_mask_array, 99 .target_masks_num = ARRAY_SIZE(target_mask_array), 100 }; 101 102 /******************************************************************************* 103 * Perform any BL3-1 platform setup code 104 ******************************************************************************/ 105 void bl31_platform_setup(void) 106 { 107 socfpga_delay_timer_init(); 108 109 /* Initialize the gic cpu and distributor interfaces */ 110 gicv2_driver_init(&plat_gicv2_gic_data); 111 gicv2_distif_init(); 112 gicv2_pcpu_distif_init(); 113 gicv2_cpuif_enable(); 114 115 /* Signal secondary CPUs to jump to BL31 (BL2 = U-boot SPL) */ 116 mmio_write_64(PLAT_CPU_RELEASE_ADDR, 117 (uint64_t)plat_secondary_cpus_bl31_entry); 118 119 #if SIP_SVC_V3 120 /* 121 * Re-initialize the mailbox to include V3 specific routines. 122 * In V3, this re-initialize is required because prior to BL31, U-Boot 123 * SPL has its own mailbox settings and this initialization will 124 * override to those settings as required by the V3 framework. 125 */ 126 mailbox_init(); 127 #endif 128 129 mailbox_hps_stage_notify(HPS_EXECUTION_STATE_SSBL); 130 } 131 132 const mmap_region_t plat_dm_mmap[] = { 133 MAP_REGION_FLAT(DRAM_BASE, DRAM_SIZE, 134 MT_MEMORY | MT_RW | MT_NS), 135 MAP_REGION_FLAT(DEVICE1_BASE, DEVICE1_SIZE, 136 MT_DEVICE | MT_RW | MT_NS), 137 MAP_REGION_FLAT(DEVICE2_BASE, DEVICE2_SIZE, 138 MT_DEVICE | MT_RW | MT_SECURE), 139 MAP_REGION_FLAT(OCRAM_BASE, OCRAM_SIZE, 140 MT_NON_CACHEABLE | MT_RW | MT_SECURE), 141 MAP_REGION_FLAT(DEVICE3_BASE, DEVICE3_SIZE, 142 MT_DEVICE | MT_RW | MT_SECURE), 143 MAP_REGION_FLAT(MEM64_BASE, MEM64_SIZE, 144 MT_DEVICE | MT_RW | MT_NS), 145 MAP_REGION_FLAT(DEVICE4_BASE, DEVICE4_SIZE, 146 MT_DEVICE | MT_RW | MT_NS), 147 {0} 148 }; 149 150 /******************************************************************************* 151 * Perform the very early platform specific architectural setup here. At the 152 * moment this is only initializes the mmu in a quick and dirty way. 153 ******************************************************************************/ 154 void bl31_plat_arch_setup(void) 155 { 156 const mmap_region_t bl_regions[] = { 157 MAP_REGION_FLAT(BL31_BASE, BL31_END - BL31_BASE, 158 MT_MEMORY | MT_RW | MT_SECURE), 159 MAP_REGION_FLAT(BL_CODE_BASE, BL_CODE_END - BL_CODE_BASE, 160 MT_CODE | MT_SECURE), 161 MAP_REGION_FLAT(BL_RO_DATA_BASE, 162 BL_RO_DATA_END - BL_RO_DATA_BASE, 163 MT_RO_DATA | MT_SECURE), 164 #if USE_COHERENT_MEM 165 MAP_REGION_FLAT(BL_COHERENT_RAM_BASE, 166 BL_COHERENT_RAM_END - BL_COHERENT_RAM_BASE, 167 MT_DEVICE | MT_RW | MT_SECURE), 168 #endif 169 {0} 170 }; 171 172 setup_page_tables(bl_regions, plat_dm_mmap); 173 enable_mmu_el3(0); 174 } 175