1 /* 2 * Copyright (C) 2018 Marvell International Ltd. 3 * 4 * SPDX-License-Identifier: BSD-3-Clause 5 * https://spdx.org/licenses 6 */ 7 8 #include <assert.h> 9 10 #include <common/debug.h> 11 #include <drivers/arm/gicv2.h> 12 #include <drivers/console.h> 13 #include <drivers/delay_timer.h> 14 #include <drivers/marvell/cache_llc.h> 15 #include <lib/bakery_lock.h> 16 #include <lib/mmio.h> 17 #include <plat/common/platform.h> 18 19 #include <armada_common.h> 20 #include <marvell_pm.h> 21 #if MSS_SUPPORT 22 #include <mss_pm_ipc.h> 23 #endif 24 #include <plat_marvell.h> 25 #include <plat_pm_trace.h> 26 27 #define MVEBU_PRIVATE_UID_REG 0x30 28 #define MVEBU_RFU_GLOBL_SW_RST 0x84 29 #define MVEBU_CCU_RVBAR(cpu) (MVEBU_REGS_BASE + 0x640 + (cpu * 4)) 30 #define MVEBU_CCU_CPU_UN_RESET(cpu) (MVEBU_REGS_BASE + 0x650 + (cpu * 4)) 31 32 #define MPIDR_CPU_GET(mpidr) ((mpidr) & MPIDR_CPU_MASK) 33 #define MPIDR_CLUSTER_GET(mpidr) MPIDR_AFFLVL1_VAL((mpidr)) 34 35 #define MVEBU_GPIO_MASK(index) (1 << (index % 32)) 36 #define MVEBU_MPP_MASK(index) (0xF << (4 * (index % 8))) 37 #define MVEBU_GPIO_VALUE(index, value) (value << (index % 32)) 38 39 #define MVEBU_USER_CMD_0_REG (MVEBU_DRAM_MAC_BASE + 0x20) 40 #define MVEBU_USER_CMD_CH0_OFFSET 28 41 #define MVEBU_USER_CMD_CH0_MASK (1 << MVEBU_USER_CMD_CH0_OFFSET) 42 #define MVEBU_USER_CMD_CH0_EN (1 << MVEBU_USER_CMD_CH0_OFFSET) 43 #define MVEBU_USER_CMD_CS_OFFSET 24 44 #define MVEBU_USER_CMD_CS_MASK (0xF << MVEBU_USER_CMD_CS_OFFSET) 45 #define MVEBU_USER_CMD_CS_ALL (0xF << MVEBU_USER_CMD_CS_OFFSET) 46 #define MVEBU_USER_CMD_SR_OFFSET 6 47 #define MVEBU_USER_CMD_SR_MASK (0x3 << MVEBU_USER_CMD_SR_OFFSET) 48 #define MVEBU_USER_CMD_SR_ENTER (0x1 << MVEBU_USER_CMD_SR_OFFSET) 49 #define MVEBU_MC_PWR_CTRL_REG (MVEBU_DRAM_MAC_BASE + 0x54) 50 #define MVEBU_MC_AC_ON_DLY_OFFSET 8 51 #define MVEBU_MC_AC_ON_DLY_MASK (0xF << MVEBU_MC_AC_ON_DLY_OFFSET) 52 #define MVEBU_MC_AC_ON_DLY_DEF_VAR (8 << MVEBU_MC_AC_ON_DLY_OFFSET) 53 #define MVEBU_MC_AC_OFF_DLY_OFFSET 4 54 #define MVEBU_MC_AC_OFF_DLY_MASK (0xF << MVEBU_MC_AC_OFF_DLY_OFFSET) 55 #define MVEBU_MC_AC_OFF_DLY_DEF_VAR (0xC << MVEBU_MC_AC_OFF_DLY_OFFSET) 56 #define MVEBU_MC_PHY_AUTO_OFF_OFFSET 0 57 #define MVEBU_MC_PHY_AUTO_OFF_MASK (1 << MVEBU_MC_PHY_AUTO_OFF_OFFSET) 58 #define MVEBU_MC_PHY_AUTO_OFF_EN (1 << MVEBU_MC_PHY_AUTO_OFF_OFFSET) 59 60 /* this lock synchronize AP multiple cores execution with MSS */ 61 DEFINE_BAKERY_LOCK(pm_sys_lock); 62 63 /* Weak definitions may be overridden in specific board */ 64 #pragma weak plat_marvell_get_pm_cfg 65 66 /* AP806 CPU power down /power up definitions */ 67 enum CPU_ID { 68 CPU0, 69 CPU1, 70 CPU2, 71 CPU3 72 }; 73 74 #define REG_WR_VALIDATE_TIMEOUT (2000) 75 76 #define FEATURE_DISABLE_STATUS_REG \ 77 (MVEBU_REGS_BASE + 0x6F8230) 78 #define FEATURE_DISABLE_STATUS_CPU_CLUSTER_OFFSET 4 79 #define FEATURE_DISABLE_STATUS_CPU_CLUSTER_MASK \ 80 (0x1 << FEATURE_DISABLE_STATUS_CPU_CLUSTER_OFFSET) 81 82 #ifdef MVEBU_SOC_AP807 83 #define PWRC_CPUN_CR_PWR_DN_RQ_OFFSET 1 84 #define PWRC_CPUN_CR_LDO_BYPASS_RDY_OFFSET 0 85 #else 86 #define PWRC_CPUN_CR_PWR_DN_RQ_OFFSET 0 87 #define PWRC_CPUN_CR_LDO_BYPASS_RDY_OFFSET 31 88 #endif 89 90 #define PWRC_CPUN_CR_REG(cpu_id) \ 91 (MVEBU_REGS_BASE + 0x680000 + (cpu_id * 0x10)) 92 #define PWRC_CPUN_CR_PWR_DN_RQ_MASK \ 93 (0x1 << PWRC_CPUN_CR_PWR_DN_RQ_OFFSET) 94 #define PWRC_CPUN_CR_ISO_ENABLE_OFFSET 16 95 #define PWRC_CPUN_CR_ISO_ENABLE_MASK \ 96 (0x1 << PWRC_CPUN_CR_ISO_ENABLE_OFFSET) 97 #define PWRC_CPUN_CR_LDO_BYPASS_RDY_MASK \ 98 (0x1U << PWRC_CPUN_CR_LDO_BYPASS_RDY_OFFSET) 99 100 #define CCU_B_PRCRN_REG(cpu_id) \ 101 (MVEBU_REGS_BASE + 0x1A50 + \ 102 ((cpu_id / 2) * (0x400)) + ((cpu_id % 2) * 4)) 103 #define CCU_B_PRCRN_CPUPORESET_STATIC_OFFSET 0 104 #define CCU_B_PRCRN_CPUPORESET_STATIC_MASK \ 105 (0x1 << CCU_B_PRCRN_CPUPORESET_STATIC_OFFSET) 106 107 /* power switch fingers */ 108 #define AP807_PWRC_LDO_CR0_REG \ 109 (MVEBU_REGS_BASE + 0x680000 + 0x100) 110 #define AP807_PWRC_LDO_CR0_OFFSET 16 111 #define AP807_PWRC_LDO_CR0_MASK \ 112 (0xff << AP807_PWRC_LDO_CR0_OFFSET) 113 #define AP807_PWRC_LDO_CR0_VAL 0xfc 114 115 /* 116 * Power down CPU: 117 * Used to reduce power consumption, and avoid SoC unnecessary temperature rise. 118 */ 119 static int plat_marvell_cpu_powerdown(int cpu_id) 120 { 121 uint32_t reg_val; 122 int exit_loop = REG_WR_VALIDATE_TIMEOUT; 123 124 INFO("Powering down CPU%d\n", cpu_id); 125 126 /* 1. Isolation enable */ 127 reg_val = mmio_read_32(PWRC_CPUN_CR_REG(cpu_id)); 128 reg_val |= 0x1 << PWRC_CPUN_CR_ISO_ENABLE_OFFSET; 129 mmio_write_32(PWRC_CPUN_CR_REG(cpu_id), reg_val); 130 131 /* 2. Read and check Isolation enabled - verify bit set to 1 */ 132 do { 133 reg_val = mmio_read_32(PWRC_CPUN_CR_REG(cpu_id)); 134 exit_loop--; 135 } while (!(reg_val & (0x1 << PWRC_CPUN_CR_ISO_ENABLE_OFFSET)) && 136 exit_loop > 0); 137 138 /* 3. Switch off CPU power */ 139 reg_val = mmio_read_32(PWRC_CPUN_CR_REG(cpu_id)); 140 reg_val &= ~PWRC_CPUN_CR_PWR_DN_RQ_MASK; 141 mmio_write_32(PWRC_CPUN_CR_REG(cpu_id), reg_val); 142 143 /* 4. Read and check Switch Off - verify bit set to 0 */ 144 exit_loop = REG_WR_VALIDATE_TIMEOUT; 145 do { 146 reg_val = mmio_read_32(PWRC_CPUN_CR_REG(cpu_id)); 147 exit_loop--; 148 } while (reg_val & PWRC_CPUN_CR_PWR_DN_RQ_MASK && exit_loop > 0); 149 150 if (exit_loop <= 0) 151 goto cpu_poweroff_error; 152 153 /* 5. De-Assert power ready */ 154 reg_val = mmio_read_32(PWRC_CPUN_CR_REG(cpu_id)); 155 reg_val &= ~PWRC_CPUN_CR_LDO_BYPASS_RDY_MASK; 156 mmio_write_32(PWRC_CPUN_CR_REG(cpu_id), reg_val); 157 158 /* 6. Assert CPU POR reset */ 159 reg_val = mmio_read_32(CCU_B_PRCRN_REG(cpu_id)); 160 reg_val &= ~CCU_B_PRCRN_CPUPORESET_STATIC_MASK; 161 mmio_write_32(CCU_B_PRCRN_REG(cpu_id), reg_val); 162 163 /* 7. Read and poll on Validate the CPU is out of reset */ 164 exit_loop = REG_WR_VALIDATE_TIMEOUT; 165 do { 166 reg_val = mmio_read_32(CCU_B_PRCRN_REG(cpu_id)); 167 exit_loop--; 168 } while (reg_val & CCU_B_PRCRN_CPUPORESET_STATIC_MASK && exit_loop > 0); 169 170 if (exit_loop <= 0) 171 goto cpu_poweroff_error; 172 173 INFO("Successfully powered down CPU%d\n", cpu_id); 174 175 return 0; 176 177 cpu_poweroff_error: 178 ERROR("ERROR: Can't power down CPU%d\n", cpu_id); 179 return -1; 180 } 181 182 /* 183 * Power down CPUs 1-3 at early boot stage, 184 * to reduce power consumption and SoC temperature. 185 * This is triggered by BLE prior to DDR initialization. 186 * 187 * Note: 188 * All CPUs will be powered up by plat_marvell_cpu_powerup on Linux boot stage, 189 * which is triggered by PSCI ops (pwr_domain_on). 190 */ 191 int plat_marvell_early_cpu_powerdown(void) 192 { 193 uint32_t cpu_cluster_status = 194 mmio_read_32(FEATURE_DISABLE_STATUS_REG) & 195 FEATURE_DISABLE_STATUS_CPU_CLUSTER_MASK; 196 /* if cpu_cluster_status bit is set, 197 * that means we have only single cluster 198 */ 199 int cluster_count = cpu_cluster_status ? 1 : 2; 200 201 INFO("Powering off unused CPUs\n"); 202 203 /* CPU1 is in AP806 cluster-0, which always exists, so power it down */ 204 if (plat_marvell_cpu_powerdown(CPU1) == -1) 205 return -1; 206 207 /* 208 * CPU2-3 are in AP806 2nd cluster (cluster-1), 209 * which doesn't exists in dual-core systems. 210 * so need to check if we have dual-core (single cluster) 211 * or quad-code (2 clusters) 212 */ 213 if (cluster_count == 2) { 214 /* CPU2-3 are part of 2nd cluster */ 215 if (plat_marvell_cpu_powerdown(CPU2) == -1) 216 return -1; 217 if (plat_marvell_cpu_powerdown(CPU3) == -1) 218 return -1; 219 } 220 221 return 0; 222 } 223 224 /* 225 * Power up CPU - part of Linux boot stage 226 */ 227 static int plat_marvell_cpu_powerup(u_register_t mpidr) 228 { 229 uint32_t reg_val; 230 int cpu_id = MPIDR_CPU_GET(mpidr), 231 cluster = MPIDR_CLUSTER_GET(mpidr); 232 int exit_loop = REG_WR_VALIDATE_TIMEOUT; 233 234 /* calculate absolute CPU ID */ 235 cpu_id = cluster * PLAT_MARVELL_CLUSTER_CORE_COUNT + cpu_id; 236 237 INFO("Powering on CPU%d\n", cpu_id); 238 239 #ifdef MVEBU_SOC_AP807 240 /* Activate 2 power switch fingers */ 241 reg_val = mmio_read_32(AP807_PWRC_LDO_CR0_REG); 242 reg_val &= ~(AP807_PWRC_LDO_CR0_MASK); 243 reg_val |= (AP807_PWRC_LDO_CR0_VAL << AP807_PWRC_LDO_CR0_OFFSET); 244 mmio_write_32(AP807_PWRC_LDO_CR0_REG, reg_val); 245 udelay(100); 246 #endif 247 248 /* 1. Switch CPU power ON */ 249 reg_val = mmio_read_32(PWRC_CPUN_CR_REG(cpu_id)); 250 reg_val |= 0x1 << PWRC_CPUN_CR_PWR_DN_RQ_OFFSET; 251 mmio_write_32(PWRC_CPUN_CR_REG(cpu_id), reg_val); 252 253 /* 2. Wait for CPU on, up to 100 uSec: */ 254 udelay(100); 255 256 /* 3. Assert power ready */ 257 reg_val = mmio_read_32(PWRC_CPUN_CR_REG(cpu_id)); 258 reg_val |= 0x1U << PWRC_CPUN_CR_LDO_BYPASS_RDY_OFFSET; 259 mmio_write_32(PWRC_CPUN_CR_REG(cpu_id), reg_val); 260 261 /* 4. Read & Validate power ready 262 * used in order to generate 16 Host CPU cycles 263 */ 264 do { 265 reg_val = mmio_read_32(PWRC_CPUN_CR_REG(cpu_id)); 266 exit_loop--; 267 } while (!(reg_val & (0x1U << PWRC_CPUN_CR_LDO_BYPASS_RDY_OFFSET)) && 268 exit_loop > 0); 269 270 if (exit_loop <= 0) 271 goto cpu_poweron_error; 272 273 /* 5. Isolation disable */ 274 reg_val = mmio_read_32(PWRC_CPUN_CR_REG(cpu_id)); 275 reg_val &= ~PWRC_CPUN_CR_ISO_ENABLE_MASK; 276 mmio_write_32(PWRC_CPUN_CR_REG(cpu_id), reg_val); 277 278 /* 6. Read and check Isolation enabled - verify bit set to 1 */ 279 exit_loop = REG_WR_VALIDATE_TIMEOUT; 280 do { 281 reg_val = mmio_read_32(PWRC_CPUN_CR_REG(cpu_id)); 282 exit_loop--; 283 } while ((reg_val & (0x1 << PWRC_CPUN_CR_ISO_ENABLE_OFFSET)) && 284 exit_loop > 0); 285 286 /* 7. De Assert CPU POR reset & Core reset */ 287 reg_val = mmio_read_32(CCU_B_PRCRN_REG(cpu_id)); 288 reg_val |= 0x1 << CCU_B_PRCRN_CPUPORESET_STATIC_OFFSET; 289 mmio_write_32(CCU_B_PRCRN_REG(cpu_id), reg_val); 290 291 /* 8. Read & Validate CPU POR reset */ 292 exit_loop = REG_WR_VALIDATE_TIMEOUT; 293 do { 294 reg_val = mmio_read_32(CCU_B_PRCRN_REG(cpu_id)); 295 exit_loop--; 296 } while (!(reg_val & (0x1 << CCU_B_PRCRN_CPUPORESET_STATIC_OFFSET)) && 297 exit_loop > 0); 298 299 if (exit_loop <= 0) 300 goto cpu_poweron_error; 301 302 INFO("Successfully powered on CPU%d\n", cpu_id); 303 304 return 0; 305 306 cpu_poweron_error: 307 ERROR("ERROR: Can't power up CPU%d\n", cpu_id); 308 return -1; 309 } 310 311 static int plat_marvell_cpu_on(u_register_t mpidr) 312 { 313 int cpu_id; 314 int cluster; 315 316 /* Set barierr */ 317 dsbsy(); 318 319 /* Get cpu number - use CPU ID */ 320 cpu_id = MPIDR_CPU_GET(mpidr); 321 322 /* Get cluster number - use affinity level 1 */ 323 cluster = MPIDR_CLUSTER_GET(mpidr); 324 325 /* Set CPU private UID */ 326 mmio_write_32(MVEBU_REGS_BASE + MVEBU_PRIVATE_UID_REG, cluster + 0x4); 327 328 /* Set the cpu start address to BL1 entry point (align to 0x10000) */ 329 mmio_write_32(MVEBU_CCU_RVBAR(cpu_id), 330 PLAT_MARVELL_CPU_ENTRY_ADDR >> 16); 331 332 /* Get the cpu out of reset */ 333 mmio_write_32(MVEBU_CCU_CPU_UN_RESET(cpu_id), 0x10001); 334 335 return 0; 336 } 337 338 /***************************************************************************** 339 * A8K handler called to check the validity of the power state 340 * parameter. 341 ***************************************************************************** 342 */ 343 static int a8k_validate_power_state(unsigned int power_state, 344 psci_power_state_t *req_state) 345 { 346 int pstate = psci_get_pstate_type(power_state); 347 int pwr_lvl = psci_get_pstate_pwrlvl(power_state); 348 int i; 349 350 if (pwr_lvl > PLAT_MAX_PWR_LVL) 351 return PSCI_E_INVALID_PARAMS; 352 353 /* Sanity check the requested state */ 354 if (pstate == PSTATE_TYPE_STANDBY) { 355 /* 356 * It's possible to enter standby only on power level 0 357 * Ignore any other power level. 358 */ 359 if (pwr_lvl != MARVELL_PWR_LVL0) 360 return PSCI_E_INVALID_PARAMS; 361 362 req_state->pwr_domain_state[MARVELL_PWR_LVL0] = 363 MARVELL_LOCAL_STATE_RET; 364 } else { 365 for (i = MARVELL_PWR_LVL0; i <= pwr_lvl; i++) 366 req_state->pwr_domain_state[i] = 367 MARVELL_LOCAL_STATE_OFF; 368 } 369 370 /* 371 * We expect the 'state id' to be zero. 372 */ 373 if (psci_get_pstate_id(power_state)) 374 return PSCI_E_INVALID_PARAMS; 375 376 return PSCI_E_SUCCESS; 377 } 378 379 /***************************************************************************** 380 * A8K handler called when a CPU is about to enter standby. 381 ***************************************************************************** 382 */ 383 static void a8k_cpu_standby(plat_local_state_t cpu_state) 384 { 385 if (!is_pm_fw_running()) { 386 ERROR("%s: needs to be implemented\n", __func__); 387 panic(); 388 } 389 } 390 391 /***************************************************************************** 392 * A8K handler called when a power domain is about to be turned on. The 393 * mpidr determines the CPU to be turned on. 394 ***************************************************************************** 395 */ 396 static int a8k_pwr_domain_on(u_register_t mpidr) 397 { 398 /* Power up CPU (CPUs 1-3 are powered off at start of BLE) */ 399 plat_marvell_cpu_powerup(mpidr); 400 401 #if MSS_SUPPORT 402 if (is_pm_fw_running()) { 403 unsigned int target = 404 ((mpidr & 0xFF) + (((mpidr >> 8) & 0xFF) * 2)); 405 406 /* 407 * pm system synchronization - used to synchronize 408 * multiple core access to MSS 409 */ 410 bakery_lock_get(&pm_sys_lock); 411 412 /* send CPU ON IPC Message to MSS */ 413 mss_pm_ipc_msg_send(target, PM_IPC_MSG_CPU_ON, 0); 414 415 /* trigger IPC message to MSS */ 416 mss_pm_ipc_msg_trigger(); 417 418 /* pm system synchronization */ 419 bakery_lock_release(&pm_sys_lock); 420 421 /* trace message */ 422 PM_TRACE(TRACE_PWR_DOMAIN_ON | target); 423 } else 424 #endif 425 { 426 /* proprietary CPU ON execution flow */ 427 plat_marvell_cpu_on(mpidr); 428 } 429 return 0; 430 } 431 432 /***************************************************************************** 433 * A8K handler called to validate the entry point. 434 ***************************************************************************** 435 */ 436 static int a8k_validate_ns_entrypoint(uintptr_t entrypoint) 437 { 438 return PSCI_E_SUCCESS; 439 } 440 441 /***************************************************************************** 442 * A8K handler called when a power domain is about to be turned off. The 443 * target_state encodes the power state that each level should transition to. 444 ***************************************************************************** 445 */ 446 static void a8k_pwr_domain_off(const psci_power_state_t *target_state) 447 { 448 #if MSS_SUPPORT 449 if (is_pm_fw_running()) { 450 unsigned int idx = plat_my_core_pos(); 451 452 /* Prevent interrupts from spuriously waking up this cpu */ 453 gicv2_cpuif_disable(); 454 455 /* pm system synchronization - used to synchronize multiple 456 * core access to MSS 457 */ 458 bakery_lock_get(&pm_sys_lock); 459 460 /* send CPU OFF IPC Message to MSS */ 461 mss_pm_ipc_msg_send(idx, PM_IPC_MSG_CPU_OFF, target_state); 462 463 /* trigger IPC message to MSS */ 464 mss_pm_ipc_msg_trigger(); 465 466 /* pm system synchronization */ 467 bakery_lock_release(&pm_sys_lock); 468 469 /* trace message */ 470 PM_TRACE(TRACE_PWR_DOMAIN_OFF); 471 } else { 472 INFO("%s: is not supported without SCP\n", __func__); 473 } 474 #endif 475 } 476 477 /* Get PM config to power off the SoC */ 478 void *plat_marvell_get_pm_cfg(void) 479 { 480 return NULL; 481 } 482 483 /* 484 * This function should be called on restore from 485 * "suspend to RAM" state when the execution flow 486 * has to bypass BootROM image to RAM copy and speed up 487 * the system recovery 488 * 489 */ 490 static void plat_marvell_exit_bootrom(void) 491 { 492 marvell_exit_bootrom(PLAT_MARVELL_TRUSTED_ROM_BASE); 493 } 494 495 /* 496 * Prepare for the power off of the system via GPIO 497 */ 498 static void plat_marvell_power_off_gpio(struct power_off_method *pm_cfg, 499 register_t *gpio_addr, 500 register_t *gpio_data) 501 { 502 unsigned int gpio; 503 unsigned int idx; 504 unsigned int shift; 505 unsigned int reg; 506 unsigned int addr; 507 gpio_info_t *info; 508 unsigned int tog_bits; 509 510 assert((pm_cfg->cfg.gpio.pin_count < PMIC_GPIO_MAX_NUMBER) && 511 (pm_cfg->cfg.gpio.step_count < PMIC_GPIO_MAX_TOGGLE_STEP)); 512 513 /* Prepare GPIOs for PMIC */ 514 for (gpio = 0; gpio < pm_cfg->cfg.gpio.pin_count; gpio++) { 515 info = &pm_cfg->cfg.gpio.info[gpio]; 516 /* Set PMIC GPIO to output mode */ 517 reg = mmio_read_32(MVEBU_CP_GPIO_DATA_OUT_EN( 518 info->cp_index, info->gpio_index)); 519 mmio_write_32(MVEBU_CP_GPIO_DATA_OUT_EN( 520 info->cp_index, info->gpio_index), 521 reg & ~MVEBU_GPIO_MASK(info->gpio_index)); 522 523 /* Set the appropriate MPP to GPIO mode */ 524 reg = mmio_read_32(MVEBU_PM_MPP_REGS(info->cp_index, 525 info->gpio_index)); 526 mmio_write_32(MVEBU_PM_MPP_REGS(info->cp_index, 527 info->gpio_index), 528 reg & ~MVEBU_MPP_MASK(info->gpio_index)); 529 } 530 531 /* Wait for MPP & GPIO pre-configurations done */ 532 mdelay(pm_cfg->cfg.gpio.delay_ms); 533 534 /* Toggle the GPIO values, and leave final step to be triggered 535 * after DDR self-refresh is enabled 536 */ 537 for (idx = 0; idx < pm_cfg->cfg.gpio.step_count; idx++) { 538 tog_bits = pm_cfg->cfg.gpio.seq[idx]; 539 540 /* The GPIOs must be within same GPIO register, 541 * thus could get the original value by first GPIO 542 */ 543 info = &pm_cfg->cfg.gpio.info[0]; 544 reg = mmio_read_32(MVEBU_CP_GPIO_DATA_OUT( 545 info->cp_index, info->gpio_index)); 546 addr = MVEBU_CP_GPIO_DATA_OUT(info->cp_index, info->gpio_index); 547 548 for (gpio = 0; gpio < pm_cfg->cfg.gpio.pin_count; gpio++) { 549 shift = pm_cfg->cfg.gpio.info[gpio].gpio_index % 32; 550 if (GPIO_LOW == (tog_bits & (1 << gpio))) 551 reg &= ~(1 << shift); 552 else 553 reg |= (1 << shift); 554 } 555 556 /* Set the GPIO register, for last step just store 557 * register address and values to system registers 558 */ 559 if (idx < pm_cfg->cfg.gpio.step_count - 1) { 560 mmio_write_32(MVEBU_CP_GPIO_DATA_OUT( 561 info->cp_index, info->gpio_index), reg); 562 mdelay(pm_cfg->cfg.gpio.delay_ms); 563 } else { 564 /* Save GPIO register and address values for 565 * finishing the power down operation later 566 */ 567 *gpio_addr = addr; 568 *gpio_data = reg; 569 } 570 } 571 } 572 573 /* 574 * Prepare for the power off of the system 575 */ 576 static void plat_marvell_power_off_prepare(struct power_off_method *pm_cfg, 577 register_t *addr, register_t *data) 578 { 579 switch (pm_cfg->type) { 580 case PMIC_GPIO: 581 plat_marvell_power_off_gpio(pm_cfg, addr, data); 582 break; 583 default: 584 break; 585 } 586 } 587 588 /***************************************************************************** 589 * A8K handler called when a power domain is about to be suspended. The 590 * target_state encodes the power state that each level should transition to. 591 ***************************************************************************** 592 */ 593 static void a8k_pwr_domain_suspend(const psci_power_state_t *target_state) 594 { 595 #if MSS_SUPPORT 596 if (is_pm_fw_running()) { 597 unsigned int idx; 598 599 /* Prevent interrupts from spuriously waking up this cpu */ 600 gicv2_cpuif_disable(); 601 602 idx = plat_my_core_pos(); 603 604 /* pm system synchronization - used to synchronize multiple 605 * core access to MSS 606 */ 607 bakery_lock_get(&pm_sys_lock); 608 609 /* send CPU Suspend IPC Message to MSS */ 610 mss_pm_ipc_msg_send(idx, PM_IPC_MSG_CPU_SUSPEND, target_state); 611 612 /* trigger IPC message to MSS */ 613 mss_pm_ipc_msg_trigger(); 614 615 /* pm system synchronization */ 616 bakery_lock_release(&pm_sys_lock); 617 618 /* trace message */ 619 PM_TRACE(TRACE_PWR_DOMAIN_SUSPEND); 620 } else 621 #endif 622 { 623 uintptr_t *mailbox = (void *)PLAT_MARVELL_MAILBOX_BASE; 624 625 INFO("Suspending to RAM\n"); 626 627 marvell_console_runtime_end(); 628 629 /* Prevent interrupts from spuriously waking up this cpu */ 630 gicv2_cpuif_disable(); 631 632 mailbox[MBOX_IDX_SUSPEND_MAGIC] = MVEBU_MAILBOX_SUSPEND_STATE; 633 mailbox[MBOX_IDX_ROM_EXIT_ADDR] = (uintptr_t)&plat_marvell_exit_bootrom; 634 635 #if PLAT_MARVELL_SHARED_RAM_CACHED 636 flush_dcache_range(PLAT_MARVELL_MAILBOX_BASE + 637 MBOX_IDX_SUSPEND_MAGIC * sizeof(uintptr_t), 638 2 * sizeof(uintptr_t)); 639 #endif 640 /* Flush and disable LLC before going off-power */ 641 llc_disable(0); 642 643 isb(); 644 /* 645 * Do not halt here! 646 * The function must return for allowing the caller function 647 * psci_power_up_finish() to do the proper context saving and 648 * to release the CPU lock. 649 */ 650 } 651 } 652 653 /***************************************************************************** 654 * A8K handler called when a power domain has just been powered on after 655 * being turned off earlier. The target_state encodes the low power state that 656 * each level has woken up from. 657 ***************************************************************************** 658 */ 659 static void a8k_pwr_domain_on_finish(const psci_power_state_t *target_state) 660 { 661 /* arch specific configuration */ 662 marvell_psci_arch_init(0); 663 664 /* Interrupt initialization */ 665 gicv2_pcpu_distif_init(); 666 gicv2_cpuif_enable(); 667 668 if (is_pm_fw_running()) { 669 /* trace message */ 670 PM_TRACE(TRACE_PWR_DOMAIN_ON_FINISH); 671 } 672 } 673 674 /***************************************************************************** 675 * A8K handler called when a power domain has just been powered on after 676 * having been suspended earlier. The target_state encodes the low power state 677 * that each level has woken up from. 678 * TODO: At the moment we reuse the on finisher and reinitialize the secure 679 * context. Need to implement a separate suspend finisher. 680 ***************************************************************************** 681 */ 682 static void a8k_pwr_domain_suspend_finish( 683 const psci_power_state_t *target_state) 684 { 685 if (is_pm_fw_running()) { 686 /* arch specific configuration */ 687 marvell_psci_arch_init(0); 688 689 /* Interrupt initialization */ 690 gicv2_cpuif_enable(); 691 692 /* trace message */ 693 PM_TRACE(TRACE_PWR_DOMAIN_SUSPEND_FINISH); 694 } else { 695 uintptr_t *mailbox = (void *)PLAT_MARVELL_MAILBOX_BASE; 696 697 /* Only primary CPU requres platform init */ 698 if (!plat_my_core_pos()) { 699 /* Initialize the console to provide 700 * early debug support 701 */ 702 marvell_console_runtime_init(); 703 704 bl31_plat_arch_setup(); 705 marvell_bl31_platform_setup(); 706 /* 707 * Remove suspend to RAM marker from the mailbox 708 * for treating a regular reset as a cold boot 709 */ 710 mailbox[MBOX_IDX_SUSPEND_MAGIC] = 0; 711 mailbox[MBOX_IDX_ROM_EXIT_ADDR] = 0; 712 #if PLAT_MARVELL_SHARED_RAM_CACHED 713 flush_dcache_range(PLAT_MARVELL_MAILBOX_BASE + 714 MBOX_IDX_SUSPEND_MAGIC * sizeof(uintptr_t), 715 2 * sizeof(uintptr_t)); 716 #endif 717 } 718 } 719 } 720 721 /***************************************************************************** 722 * This handler is called by the PSCI implementation during the `SYSTEM_SUSPEND` 723 * call to get the `power_state` parameter. This allows the platform to encode 724 * the appropriate State-ID field within the `power_state` parameter which can 725 * be utilized in `pwr_domain_suspend()` to suspend to system affinity level. 726 ***************************************************************************** 727 */ 728 static void a8k_get_sys_suspend_power_state(psci_power_state_t *req_state) 729 { 730 /* lower affinities use PLAT_MAX_OFF_STATE */ 731 for (int i = MPIDR_AFFLVL0; i <= PLAT_MAX_PWR_LVL; i++) 732 req_state->pwr_domain_state[i] = PLAT_MAX_OFF_STATE; 733 } 734 735 static void 736 __dead2 a8k_pwr_domain_pwr_down_wfi(const psci_power_state_t *target_state) 737 { 738 struct power_off_method *pm_cfg; 739 unsigned int srcmd; 740 unsigned int sdram_reg; 741 register_t gpio_data = 0, gpio_addr = 0; 742 743 if (is_pm_fw_running()) { 744 psci_power_down_wfi(); 745 panic(); 746 } 747 748 pm_cfg = (struct power_off_method *)plat_marvell_get_pm_cfg(); 749 750 /* Prepare for power off */ 751 plat_marvell_power_off_prepare(pm_cfg, &gpio_addr, &gpio_data); 752 753 /* First step to enable DDR self-refresh 754 * to keep the data during suspend 755 */ 756 mmio_write_32(MVEBU_MC_PWR_CTRL_REG, 0x8C1); 757 758 /* Save DDR self-refresh second step register 759 * and value to be issued later 760 */ 761 sdram_reg = MVEBU_USER_CMD_0_REG; 762 srcmd = mmio_read_32(sdram_reg); 763 srcmd &= ~(MVEBU_USER_CMD_CH0_MASK | MVEBU_USER_CMD_CS_MASK | 764 MVEBU_USER_CMD_SR_MASK); 765 srcmd |= (MVEBU_USER_CMD_CH0_EN | MVEBU_USER_CMD_CS_ALL | 766 MVEBU_USER_CMD_SR_ENTER); 767 768 /* 769 * Wait for DRAM is done using registers access only. 770 * At this stage any access to DRAM (procedure call) will 771 * release it from the self-refresh mode 772 */ 773 __asm__ volatile ( 774 /* Align to a cache line */ 775 " .balign 64\n\t" 776 777 /* Enter self refresh */ 778 " str %[srcmd], [%[sdram_reg]]\n\t" 779 780 /* 781 * Wait 100 cycles for DDR to enter self refresh, by 782 * doing 50 times two instructions. 783 */ 784 " mov x1, #50\n\t" 785 "1: subs x1, x1, #1\n\t" 786 " bne 1b\n\t" 787 788 /* Issue the command to trigger the SoC power off */ 789 " str %[gpio_data], [%[gpio_addr]]\n\t" 790 791 /* Trap the processor */ 792 " b .\n\t" 793 : : [srcmd] "r" (srcmd), [sdram_reg] "r" (sdram_reg), 794 [gpio_addr] "r" (gpio_addr), [gpio_data] "r" (gpio_data) 795 : "x1"); 796 797 panic(); 798 } 799 800 /***************************************************************************** 801 * A8K handlers to shutdown/reboot the system 802 ***************************************************************************** 803 */ 804 805 /* Set a weak stub for platforms that don't configure system power off */ 806 #pragma weak system_power_off 807 int system_power_off(void) 808 { 809 return 0; 810 } 811 812 static void __dead2 a8k_system_off(void) 813 { 814 /* Call the platform specific system power off function */ 815 system_power_off(); 816 817 /* board doesn't have a system off implementation */ 818 ERROR("%s: needs to be implemented\n", __func__); 819 panic(); 820 } 821 822 void plat_marvell_system_reset(void) 823 { 824 mmio_write_32(MVEBU_RFU_BASE + MVEBU_RFU_GLOBL_SW_RST, 0x0); 825 } 826 827 static void __dead2 a8k_system_reset(void) 828 { 829 plat_marvell_system_reset(); 830 831 /* we shouldn't get to this point */ 832 panic(); 833 } 834 835 /***************************************************************************** 836 * Export the platform handlers via plat_arm_psci_pm_ops. The ARM Standard 837 * platform layer will take care of registering the handlers with PSCI. 838 ***************************************************************************** 839 */ 840 const plat_psci_ops_t plat_arm_psci_pm_ops = { 841 .cpu_standby = a8k_cpu_standby, 842 .pwr_domain_on = a8k_pwr_domain_on, 843 .pwr_domain_off = a8k_pwr_domain_off, 844 .pwr_domain_suspend = a8k_pwr_domain_suspend, 845 .pwr_domain_on_finish = a8k_pwr_domain_on_finish, 846 .get_sys_suspend_power_state = a8k_get_sys_suspend_power_state, 847 .pwr_domain_suspend_finish = a8k_pwr_domain_suspend_finish, 848 .pwr_domain_pwr_down = a8k_pwr_domain_pwr_down_wfi, 849 .system_off = a8k_system_off, 850 .system_reset = a8k_system_reset, 851 .validate_power_state = a8k_validate_power_state, 852 .validate_ns_entrypoint = a8k_validate_ns_entrypoint 853 }; 854