1/* 2 * Copyright (c) 2021-2025, Arm Limited. All rights reserved. 3 * 4 * SPDX-License-Identifier: BSD-3-Clause 5 */ 6 7#include <arch.h> 8#include <asm_macros.S> 9#include <common/bl_common.h> 10#include <cortex_x2.h> 11#include <cpu_macros.S> 12#include <dsu_macros.S> 13#include <plat_macros.S> 14#include "wa_cve_2022_23960_bhb_vector.S" 15 16/* Hardware handled coherency */ 17#if HW_ASSISTED_COHERENCY == 0 18#error "Cortex X2 must be compiled with HW_ASSISTED_COHERENCY enabled" 19#endif 20 21/* 64-bit only core */ 22#if CTX_INCLUDE_AARCH32_REGS == 1 23#error "Cortex X2 supports only AArch64. Compile with CTX_INCLUDE_AARCH32_REGS=0" 24#endif 25 26.global check_erratum_cortex_x2_3701772 27 28add_erratum_entry cortex_x2, ERRATUM(3701772), ERRATA_X2_3701772, NO_APPLY_AT_RESET 29 30check_erratum_ls cortex_x2, ERRATUM(3701772), CPU_REV(2, 1) 31 32#if WORKAROUND_CVE_2022_23960 33 wa_cve_2022_23960_bhb_vector_table CORTEX_X2_BHB_LOOP_COUNT, cortex_x2 34#endif /* WORKAROUND_CVE_2022_23960 */ 35 36/* Disable hardware page aggregation. Enables mitigation for `CVE-2024-5660` */ 37workaround_reset_start cortex_x2, CVE(2024, 5660), WORKAROUND_CVE_2024_5660 38 sysreg_bit_set CORTEX_X2_CPUECTLR_EL1, BIT(46) 39workaround_reset_end cortex_x2, CVE(2024, 5660) 40 41check_erratum_ls cortex_x2, CVE(2024, 5660), CPU_REV(2, 1) 42 43workaround_reset_start cortex_x2, ERRATUM(2002765), ERRATA_X2_2002765 44 ldr x0, =0x6 45 msr S3_6_C15_C8_0, x0 /* CPUPSELR_EL3 */ 46 ldr x0, =0xF3A08002 47 msr S3_6_C15_C8_2, x0 /* CPUPOR_EL3 */ 48 ldr x0, =0xFFF0F7FE 49 msr S3_6_C15_C8_3, x0 /* CPUPMR_EL3 */ 50 ldr x0, =0x40000001003ff 51 msr S3_6_C15_C8_1, x0 /* CPUPCR_EL3 */ 52workaround_reset_end cortex_x2, ERRATUM(2002765) 53 54check_erratum_ls cortex_x2, ERRATUM(2002765), CPU_REV(2, 0) 55 56workaround_reset_start cortex_x2, ERRATUM(2017096), ERRATA_X2_2017096 57 sysreg_bit_set CORTEX_X2_CPUECTLR_EL1, CORTEX_X2_CPUECTLR_EL1_PFSTIDIS_BIT 58workaround_reset_end cortex_x2, ERRATUM(2017096) 59 60check_erratum_ls cortex_x2, ERRATUM(2017096), CPU_REV(2, 0) 61 62workaround_reset_start cortex_x2, ERRATUM(2058056), ERRATA_X2_2058056 63 sysreg_bitfield_insert CORTEX_X2_CPUECTLR2_EL1, CORTEX_X2_CPUECTLR2_EL1_PF_MODE_CNSRV, \ 64 CORTEX_X2_CPUECTLR2_EL1_PF_MODE_SHIFT, CORTEX_X2_CPUECTLR2_EL1_PF_MODE_WIDTH 65workaround_reset_end cortex_x2, ERRATUM(2058056) 66 67check_erratum_ls cortex_x2, ERRATUM(2058056), CPU_REV(2, 1) 68 69workaround_reset_start cortex_x2, ERRATUM(2081180), ERRATA_X2_2081180 70 /* Apply instruction patching sequence */ 71 ldr x0, =0x3 72 msr CORTEX_X2_IMP_CPUPSELR_EL3, x0 73 ldr x0, =0xF3A08002 74 msr CORTEX_X2_IMP_CPUPOR_EL3, x0 75 ldr x0, =0xFFF0F7FE 76 msr CORTEX_X2_IMP_CPUPMR_EL3, x0 77 ldr x0, =0x10002001003FF 78 msr CORTEX_X2_IMP_CPUPCR_EL3, x0 79 ldr x0, =0x4 80 msr CORTEX_X2_IMP_CPUPSELR_EL3, x0 81 ldr x0, =0xBF200000 82 msr CORTEX_X2_IMP_CPUPOR_EL3, x0 83 ldr x0, =0xFFEF0000 84 msr CORTEX_X2_IMP_CPUPMR_EL3, x0 85 ldr x0, =0x10002001003F3 86 msr CORTEX_X2_IMP_CPUPCR_EL3, x0 87workaround_reset_end cortex_x2, ERRATUM(2081180) 88 89check_erratum_ls cortex_x2, ERRATUM(2081180), CPU_REV(2, 0) 90 91workaround_reset_start cortex_x2, ERRATUM(2083908), ERRATA_X2_2083908 92 /* Apply the workaround by setting bit 13 in CPUACTLR5_EL1. */ 93 sysreg_bit_set CORTEX_X2_CPUACTLR5_EL1, BIT(13) 94workaround_reset_end cortex_x2, ERRATUM(2083908) 95 96check_erratum_range cortex_x2, ERRATUM(2083908), CPU_REV(2, 0), CPU_REV(2, 0) 97 98workaround_reset_start cortex_x2, ERRATUM(2147715), ERRATA_X2_2147715 99 /* Apply the workaround by setting bit 22 in CPUACTLR_EL1. */ 100 sysreg_bit_set CORTEX_X2_CPUACTLR_EL1, CORTEX_X2_CPUACTLR_EL1_BIT_22 101workaround_reset_end cortex_x2, ERRATUM(2147715) 102 103check_erratum_range cortex_x2, ERRATUM(2147715), CPU_REV(2, 0), CPU_REV(2, 0) 104 105workaround_reset_start cortex_x2, ERRATUM(2216384), ERRATA_X2_2216384 106 sysreg_bit_set CORTEX_X2_CPUACTLR5_EL1, CORTEX_X2_CPUACTLR5_EL1_BIT_17 107 108 /* Apply instruction patching sequence */ 109 ldr x0, =0x5 110 msr CORTEX_X2_IMP_CPUPSELR_EL3, x0 111 ldr x0, =0x10F600E000 112 msr CORTEX_X2_IMP_CPUPOR_EL3, x0 113 ldr x0, =0x10FF80E000 114 msr CORTEX_X2_IMP_CPUPMR_EL3, x0 115 ldr x0, =0x80000000003FF 116 msr CORTEX_X2_IMP_CPUPCR_EL3, x0 117workaround_reset_end cortex_x2, ERRATUM(2216384) 118 119check_erratum_ls cortex_x2, ERRATUM(2216384), CPU_REV(2, 0) 120 121workaround_reset_start cortex_x2, ERRATUM(2282622), ERRATA_X2_2282622 122 /* Apply the workaround */ 123 sysreg_bit_set CORTEX_X2_CPUACTLR2_EL1, BIT(0) 124workaround_reset_end cortex_x2, ERRATUM(2282622) 125 126check_erratum_ls cortex_x2, ERRATUM(2282622), CPU_REV(2, 1) 127 128workaround_reset_start cortex_x2, ERRATUM(2371105), ERRATA_X2_2371105 129 /* Set bit 40 in CPUACTLR2_EL1 */ 130 sysreg_bit_set CORTEX_X2_CPUACTLR2_EL1, CORTEX_X2_CPUACTLR2_EL1_BIT_40 131workaround_reset_end cortex_x2, ERRATUM(2371105) 132 133check_erratum_ls cortex_x2, ERRATUM(2371105), CPU_REV(2, 0) 134 135workaround_reset_start cortex_x2, ERRATUM(2742423), ERRATA_X2_2742423 136 /* Set CPUACTLR5_EL1[56:55] to 2'b01 */ 137 sysreg_bit_set CORTEX_X2_CPUACTLR5_EL1, BIT(55) 138 sysreg_bit_clear CORTEX_X2_CPUACTLR5_EL1, BIT(56) 139workaround_reset_end cortex_x2, ERRATUM(2742423) 140 141check_erratum_ls cortex_x2, ERRATUM(2742423), CPU_REV(2, 1) 142 143workaround_runtime_start cortex_x2, ERRATUM(2768515), ERRATA_X2_2768515 144 /* dsb before isb of power down sequence */ 145 dsb sy 146workaround_runtime_end cortex_x2, ERRATUM(2768515) 147 148check_erratum_ls cortex_x2, ERRATUM(2768515), CPU_REV(2, 1) 149 150workaround_reset_start cortex_x2, ERRATUM(2778471), ERRATA_X2_2778471 151 sysreg_bit_set CORTEX_X2_CPUACTLR3_EL1, BIT(47) 152workaround_reset_end cortex_x2, ERRATUM(2778471) 153 154check_erratum_ls cortex_x2, ERRATUM(2778471), CPU_REV(2, 1) 155 156workaround_reset_start cortex_x2, CVE(2022, 23960), WORKAROUND_CVE_2022_23960 157#if IMAGE_BL31 158 /* 159 * The Cortex-X2 generic vectors are overridden to apply errata 160 * mitigation on exception entry from lower ELs. 161 */ 162 override_vector_table wa_cve_vbar_cortex_x2 163#endif /* IMAGE_BL31 */ 164workaround_reset_end cortex_x2, CVE(2022, 23960) 165 166check_erratum_chosen cortex_x2, CVE(2022, 23960), WORKAROUND_CVE_2022_23960 167 168workaround_reset_start cortex_x2, ERRATUM(2313941), ERRATA_DSU_2313941 169 errata_dsu_2313941_wa_impl 170workaround_reset_end cortex_x2, ERRATUM(2313941) 171 172check_erratum_custom_start cortex_x2, ERRATUM(2313941) 173 check_errata_dsu_2313941_impl 174 ret 175check_erratum_custom_end cortex_x2, ERRATUM(2313941) 176 177 /* ---------------------------------------------------- 178 * HW will do the cache maintenance while powering down 179 * ---------------------------------------------------- 180 */ 181func cortex_x2_core_pwr_dwn 182 /* --------------------------------------------------- 183 * Enable CPU power down bit in power control register 184 * --------------------------------------------------- 185 */ 186 sysreg_bit_set CORTEX_X2_CPUPWRCTLR_EL1, CORTEX_X2_CPUPWRCTLR_EL1_CORE_PWRDN_BIT 187 188 apply_erratum cortex_x2, ERRATUM(2768515), ERRATA_X2_2768515, NO_GET_CPU_REV 189 isb 190 ret 191endfunc cortex_x2_core_pwr_dwn 192 193cpu_reset_func_start cortex_x2 194 /* Disable speculative loads */ 195 msr SSBS, xzr 196cpu_reset_func_end cortex_x2 197 198 /* --------------------------------------------- 199 * This function provides Cortex X2 specific 200 * register information for crash reporting. 201 * It needs to return with x6 pointing to 202 * a list of register names in ascii and 203 * x8 - x15 having values of registers to be 204 * reported. 205 * --------------------------------------------- 206 */ 207.section .rodata.cortex_x2_regs, "aS" 208cortex_x2_regs: /* The ascii list of register names to be reported */ 209 .asciz "cpuectlr_el1", "" 210 211func cortex_x2_cpu_reg_dump 212 adr x6, cortex_x2_regs 213 mrs x8, CORTEX_X2_CPUECTLR_EL1 214 ret 215endfunc cortex_x2_cpu_reg_dump 216 217declare_cpu_ops cortex_x2, CORTEX_X2_MIDR, \ 218 cortex_x2_reset_func, \ 219 cortex_x2_core_pwr_dwn 220