1 /* 2 * Copyright (c) 2022, Xilinx, Inc. All rights reserved. 3 * Copyright (c) 2022-2024, Advanced Micro Devices, Inc. All rights reserved. 4 * 5 * SPDX-License-Identifier: BSD-3-Clause 6 */ 7 8 #include <assert.h> 9 10 #include <common/debug.h> 11 #include <lib/mmio.h> 12 #include <lib/psci/psci.h> 13 #include <plat/arm/common/plat_arm.h> 14 #include <plat/common/platform.h> 15 #include <plat_arm.h> 16 17 #include <drivers/delay_timer.h> 18 #include <plat_private.h> 19 #include "pm_api_sys.h" 20 #include "pm_client.h" 21 #include <pm_common.h> 22 #include "pm_ipi.h" 23 #include "pm_svc_main.h" 24 #include "versal_net_def.h" 25 26 static uintptr_t versal_net_sec_entry; 27 28 static int32_t versal_net_pwr_domain_on(u_register_t mpidr) 29 { 30 int32_t cpu_id = plat_core_pos_by_mpidr(mpidr); 31 const struct pm_proc *proc; 32 int32_t ret = PSCI_E_INTERN_FAIL; 33 34 VERBOSE("%s: mpidr: 0x%lx, cpuid: %x\n", 35 __func__, mpidr, cpu_id); 36 37 if (cpu_id == -1) { 38 goto exit_label; 39 } 40 41 proc = pm_get_proc(cpu_id); 42 if (proc == NULL) { 43 goto exit_label; 44 } 45 46 (void)pm_req_wakeup(proc->node_id, (versal_net_sec_entry & 0xFFFFFFFFU) | 0x1U, 47 versal_net_sec_entry >> 32, 0, 0); 48 49 /* Clear power down request */ 50 pm_client_wakeup(proc); 51 52 ret = PSCI_E_SUCCESS; 53 54 exit_label: 55 return ret; 56 } 57 58 /** 59 * versal_net_pwr_domain_off() - This function performs actions to turn off 60 * core. 61 * @target_state: Targeted state. 62 * 63 */ 64 static void versal_net_pwr_domain_off(const psci_power_state_t *target_state) 65 { 66 uint32_t ret, fw_api_version, version_type[RET_PAYLOAD_ARG_CNT] = {0U}; 67 uint32_t cpu_id = plat_my_core_pos(); 68 const struct pm_proc *proc = pm_get_proc(cpu_id); 69 70 if (proc == NULL) { 71 goto exit_label; 72 } 73 74 for (size_t i = 0; i <= PLAT_MAX_PWR_LVL; i++) { 75 VERBOSE("%s: target_state->pwr_domain_state[%lu]=%x\n", 76 __func__, i, target_state->pwr_domain_state[i]); 77 } 78 79 /* Prevent interrupts from spuriously waking up this cpu */ 80 plat_arm_gic_cpuif_disable(); 81 82 /* 83 * Send request to PMC to power down the appropriate APU CPU 84 * core. 85 * According to PSCI specification, CPU_off function does not 86 * have resume address and CPU core can only be woken up 87 * invoking CPU_on function, during which resume address will 88 * be set. 89 */ 90 ret = pm_feature_check((uint32_t)PM_SELF_SUSPEND, &version_type[0], SECURE_FLAG); 91 if (ret == (uint32_t)PM_RET_SUCCESS) { 92 fw_api_version = version_type[0] & 0xFFFFU; 93 if (fw_api_version >= 3U) { 94 (void)pm_self_suspend(proc->node_id, MAX_LATENCY, PM_STATE_CPU_OFF, 0, 95 SECURE_FLAG); 96 } else { 97 (void)pm_self_suspend(proc->node_id, MAX_LATENCY, PM_STATE_CPU_IDLE, 0, 98 SECURE_FLAG); 99 } 100 } 101 102 exit_label: 103 return; 104 } 105 106 static int32_t versal_net_validate_ns_entrypoint(uint64_t ns_entrypoint) 107 { 108 int32_t ret = PSCI_E_SUCCESS; 109 110 if (((ns_entrypoint >= PLAT_DDR_LOWMEM_MAX) && (ns_entrypoint <= PLAT_DDR_HIGHMEM_MAX)) || 111 ((ns_entrypoint >= BL31_BASE) && (ns_entrypoint <= BL31_LIMIT))) { 112 ret = PSCI_E_INVALID_ADDRESS; 113 } 114 115 return ret; 116 } 117 118 /** 119 * versal_net_system_reset() - This function sends the reset request to firmware 120 * for the system to reset. This function does not 121 * return. 122 * 123 */ 124 static void __dead2 versal_net_system_reset(void) 125 { 126 uint32_t ret, timeout = 10000U; 127 128 request_cpu_pwrdwn(); 129 130 /* 131 * Send the system reset request to the firmware if power down request 132 * is not received from firmware. 133 */ 134 if (!pwrdwn_req_received) { 135 (void)pm_system_shutdown(XPM_SHUTDOWN_TYPE_RESET, 136 pm_get_shutdown_scope(), SECURE_FLAG); 137 138 /* 139 * Wait for system shutdown request completed and idle callback 140 * not received. 141 */ 142 do { 143 ret = ipi_mb_enquire_status(primary_proc->ipi->local_ipi_id, 144 primary_proc->ipi->remote_ipi_id); 145 udelay(100); 146 timeout--; 147 } while ((ret != IPI_MB_STATUS_RECV_PENDING) && (timeout > 0U)); 148 } 149 150 (void)psci_cpu_off(); 151 152 while (true) { 153 wfi(); 154 } 155 } 156 157 /** 158 * versal_net_pwr_domain_suspend() - This function sends request to PMC to suspend 159 * core. 160 * @target_state: Targeted state. 161 * 162 */ 163 static void versal_net_pwr_domain_suspend(const psci_power_state_t *target_state) 164 { 165 uint32_t state; 166 uint32_t cpu_id = plat_my_core_pos(); 167 const struct pm_proc *proc = pm_get_proc(cpu_id); 168 169 if (proc == NULL) { 170 goto exit_label; 171 } 172 173 for (size_t i = 0; i <= PLAT_MAX_PWR_LVL; i++) { 174 VERBOSE("%s: target_state->pwr_domain_state[%lu]=%x\n", 175 __func__, i, target_state->pwr_domain_state[i]); 176 } 177 178 plat_arm_gic_cpuif_disable(); 179 180 if (target_state->pwr_domain_state[1] > PLAT_MAX_RET_STATE) { 181 plat_arm_gic_save(); 182 } 183 184 state = (target_state->pwr_domain_state[1] > PLAT_MAX_RET_STATE) ? 185 PM_STATE_SUSPEND_TO_RAM : PM_STATE_CPU_IDLE; 186 187 /* Send request to PMC to suspend this core */ 188 (void)pm_self_suspend(proc->node_id, MAX_LATENCY, state, versal_net_sec_entry, 189 SECURE_FLAG); 190 191 /* TODO: disable coherency */ 192 193 exit_label: 194 return; 195 } 196 197 static void versal_net_pwr_domain_on_finish(const psci_power_state_t *target_state) 198 { 199 (void)target_state; 200 201 /* Enable the gic cpu interface */ 202 plat_arm_gic_pcpu_init(); 203 204 /* Program the gic per-cpu distributor or re-distributor interface */ 205 plat_arm_gic_cpuif_enable(); 206 } 207 208 /** 209 * versal_net_pwr_domain_suspend_finish() - This function performs actions to finish 210 * suspend procedure. 211 * @target_state: Targeted state. 212 * 213 */ 214 static void versal_net_pwr_domain_suspend_finish(const psci_power_state_t *target_state) 215 { 216 uint32_t cpu_id = plat_my_core_pos(); 217 const struct pm_proc *proc = pm_get_proc(cpu_id); 218 219 if (proc == NULL) { 220 goto exit_label; 221 } 222 223 for (size_t i = 0; i <= PLAT_MAX_PWR_LVL; i++) { 224 VERBOSE("%s: target_state->pwr_domain_state[%lu]=%x\n", 225 __func__, i, target_state->pwr_domain_state[i]); 226 } 227 228 /* Clear the APU power control register for this cpu */ 229 pm_client_wakeup(proc); 230 231 /* TODO: enable coherency */ 232 233 /* APU was turned off, so restore GIC context */ 234 if (target_state->pwr_domain_state[1] > PLAT_MAX_RET_STATE) { 235 plat_arm_gic_resume(); 236 } 237 238 plat_arm_gic_cpuif_enable(); 239 240 exit_label: 241 return; 242 } 243 244 /** 245 * versal_net_system_off() - This function sends the system off request 246 * to firmware. This function does not return. 247 * 248 */ 249 static void __dead2 versal_net_system_off(void) 250 { 251 /* Send the power down request to the PMC */ 252 (void)pm_system_shutdown(XPM_SHUTDOWN_TYPE_SHUTDOWN, 253 pm_get_shutdown_scope(), SECURE_FLAG); 254 255 while (true) { 256 wfi(); 257 } 258 } 259 260 /** 261 * versal_net_validate_power_state() - This function ensures that the power state 262 * parameter in request is valid. 263 * @power_state: Power state of core. 264 * @req_state: Requested state. 265 * 266 * Return: Returns status, either PSCI_E_SUCCESS or reason. 267 * 268 */ 269 static int32_t versal_net_validate_power_state(unsigned int power_state, 270 psci_power_state_t *req_state) 271 { 272 int32_t ret = PSCI_E_INVALID_PARAMS; 273 274 VERBOSE("%s: power_state: 0x%x\n", __func__, power_state); 275 276 uint32_t pstate = psci_get_pstate_type(power_state); 277 278 assert(req_state != NULL); 279 280 /* Sanity check the requested state */ 281 if (pstate == PSTATE_TYPE_STANDBY) { 282 req_state->pwr_domain_state[MPIDR_AFFLVL0] = PLAT_MAX_RET_STATE; 283 } else { 284 req_state->pwr_domain_state[MPIDR_AFFLVL0] = PLAT_MAX_OFF_STATE; 285 } 286 287 /* We expect the 'state id' to be zero */ 288 if (psci_get_pstate_id(power_state) == 0U) { 289 ret = PSCI_E_SUCCESS; 290 } 291 292 return ret; 293 } 294 295 /** 296 * versal_net_get_sys_suspend_power_state() - Get power state for system 297 * suspend. 298 * @req_state: Requested state. 299 * 300 */ 301 static void versal_net_get_sys_suspend_power_state(psci_power_state_t *req_state) 302 { 303 uint64_t i; 304 305 for (i = MPIDR_AFFLVL0; i <= PLAT_MAX_PWR_LVL; i++) { 306 req_state->pwr_domain_state[i] = PLAT_MAX_OFF_STATE; 307 } 308 } 309 310 static const struct plat_psci_ops versal_net_nopmc_psci_ops = { 311 .pwr_domain_on = versal_net_pwr_domain_on, 312 .pwr_domain_off = versal_net_pwr_domain_off, 313 .pwr_domain_on_finish = versal_net_pwr_domain_on_finish, 314 .pwr_domain_suspend = versal_net_pwr_domain_suspend, 315 .pwr_domain_suspend_finish = versal_net_pwr_domain_suspend_finish, 316 .system_off = versal_net_system_off, 317 .system_reset = versal_net_system_reset, 318 .validate_ns_entrypoint = versal_net_validate_ns_entrypoint, 319 .validate_power_state = versal_net_validate_power_state, 320 .get_sys_suspend_power_state = versal_net_get_sys_suspend_power_state, 321 }; 322 323 /******************************************************************************* 324 * Export the platform specific power ops. 325 ******************************************************************************/ 326 int32_t plat_setup_psci_ops(uintptr_t sec_entrypoint, 327 const struct plat_psci_ops **psci_ops) 328 { 329 versal_net_sec_entry = sec_entrypoint; 330 331 VERBOSE("Setting up entry point %lx\n", versal_net_sec_entry); 332 333 *psci_ops = &versal_net_nopmc_psci_ops; 334 335 return 0; 336 } 337 338 int32_t sip_svc_setup_init(void) 339 { 340 return pm_setup(); 341 } 342 343 uint64_t smc_handler(uint32_t smc_fid, uint64_t x1, uint64_t x2, uint64_t x3, uint64_t x4, 344 void *cookie, void *handle, uint64_t flags) 345 { 346 return pm_smc_handler(smc_fid, x1, x2, x3, x4, cookie, handle, flags); 347 } 348