1/* 2 * Copyright (c) 2013-2025, Arm Limited and Contributors. All rights reserved. 3 * 4 * SPDX-License-Identifier: BSD-3-Clause 5 */ 6 7#include <platform_def.h> 8 9#include <arch.h> 10#include <asm_macros.S> 11#include <bl31/ea_handle.h> 12#include <bl31/interrupt_mgmt.h> 13#include <bl31/sync_handle.h> 14#include <common/runtime_svc.h> 15#include <context.h> 16#include <cpu_macros.S> 17#include <el3_common_macros.S> 18#include <lib/el3_runtime/cpu_data.h> 19#include <lib/smccc.h> 20 21 .globl runtime_exceptions 22 23 .globl sync_exception_sp_el0 24 .globl irq_sp_el0 25 .globl fiq_sp_el0 26 .globl serror_sp_el0 27 28 .globl sync_exception_sp_elx 29 .globl irq_sp_elx 30 .globl fiq_sp_elx 31 .globl serror_sp_elx 32 33 .globl sync_exception_aarch64 34 .globl irq_aarch64 35 .globl fiq_aarch64 36 .globl serror_aarch64 37 38 .globl sync_exception_aarch32 39 .globl irq_aarch32 40 .globl fiq_aarch32 41 .globl serror_aarch32 42 43 /* 44 * Save LR and make x30 available as most of the routines in vector entry 45 * need a free register 46 */ 47 .macro save_x30 48 str x30, [sp, #CTX_GPREGS_OFFSET + CTX_GPREG_LR] 49 .endm 50 51 .macro restore_x30 52 ldr x30, [sp, #CTX_GPREGS_OFFSET + CTX_GPREG_LR] 53 .endm 54 55 /* 56 * Macro that synchronizes errors (EA) and checks for pending SError. 57 * On detecting a pending SError it either reflects it back to lower 58 * EL (KFH) or handles it in EL3 (FFH) based on EA routing model. 59 */ 60 .macro sync_and_handle_pending_serror 61 synchronize_errors 62 mrs x30, ISR_EL1 63 tbz x30, #ISR_A_SHIFT, 2f 64#if FFH_SUPPORT 65 mrs x30, scr_el3 66 tst x30, #SCR_EA_BIT 67 b.eq 1f 68 bl handle_pending_async_ea 69 b 2f 70#endif 711: 72 /* This function never returns, but need LR for decision making */ 73 bl reflect_pending_async_ea_to_lower_el 742: 75 .endm 76 77 /* --------------------------------------------------------------------- 78 * This macro handles Synchronous exceptions. 79 * Only SMC exceptions are supported. 80 * --------------------------------------------------------------------- 81 */ 82 .macro handle_sync_exception 83#if ENABLE_RUNTIME_INSTRUMENTATION 84 /* 85 * Read the timestamp value and store it in per-cpu data. The value 86 * will be extracted from per-cpu data by the C level SMC handler and 87 * saved to the PMF timestamp region. 88 */ 89 mrs x30, cntpct_el0 90 str x29, [sp, #CTX_GPREGS_OFFSET + CTX_GPREG_X29] 91 mrs x29, tpidr_el3 92 str x30, [x29, #CPU_DATA_CPU_DATA_PMF_TS] 93 ldr x29, [sp, #CTX_GPREGS_OFFSET + CTX_GPREG_X29] 94#endif 95 96 mrs x30, esr_el3 97 ubfx x30, x30, #ESR_EC_SHIFT, #ESR_EC_LENGTH 98 99 /* Handle SMC exceptions separately from other synchronous exceptions */ 100 cmp x30, #EC_AARCH32_SMC 101 b.eq smc_handler32 102 103 cmp x30, #EC_AARCH64_SMC 104 b.eq sync_handler64 105 106 cmp x30, #EC_AARCH64_SYS 107 b.eq sync_handler64 108 109 cmp x30, #EC_IMP_DEF_EL3 110 b.eq imp_def_el3_handler 111 112 /* If FFH Support then try to handle lower EL EA exceptions. */ 113#if FFH_SUPPORT 114 mrs x30, scr_el3 115 tst x30, #SCR_EA_BIT 116 b.eq 1f 117 b handle_lower_el_sync_ea 118#endif 1191: 120 /* Synchronous exceptions other than the above are unhandled */ 121 b report_unhandled_exception 122 .endm 123 124vector_base runtime_exceptions 125 126 /* --------------------------------------------------------------------- 127 * Current EL with SP_EL0 : 0x0 - 0x200 128 * --------------------------------------------------------------------- 129 */ 130vector_entry sync_exception_sp_el0 131#ifdef MONITOR_TRAPS 132 stp x29, x30, [sp, #-16]! 133 134 mrs x30, esr_el3 135 ubfx x30, x30, #ESR_EC_SHIFT, #ESR_EC_LENGTH 136 137 /* Check for BRK */ 138 cmp x30, #EC_BRK 139 b.eq brk_handler 140 141 ldp x29, x30, [sp], #16 142#endif /* MONITOR_TRAPS */ 143 144 /* We don't expect any synchronous exceptions from EL3 */ 145 b report_unhandled_exception 146end_vector_entry sync_exception_sp_el0 147 148vector_entry irq_sp_el0 149 /* 150 * EL3 code is non-reentrant. Any asynchronous exception is a serious 151 * error. Loop infinitely. 152 */ 153 b report_unhandled_interrupt 154end_vector_entry irq_sp_el0 155 156 157vector_entry fiq_sp_el0 158 b report_unhandled_interrupt 159end_vector_entry fiq_sp_el0 160 161 162vector_entry serror_sp_el0 163 no_ret plat_handle_el3_ea 164end_vector_entry serror_sp_el0 165 166 /* --------------------------------------------------------------------- 167 * Current EL with SP_ELx: 0x200 - 0x400 168 * --------------------------------------------------------------------- 169 */ 170vector_entry sync_exception_sp_elx 171 /* 172 * This exception will trigger if anything went wrong during a previous 173 * exception entry or exit or while handling an earlier unexpected 174 * synchronous exception. There is a high probability that SP_EL3 is 175 * corrupted. 176 */ 177 b report_unhandled_exception 178end_vector_entry sync_exception_sp_elx 179 180vector_entry irq_sp_elx 181 b report_unhandled_interrupt 182end_vector_entry irq_sp_elx 183 184vector_entry fiq_sp_elx 185 b report_unhandled_interrupt 186end_vector_entry fiq_sp_elx 187 188vector_entry serror_sp_elx 189#if FFH_SUPPORT 190 /* 191 * This will trigger if the exception was taken due to SError in EL3 or 192 * because of pending asynchronous external aborts from lower EL that got 193 * triggered due to implicit/explicit synchronization in EL3 (SCR_EL3.EA=1) 194 * during EL3 entry. For the former case we continue with "plat_handle_el3_ea". 195 * The later case will occur when PSTATE.A bit is cleared in 196 * "handle_pending_async_ea". This means we are doing a nested 197 * exception in EL3. Call the handler for async EA which will eret back to 198 * original el3 handler if it is nested exception. Also, unmask EA so that we 199 * catch any further EA arise when handling this nested exception at EL3. 200 */ 201 save_x30 202 ldr x30, [sp, #CTX_EL3STATE_OFFSET + CTX_NESTED_EA_FLAG] 203 cbz x30, 1f 204 /* 205 * This is nested exception handling, clear the flag to avoid taking this 206 * path for further exceptions caused by EA handling 207 */ 208 str xzr, [sp, #CTX_EL3STATE_OFFSET + CTX_NESTED_EA_FLAG] 209 unmask_async_ea 210 b handle_lower_el_async_ea 2111: 212 restore_x30 213#endif 214 no_ret plat_handle_el3_ea 215 216end_vector_entry serror_sp_elx 217 218 /* --------------------------------------------------------------------- 219 * Lower EL using AArch64 : 0x400 - 0x600 220 * --------------------------------------------------------------------- 221 */ 222vector_entry sync_exception_aarch64 223 /* 224 * This exception vector will be the entry point for SMCs and traps 225 * that are unhandled at lower ELs most commonly. SP_EL3 should point 226 * to a valid cpu context where the general purpose and system register 227 * state can be saved. 228 */ 229 save_x30 230 apply_at_speculative_wa 231 sync_and_handle_pending_serror 232 handle_sync_exception 233end_vector_entry sync_exception_aarch64 234 235vector_entry irq_aarch64 236 save_x30 237 apply_at_speculative_wa 238 sync_and_handle_pending_serror 239 b handle_interrupt_exception 240end_vector_entry irq_aarch64 241 242vector_entry fiq_aarch64 243 save_x30 244 apply_at_speculative_wa 245 sync_and_handle_pending_serror 246 b handle_interrupt_exception 247end_vector_entry fiq_aarch64 248 249 /* 250 * Need to synchronize any outstanding SError since we can get a burst of errors. 251 * So reuse the sync mechanism to catch any further errors which are pending. 252 */ 253vector_entry serror_aarch64 254#if FFH_SUPPORT 255 save_x30 256 apply_at_speculative_wa 257 sync_and_handle_pending_serror 258 b handle_lower_el_async_ea 259#else 260 b report_unhandled_exception 261#endif 262end_vector_entry serror_aarch64 263 264 /* --------------------------------------------------------------------- 265 * Lower EL using AArch32 : 0x600 - 0x800 266 * --------------------------------------------------------------------- 267 */ 268vector_entry sync_exception_aarch32 269 /* 270 * This exception vector will be the entry point for SMCs and traps 271 * that are unhandled at lower ELs most commonly. SP_EL3 should point 272 * to a valid cpu context where the general purpose and system register 273 * state can be saved. 274 */ 275 save_x30 276 apply_at_speculative_wa 277 sync_and_handle_pending_serror 278 handle_sync_exception 279end_vector_entry sync_exception_aarch32 280 281vector_entry irq_aarch32 282 save_x30 283 apply_at_speculative_wa 284 sync_and_handle_pending_serror 285 b handle_interrupt_exception 286end_vector_entry irq_aarch32 287 288vector_entry fiq_aarch32 289 save_x30 290 apply_at_speculative_wa 291 sync_and_handle_pending_serror 292 b handle_interrupt_exception 293end_vector_entry fiq_aarch32 294 295 /* 296 * Need to synchronize any outstanding SError since we can get a burst of errors. 297 * So reuse the sync mechanism to catch any further errors which are pending. 298 */ 299vector_entry serror_aarch32 300#if FFH_SUPPORT 301 save_x30 302 apply_at_speculative_wa 303 sync_and_handle_pending_serror 304 b handle_lower_el_async_ea 305#else 306 b report_unhandled_exception 307#endif 308end_vector_entry serror_aarch32 309 310#ifdef MONITOR_TRAPS 311 .section .rodata.brk_string, "aS" 312brk_location: 313 .asciz "Error at instruction 0x" 314brk_message: 315 .asciz "Unexpected BRK instruction with value 0x" 316#endif /* MONITOR_TRAPS */ 317 318 /* --------------------------------------------------------------------- 319 * The following code handles secure monitor calls. 320 * Depending upon the execution state from where the SMC has been 321 * invoked, it frees some general purpose registers to perform the 322 * remaining tasks. They involve finding the runtime service handler 323 * that is the target of the SMC & switching to runtime stacks (SP_EL0) 324 * before calling the handler. 325 * 326 * Note that x30 has been explicitly saved and can be used here 327 * --------------------------------------------------------------------- 328 */ 329func sync_exception_handler 330smc_handler32: 331 /* Check whether aarch32 issued an SMC64 */ 332 tbnz x0, #FUNCID_CC_SHIFT, smc_prohibited 333 334sync_handler64: 335 /* NOTE: The code below must preserve x0-x4 */ 336 337 /* 338 * Save general purpose and ARMv8.3-PAuth registers (if enabled). 339 * Also save PMCR_EL0 and set the PSTATE to a known state. 340 */ 341 bl prepare_el3_entry 342 343 /* 344 * Populate the parameters for the SMC handler. 345 * We already have x0-x4 in place. x5 will point to a cookie (not used 346 * now). x6 will point to the context structure (SP_EL3) and x7 will 347 * contain flags we need to pass to the handler. 348 */ 349 mov x5, xzr 350 mov x6, sp 351 352 /* 353 * Restore the saved C runtime stack value which will become the new 354 * SP_EL0 i.e. EL3 runtime stack. It was saved in the 'cpu_context' 355 * structure prior to the last ERET from EL3. 356 */ 357 ldr x12, [x6, #CTX_EL3STATE_OFFSET + CTX_RUNTIME_SP] 358 359 /* Switch to SP_EL0 */ 360 msr spsel, #MODE_SP_EL0 361 362 /* 363 * Save the SPSR_EL3 and ELR_EL3 in case there is a world 364 * switch during SMC handling. 365 * TODO: Revisit if all system registers can be saved later. 366 */ 367 mrs x16, spsr_el3 368 mrs x17, elr_el3 369 stp x16, x17, [x6, #CTX_EL3STATE_OFFSET + CTX_SPSR_EL3] 370 371 /* Load SCR_EL3 */ 372 mrs x18, scr_el3 373 374 /* check for system register traps */ 375 mrs x16, esr_el3 376 ubfx x17, x16, #ESR_EC_SHIFT, #ESR_EC_LENGTH 377 cmp x17, #EC_AARCH64_SYS 378 b.eq sysreg_handler64 379 380 /* Clear flag register */ 381 mov x7, xzr 382 383#if ENABLE_RME 384 /* Copy SCR_EL3.NSE bit to the flag to indicate caller's security */ 385 ubfx x7, x18, #SCR_NSE_SHIFT, #1 386 387 /* 388 * Shift copied SCR_EL3.NSE bit by 5 to create space for 389 * SCR_EL3.NS bit. Bit 5 of the flag corresponds to 390 * the SCR_EL3.NSE bit. 391 */ 392 lsl x7, x7, #5 393#endif /* ENABLE_RME */ 394 395 /* Copy SCR_EL3.NS bit to the flag to indicate caller's security */ 396 bfi x7, x18, #0, #1 397 398 mov sp, x12 399 400 /* 401 * Per SMCCC documentation, bits [23:17] must be zero for Fast 402 * SMCs. Other values are reserved for future use. Ensure that 403 * these bits are zeroes, if not report as unknown SMC. 404 */ 405 tbz x0, #FUNCID_TYPE_SHIFT, 2f /* Skip check if its a Yield Call*/ 406 tst x0, #(FUNCID_FC_RESERVED_MASK << FUNCID_FC_RESERVED_SHIFT) 407 b.ne smc_unknown 408 409 /* 410 * Per SMCCCv1.3 a caller can set the SVE hint bit in the SMC FID 411 * passed through x0. Copy the SVE hint bit to flags and mask the 412 * bit in smc_fid passed to the standard service dispatcher. 413 * A service/dispatcher can retrieve the SVE hint bit state from 414 * flags using the appropriate helper. 415 */ 4162: 417 and x16, x0, #(FUNCID_SVE_HINT_MASK << FUNCID_SVE_HINT_SHIFT) 418 orr x7, x7, x16 419 bic x0, x0, #(FUNCID_SVE_HINT_MASK << FUNCID_SVE_HINT_SHIFT) 420 421 /* Get the unique owning entity number */ 422 ubfx x16, x0, #FUNCID_OEN_SHIFT, #FUNCID_OEN_WIDTH 423 ubfx x15, x0, #FUNCID_TYPE_SHIFT, #FUNCID_TYPE_WIDTH 424 orr x16, x16, x15, lsl #FUNCID_OEN_WIDTH 425 426 /* Load descriptor index from array of indices */ 427 adrp x14, rt_svc_descs_indices 428 add x14, x14, :lo12:rt_svc_descs_indices 429 ldrb w15, [x14, x16] 430 431 /* Any index greater than 127 is invalid. Check bit 7. */ 432 tbnz w15, 7, smc_unknown 433 434 /* 435 * Get the descriptor using the index 436 * x11 = (base + off), w15 = index 437 * 438 * handler = (base + off) + (index << log2(size)) 439 */ 440 adr_l x11, (__RT_SVC_DESCS_START__ + RT_SVC_DESC_HANDLE) 441 lsl w10, w15, #RT_SVC_SIZE_LOG2 442 ldr x15, [x11, w10, uxtw] 443 444 /* 445 * Call the Secure Monitor Call handler and then drop directly into 446 * el3_exit() which will program any remaining architectural state 447 * prior to issuing the ERET to the desired lower EL. 448 */ 449#if DEBUG 450 cbz x15, rt_svc_fw_critical_error 451#endif 452 blr x15 453 454 b el3_exit 455 456sysreg_handler64: 457 mov x0, x16 /* ESR_EL3, containing syndrome information */ 458 mov x1, x6 /* lower EL's context */ 459 mov x19, x6 /* save context pointer for after the call */ 460 mov sp, x12 /* EL3 runtime stack, as loaded above */ 461 462 /* int handle_sysreg_trap(uint64_t esr_el3, cpu_context_t *ctx); */ 463 bl handle_sysreg_trap 464 /* 465 * returns: 466 * -1: unhandled trap, UNDEF injection into lower EL 467 * 0: handled trap, return to the trapping instruction (repeating it) 468 * 1: handled trap, return to the next instruction 469 */ 470 471 tst w0, w0 472 b.mi 2f /* negative: undefined exception injection */ 473 474 b.eq 1f /* zero: do not change ELR_EL3 */ 475 /* positive: advance the PC to continue after the instruction */ 476 ldr x1, [x19, #CTX_EL3STATE_OFFSET + CTX_ELR_EL3] 477 add x1, x1, #4 478 str x1, [x19, #CTX_EL3STATE_OFFSET + CTX_ELR_EL3] 4791: 480 b el3_exit 4812: 482 /* 483 * UNDEF injection to lower EL, the support is only provided for lower 484 * EL in AArch64 mode, for AArch32 mode it will do elx_panic as before. 485 */ 486 mrs x0, spsr_el3 487 tst x0, #(SPSR_M_MASK << SPSR_M_SHIFT) 488 b.ne elx_panic 489 /* Pass context pointer as an argument to inject_undef64 */ 490 mov x0, x19 491 bl inject_undef64 492 b el3_exit 493 494smc_unknown: 495 /* 496 * Unknown SMC call. Populate return value with SMC_UNK and call 497 * el3_exit() which will restore the remaining architectural state 498 * i.e., SYS, GP and PAuth registers(if any) prior to issuing the ERET 499 * to the desired lower EL. 500 */ 501 mov x0, #SMC_UNK 502 str x0, [x6, #CTX_GPREGS_OFFSET + CTX_GPREG_X0] 503 b el3_exit 504 505smc_prohibited: 506 restore_ptw_el1_sys_regs 507 ldp x28, x29, [sp, #CTX_GPREGS_OFFSET + CTX_GPREG_X28] 508 ldr x30, [sp, #CTX_GPREGS_OFFSET + CTX_GPREG_LR] 509 mov x0, #SMC_UNK 510 exception_return 511 512#if DEBUG 513rt_svc_fw_critical_error: 514 /* Switch to SP_ELx */ 515 msr spsel, #MODE_SP_ELX 516 no_ret report_unhandled_exception 517#endif 518endfunc sync_exception_handler 519 520 /* --------------------------------------------------------------------- 521 * This function handles FIQ or IRQ interrupts i.e. EL3, S-EL1 and NS 522 * interrupts. 523 * 524 * Note that x30 has been explicitly saved and can be used here 525 * --------------------------------------------------------------------- 526 */ 527func handle_interrupt_exception 528 /* 529 * Save general purpose and ARMv8.3-PAuth registers (if enabled). 530 * Also save PMCR_EL0 and set the PSTATE to a known state. 531 */ 532 bl prepare_el3_entry 533 534 /* Save the EL3 system registers needed to return from this exception */ 535 mrs x0, spsr_el3 536 mrs x1, elr_el3 537 stp x0, x1, [sp, #CTX_EL3STATE_OFFSET + CTX_SPSR_EL3] 538 539 /* Switch to the runtime stack i.e. SP_EL0 */ 540 ldr x2, [sp, #CTX_EL3STATE_OFFSET + CTX_RUNTIME_SP] 541 mov x20, sp 542 msr spsel, #MODE_SP_EL0 543 mov sp, x2 544 545 /* 546 * Find out whether this is a valid interrupt type. 547 * If the interrupt controller reports a spurious interrupt then return 548 * to where we came from. 549 */ 550 bl plat_ic_get_pending_interrupt_type 551 cmp x0, #INTR_TYPE_INVAL 552 b.eq interrupt_exit 553 554 /* 555 * Get the registered handler for this interrupt type. 556 * A NULL return value could be 'cause of the following conditions: 557 * 558 * a. An interrupt of a type was routed correctly but a handler for its 559 * type was not registered. 560 * 561 * b. An interrupt of a type was not routed correctly so a handler for 562 * its type was not registered. 563 * 564 * c. An interrupt of a type was routed correctly to EL3, but was 565 * deasserted before its pending state could be read. Another 566 * interrupt of a different type pended at the same time and its 567 * type was reported as pending instead. However, a handler for this 568 * type was not registered. 569 * 570 * a. and b. can only happen due to a programming error. The 571 * occurrence of c. could be beyond the control of Trusted Firmware. 572 * It makes sense to return from this exception instead of reporting an 573 * error. 574 */ 575 bl get_interrupt_type_handler 576 cbz x0, interrupt_exit 577 mov x21, x0 578 579 mov x0, #INTR_ID_UNAVAILABLE 580 581 /* Set the current security state in the 'flags' parameter */ 582 mrs x2, scr_el3 583 ubfx x1, x2, #0, #1 584 585 /* Restore the reference to the 'handle' i.e. SP_EL3 */ 586 mov x2, x20 587 588 /* x3 will point to a cookie (not used now) */ 589 mov x3, xzr 590 591 /* Call the interrupt type handler */ 592 blr x21 593 594interrupt_exit: 595 /* Return from exception, possibly in a different security state */ 596 b el3_exit 597endfunc handle_interrupt_exception 598 599func imp_def_el3_handler 600 /* Save GP registers */ 601 stp x0, x1, [sp, #CTX_GPREGS_OFFSET + CTX_GPREG_X0] 602 stp x2, x3, [sp, #CTX_GPREGS_OFFSET + CTX_GPREG_X2] 603 stp x4, x5, [sp, #CTX_GPREGS_OFFSET + CTX_GPREG_X4] 604 605 /* Get the cpu_ops pointer */ 606 bl get_cpu_ops_ptr 607 608 /* Get the cpu_ops exception handler */ 609 ldr x0, [x0, #CPU_E_HANDLER_FUNC] 610 611 /* 612 * If the reserved function pointer is NULL, this CPU does not have an 613 * implementation defined exception handler function 614 */ 615 cbz x0, el3_handler_exit 616 mrs x1, esr_el3 617 ubfx x1, x1, #ESR_EC_SHIFT, #ESR_EC_LENGTH 618 blr x0 619el3_handler_exit: 620 ldp x0, x1, [sp, #CTX_GPREGS_OFFSET + CTX_GPREG_X0] 621 ldp x2, x3, [sp, #CTX_GPREGS_OFFSET + CTX_GPREG_X2] 622 ldp x4, x5, [sp, #CTX_GPREGS_OFFSET + CTX_GPREG_X4] 623 restore_x30 624 no_ret report_unhandled_exception 625endfunc imp_def_el3_handler 626 627/* 628 * Handler for async EA from lower EL synchronized at EL3 entry in KFH mode. 629 * 630 * This scenario may arise when there is an error (EA) in the system which is not 631 * yet signaled to PE while executing in lower EL. During entry into EL3, the errors 632 * are synchronized either implicitly or explicitly causing async EA to pend at EL3. 633 * 634 * On detecting the pending EA (via ISR_EL1.A) and if the EA routing model is 635 * KFH (SCR_EL3.EA = 1) this handler reflects ther error back to lower EL. 636 * 637 * This function assumes x30 has been saved. 638 */ 639func reflect_pending_async_ea_to_lower_el 640 /* 641 * As the original exception was not handled we need to ensure that we return 642 * back to the instruction which caused the exception. To acheive that, eret 643 * to "elr-4" (Label "subtract_elr_el3") for SMC or simply eret otherwise 644 * (Label "skip_smc_check"). 645 * 646 * LIMITATION: It could be that async EA is masked at the target exception level 647 * or the priority of async EA wrt to the EL3/secure interrupt is lower, which 648 * causes back and forth between lower EL and EL3. In case of back and forth between 649 * lower EL and EL3, we can track the loop count in "CTX_NESTED_EA_FLAG" and leverage 650 * previous ELR in "CTX_SAVED_ELR_EL3" to detect this cycle and further panic 651 * to indicate a problem here (Label "check_loop_ctr"). If we are in this cycle, loop 652 * counter retains its value but if we do a normal el3_exit this flag gets cleared. 653 * However, setting SCR_EL3.IESB = 1, should give priority to SError handling 654 * as per AArch64.TakeException pseudo code in Arm ARM. 655 * 656 * TODO: In future if EL3 gets a capability to inject a virtual SError to lower 657 * ELs, we can remove the el3_panic and handle the original exception first and 658 * inject SError to lower EL before ereting back. 659 */ 660 stp x28, x29, [sp, #CTX_GPREGS_OFFSET + CTX_GPREG_X28] 661 ldr x29, [sp, #CTX_EL3STATE_OFFSET + CTX_SAVED_ELR_EL3] 662 mrs x28, elr_el3 663 cmp x29, x28 664 b.eq check_loop_ctr 665 str x28, [sp, #CTX_EL3STATE_OFFSET + CTX_SAVED_ELR_EL3] 666 /* Zero the loop counter */ 667 str xzr, [sp, #CTX_EL3STATE_OFFSET + CTX_NESTED_EA_FLAG] 668 b skip_loop_ctr 669check_loop_ctr: 670 ldr x29, [sp, #CTX_EL3STATE_OFFSET + CTX_NESTED_EA_FLAG] 671 add x29, x29, #1 672 str x29, [sp, #CTX_EL3STATE_OFFSET + CTX_NESTED_EA_FLAG] 673 cmp x29, #ASYNC_EA_REPLAY_COUNTER 674 b.ge el3_panic 675skip_loop_ctr: 676 /* 677 * Logic to distinguish if we came from SMC or any other exception. 678 * Use offsets in vector entry to get which exception we are handling. 679 * In each vector entry of size 0x200, address "0x0-0x80" is for sync 680 * exception and "0x80-0x200" is for async exceptions. 681 * Use vector base address (vbar_el3) and exception offset (LR) to 682 * calculate whether the address we came from is any of the following 683 * "0x0-0x80", "0x200-0x280", "0x400-0x480" or "0x600-0x680" 684 */ 685 mrs x29, vbar_el3 686 sub x30, x30, x29 687 and x30, x30, #0x1ff 688 cmp x30, #0x80 689 b.ge skip_smc_check 690 /* Its a synchronous exception, Now check if it is SMC or not? */ 691 mrs x30, esr_el3 692 ubfx x30, x30, #ESR_EC_SHIFT, #ESR_EC_LENGTH 693 cmp x30, #EC_AARCH32_SMC 694 b.eq subtract_elr_el3 695 cmp x30, #EC_AARCH64_SMC 696 b.eq subtract_elr_el3 697 b skip_smc_check 698subtract_elr_el3: 699 sub x28, x28, #4 700skip_smc_check: 701 msr elr_el3, x28 702 ldp x28, x29, [sp, #CTX_GPREGS_OFFSET + CTX_GPREG_X28] 703 ldr x30, [sp, #CTX_GPREGS_OFFSET + CTX_GPREG_LR] 704 exception_return 705endfunc reflect_pending_async_ea_to_lower_el 706 707 /* --------------------------------------------------------------------- 708 * The following code handles exceptions caused by BRK instructions. 709 * Following a BRK instruction, the only real valid cause of action is 710 * to print some information and panic, as the code that caused it is 711 * likely in an inconsistent internal state. 712 * 713 * This is initially intended to be used in conjunction with 714 * __builtin_trap. 715 * --------------------------------------------------------------------- 716 */ 717#ifdef MONITOR_TRAPS 718func brk_handler 719 /* Extract the ISS */ 720 mrs x10, esr_el3 721 ubfx x10, x10, #ESR_ISS_SHIFT, #ESR_ISS_LENGTH 722 723 /* Ensure the console is initialized */ 724 bl plat_crash_console_init 725 726 adr x4, brk_location 727 bl asm_print_str 728 mrs x4, elr_el3 729 bl asm_print_hex 730 bl asm_print_newline 731 732 adr x4, brk_message 733 bl asm_print_str 734 mov x4, x10 735 mov x5, #28 736 bl asm_print_hex_bits 737 bl asm_print_newline 738 739 no_ret plat_panic_handler 740endfunc brk_handler 741#endif /* MONITOR_TRAPS */ 742