1/* 2 * Copyright (c) 2024-2025, Arm Limited. All rights reserved. 3 * 4 * SPDX-License-Identifier: BSD-3-Clause 5 */ 6 7#include <arch.h> 8#include <asm_macros.S> 9#include <common/bl_common.h> 10#include <cortex_a720_ae.h> 11#include <cpu_macros.S> 12#include <plat_macros.S> 13 14/* Hardware handled coherency */ 15#if HW_ASSISTED_COHERENCY == 0 16#error "Cortex-A720AE must be compiled with HW_ASSISTED_COHERENCY enabled" 17#endif 18 19/* 64-bit only core */ 20#if CTX_INCLUDE_AARCH32_REGS == 1 21#error "Cortex-A720AE supports only AArch64. Compile with CTX_INCLUDE_AARCH32_REGS=0" 22#endif 23 24.global check_erratum_cortex_a720_ae_3699562 25 26add_erratum_entry cortex_a720_ae, ERRATUM(3699562), ERRATA_A720_AE_3699562, NO_APPLY_AT_RESET 27 28check_erratum_ls cortex_a720_ae, ERRATUM(3699562), CPU_REV(0, 0) 29 30cpu_reset_func_start cortex_a720_ae 31 /* Disable speculative loads */ 32 msr SSBS, xzr 33cpu_reset_func_end cortex_a720_ae 34 35 /* ---------------------------------------------------- 36 * HW will do the cache maintenance while powering down 37 * ---------------------------------------------------- 38 */ 39func cortex_a720_ae_core_pwr_dwn 40 /* --------------------------------------------------- 41 * Enable CPU power down bit in power control register 42 * --------------------------------------------------- 43 */ 44 sysreg_bit_set CORTEX_A720_AE_CPUPWRCTLR_EL1, CORTEX_A720_AE_CPUPWRCTLR_EL1_CORE_PWRDN_BIT 45 46 isb 47 ret 48endfunc cortex_a720_ae_core_pwr_dwn 49 50 /* --------------------------------------------- 51 * This function provides Cortex-A720AE specific 52 * register information for crash reporting. 53 * It needs to return with x6 pointing to 54 * a list of register names in ascii and 55 * x8 - x15 having values of registers to be 56 * reported. 57 * --------------------------------------------- 58 */ 59.section .rodata.cortex_a720_ae_regs, "aS" 60cortex_a720_ae_regs: /* The ascii list of register names to be reported */ 61 .asciz "cpuectlr_el1", "" 62 63func cortex_a720_ae_cpu_reg_dump 64 adr x6, cortex_a720_ae_regs 65 mrs x8, CORTEX_A720_AE_CPUECTLR_EL1 66 ret 67endfunc cortex_a720_ae_cpu_reg_dump 68 69declare_cpu_ops cortex_a720_ae, CORTEX_A720_AE_MIDR, \ 70 cortex_a720_ae_reset_func, \ 71 cortex_a720_ae_core_pwr_dwn 72