1/* 2 * Copyright (c) 2021-2025, Arm Limited. All rights reserved. 3 * 4 * SPDX-License-Identifier: BSD-3-Clause 5 */ 6 7#include <arch.h> 8#include <asm_macros.S> 9#include <common/bl_common.h> 10#include <cortex_a720.h> 11#include <cpu_macros.S> 12#include <plat_macros.S> 13#include "wa_cve_2022_23960_bhb_vector.S" 14 15/* Hardware handled coherency */ 16#if HW_ASSISTED_COHERENCY == 0 17#error "Cortex A720 must be compiled with HW_ASSISTED_COHERENCY enabled" 18#endif 19 20/* 64-bit only core */ 21#if CTX_INCLUDE_AARCH32_REGS == 1 22#error "Cortex A720 supports only AArch64. Compile with CTX_INCLUDE_AARCH32_REGS=0" 23#endif 24 25.global check_erratum_cortex_a720_3699561 26 27#if WORKAROUND_CVE_2022_23960 28 wa_cve_2022_23960_bhb_vector_table CORTEX_A720_BHB_LOOP_COUNT, cortex_a720 29#endif /* WORKAROUND_CVE_2022_23960 */ 30 31workaround_reset_start cortex_a720, ERRATUM(2792132), ERRATA_A720_2792132 32 sysreg_bit_set CORTEX_A720_CPUACTLR2_EL1, BIT(26) 33workaround_reset_end cortex_a720, ERRATUM(2792132) 34 35check_erratum_ls cortex_a720, ERRATUM(2792132), CPU_REV(0, 1) 36 37workaround_reset_start cortex_a720, ERRATUM(2844092), ERRATA_A720_2844092 38 sysreg_bit_set CORTEX_A720_CPUACTLR4_EL1, BIT(11) 39workaround_reset_end cortex_a720, ERRATUM(2844092) 40 41check_erratum_ls cortex_a720, ERRATUM(2844092), CPU_REV(0, 1) 42 43workaround_reset_start cortex_a720, ERRATUM(2926083), ERRATA_A720_2926083 44/* Erratum 2926083 workaround is required only if SPE is enabled */ 45#if ENABLE_SPE_FOR_NS != 0 46 /* Check if Static profiling extension is implemented or present. */ 47 mrs x1, id_aa64dfr0_el1 48 ubfx x0, x1, ID_AA64DFR0_PMS_SHIFT, #4 49 cbz x0, 1f 50 /* Apply the workaround by setting CPUACTLR_EL1[58:57] = 0b11. */ 51 sysreg_bit_set CORTEX_A720_CPUACTLR_EL1, BIT(57) 52 sysreg_bit_set CORTEX_A720_CPUACTLR_EL1, BIT(58) 531: 54#endif 55workaround_reset_end cortex_a720, ERRATUM(2926083) 56 57check_erratum_ls cortex_a720, ERRATUM(2926083), CPU_REV(0, 1) 58 59workaround_reset_start cortex_a720, ERRATUM(2940794), ERRATA_A720_2940794 60 sysreg_bit_set CORTEX_A720_CPUACTLR2_EL1, BIT(37) 61workaround_reset_end cortex_a720, ERRATUM(2940794) 62 63check_erratum_ls cortex_a720, ERRATUM(2940794), CPU_REV(0, 1) 64 65workaround_reset_start cortex_a720, CVE(2022, 23960), WORKAROUND_CVE_2022_23960 66#if IMAGE_BL31 67 /* 68 * The Cortex A720 generic vectors are overridden to apply errata 69 * mitigation on exception entry from lower ELs. 70 */ 71 override_vector_table wa_cve_vbar_cortex_a720 72#endif /* IMAGE_BL31 */ 73workaround_reset_end cortex_a720, CVE(2022, 23960) 74 75check_erratum_chosen cortex_a720, CVE(2022, 23960), WORKAROUND_CVE_2022_23960 76 77add_erratum_entry cortex_a720, ERRATUM(3699561), ERRATA_A720_3699561, NO_APPLY_AT_RESET 78 79check_erratum_ls cortex_a720, ERRATUM(3699561), CPU_REV(0, 2) 80 81cpu_reset_func_start cortex_a720 82 /* Disable speculative loads */ 83 msr SSBS, xzr 84cpu_reset_func_end cortex_a720 85 86 /* ---------------------------------------------------- 87 * HW will do the cache maintenance while powering down 88 * ---------------------------------------------------- 89 */ 90func cortex_a720_core_pwr_dwn 91 /* --------------------------------------------------- 92 * Enable CPU power down bit in power control register 93 * --------------------------------------------------- 94 */ 95 sysreg_bit_set CORTEX_A720_CPUPWRCTLR_EL1, CORTEX_A720_CPUPWRCTLR_EL1_CORE_PWRDN_BIT 96 97 isb 98 ret 99endfunc cortex_a720_core_pwr_dwn 100 101 /* --------------------------------------------- 102 * This function provides Cortex A720-specific 103 * register information for crash reporting. 104 * It needs to return with x6 pointing to 105 * a list of register names in ascii and 106 * x8 - x15 having values of registers to be 107 * reported. 108 * --------------------------------------------- 109 */ 110.section .rodata.cortex_a720_regs, "aS" 111cortex_a720_regs: /* The ascii list of register names to be reported */ 112 .asciz "cpuectlr_el1", "" 113 114func cortex_a720_cpu_reg_dump 115 adr x6, cortex_a720_regs 116 mrs x8, CORTEX_A720_CPUECTLR_EL1 117 ret 118endfunc cortex_a720_cpu_reg_dump 119 120declare_cpu_ops cortex_a720, CORTEX_A720_MIDR, \ 121 cortex_a720_reset_func, \ 122 cortex_a720_core_pwr_dwn 123