1/* 2 * Copyright (c) 2020-2024, Arm Limited. All rights reserved. 3 * 4 * SPDX-License-Identifier: BSD-3-Clause 5 */ 6 7/* If SCMI power domain control is enabled */ 8#if TC_SCMI_PD_CTRL_EN 9#define GPU_SCMI_PD_IDX (PLAT_MAX_CPUS_PER_CLUSTER + 1) 10#define DPU_SCMI_PD_IDX (PLAT_MAX_CPUS_PER_CLUSTER + 2) 11#endif /* TC_SCMI_PD_CTRL_EN */ 12 13/* Use SCMI controlled clocks */ 14#if TC_DPU_USE_SCMI_CLK 15#define DPU_CLK_ATTR1 \ 16 clocks = <&scmi_clk 0>; \ 17 clock-names = "aclk" 18 19#define DPU_CLK_ATTR2 \ 20 clocks = <&scmi_clk 1>; \ 21 clock-names = "pxclk" 22 23#define DPU_CLK_ATTR3 \ 24 clocks = <&scmi_clk 2>; \ 25 clock-names = "pxclk" \ 26/* Use fixed clocks */ 27#else /* !TC_DPU_USE_SCMI_CLK */ 28#define DPU_CLK_ATTR1 \ 29 clocks = <&dpu_aclk>; \ 30 clock-names = "aclk" 31 32#define DPU_CLK_ATTR2 \ 33 clocks = <&dpu_pixel_clk>, <&dpu_aclk>; \ 34 clock-names = "pxclk", "aclk" 35 36#define DPU_CLK_ATTR3 DPU_CLK_ATTR2 37#endif /* !TC_DPU_USE_SCMI_CLK */ 38 39/ { 40 compatible = "arm,tc"; 41 interrupt-parent = <&gic>; 42 #address-cells = <2>; 43 #size-cells = <2>; 44 45 aliases { 46 serial0 = &os_uart; 47 }; 48 49 cpus { 50 #address-cells = <1>; 51 #size-cells = <0>; 52 53 cpu-map { 54 cluster0 { 55 core0 { 56 cpu = <&CPU0>; 57 }; 58 core1 { 59 cpu = <&CPU1>; 60 }; 61 core2 { 62 cpu = <&CPU2>; 63 }; 64 core3 { 65 cpu = <&CPU3>; 66 }; 67 core4 { 68 cpu = <&CPU4>; 69 }; 70 core5 { 71 cpu = <&CPU5>; 72 }; 73 core6 { 74 cpu = <&CPU6>; 75 }; 76 core7 { 77 cpu = <&CPU7>; 78 }; 79 }; 80 }; 81 82 /* 83 * The timings below are just to demonstrate working cpuidle. 84 * These values may be inaccurate. 85 */ 86 idle-states { 87 entry-method = "psci"; 88 89 CPU_SLEEP_0: cpu-sleep-0 { 90 compatible = "arm,idle-state"; 91 arm,psci-suspend-param = <0x0010000>; 92 local-timer-stop; 93 entry-latency-us = <300>; 94 exit-latency-us = <1200>; 95 min-residency-us = <2000>; 96 }; 97 CLUSTER_SLEEP_0: cluster-sleep-0 { 98 compatible = "arm,idle-state"; 99 arm,psci-suspend-param = <0x1010000>; 100 local-timer-stop; 101 entry-latency-us = <400>; 102 exit-latency-us = <1200>; 103 min-residency-us = <2500>; 104 }; 105 }; 106 107 amus { 108 amu: amu-0 { 109 #address-cells = <1>; 110 #size-cells = <0>; 111 112 mpmm_gear0: counter@0 { 113 reg = <0>; 114 enable-at-el3; 115 }; 116 117 mpmm_gear1: counter@1 { 118 reg = <1>; 119 enable-at-el3; 120 }; 121 122 mpmm_gear2: counter@2 { 123 reg = <2>; 124 enable-at-el3; 125 }; 126 }; 127 }; 128 129 CPU0:cpu@0 { 130 device_type = "cpu"; 131 compatible = "arm,armv8"; 132 reg = <0x0>; 133 enable-method = "psci"; 134 clocks = <&scmi_dvfs 0>; 135 cpu-idle-states = <&CPU_SLEEP_0 &CLUSTER_SLEEP_0>; 136 capacity-dmips-mhz = <LIT_CAPACITY>; 137 amu = <&amu>; 138 supports-mpmm; 139 }; 140 141 CPU1:cpu@100 { 142 device_type = "cpu"; 143 compatible = "arm,armv8"; 144 reg = <0x100>; 145 enable-method = "psci"; 146 clocks = <&scmi_dvfs 0>; 147 cpu-idle-states = <&CPU_SLEEP_0 &CLUSTER_SLEEP_0>; 148 capacity-dmips-mhz = <LIT_CAPACITY>; 149 amu = <&amu>; 150 supports-mpmm; 151 }; 152 153 CPU2:cpu@200 { 154 device_type = "cpu"; 155 compatible = "arm,armv8"; 156 reg = <0x200>; 157 enable-method = "psci"; 158 cpu-idle-states = <&CPU_SLEEP_0 &CLUSTER_SLEEP_0>; 159 amu = <&amu>; 160 supports-mpmm; 161 }; 162 163 CPU3:cpu@300 { 164 device_type = "cpu"; 165 compatible = "arm,armv8"; 166 reg = <0x300>; 167 enable-method = "psci"; 168 cpu-idle-states = <&CPU_SLEEP_0 &CLUSTER_SLEEP_0>; 169 amu = <&amu>; 170 supports-mpmm; 171 }; 172 173 CPU4:cpu@400 { 174 device_type = "cpu"; 175 compatible = "arm,armv8"; 176 reg = <0x400>; 177 enable-method = "psci"; 178 clocks = <&scmi_dvfs 1>; 179 cpu-idle-states = <&CPU_SLEEP_0 &CLUSTER_SLEEP_0>; 180 capacity-dmips-mhz = <MID_CAPACITY>; 181 amu = <&amu>; 182 supports-mpmm; 183 }; 184 185 CPU5:cpu@500 { 186 device_type = "cpu"; 187 compatible = "arm,armv8"; 188 reg = <0x500>; 189 enable-method = "psci"; 190 clocks = <&scmi_dvfs 1>; 191 cpu-idle-states = <&CPU_SLEEP_0 &CLUSTER_SLEEP_0>; 192 capacity-dmips-mhz = <MID_CAPACITY>; 193 amu = <&amu>; 194 supports-mpmm; 195 }; 196 197 CPU6:cpu@600 { 198 device_type = "cpu"; 199 compatible = "arm,armv8"; 200 reg = <0x600>; 201 enable-method = "psci"; 202 cpu-idle-states = <&CPU_SLEEP_0 &CLUSTER_SLEEP_0>; 203 amu = <&amu>; 204 supports-mpmm; 205 }; 206 207 CPU7:cpu@700 { 208 device_type = "cpu"; 209 compatible = "arm,armv8"; 210 reg = <0x700>; 211 enable-method = "psci"; 212 cpu-idle-states = <&CPU_SLEEP_0 &CLUSTER_SLEEP_0>; 213 amu = <&amu>; 214 supports-mpmm; 215 }; 216 }; 217 218 reserved-memory { 219 #address-cells = <2>; 220 #size-cells = <2>; 221 ranges; 222 223 linux,cma { 224 compatible = "shared-dma-pool"; 225 reusable; 226 size = <0x0 0x8000000>; 227 linux,cma-default; 228 }; 229 230 optee { 231 compatible = "restricted-dma-pool"; 232 reg = <0x0 TC_NS_OPTEE_BASE 0x0 TC_NS_OPTEE_SIZE>; 233 }; 234 235 }; 236 237 memory { 238 device_type = "memory"; 239 reg = <0x0 TC_NS_DRAM1_BASE 0x0 TC_NS_DRAM1_SIZE>, 240 <HI(PLAT_ARM_DRAM2_BASE) LO(PLAT_ARM_DRAM2_BASE) 241 HI(TC_NS_DRAM2_SIZE) LO(TC_NS_DRAM2_SIZE)>; 242 }; 243 244 psci { 245 compatible = "arm,psci-1.0", "arm,psci-0.2"; 246 method = "smc"; 247 }; 248 249 cpu-pmu-little { 250 compatible = LIT_CPU_PMU_COMPATIBLE; 251 interrupts = <GIC_PPI 7 IRQ_TYPE_LEVEL_HIGH &ppi_partition_little>; 252 status = "okay"; 253 }; 254 255 cpu-pmu-mid { 256 compatible = MID_CPU_PMU_COMPATIBLE; 257 interrupts = <GIC_PPI 7 IRQ_TYPE_LEVEL_HIGH &ppi_partition_mid>; 258 status = "okay"; 259 }; 260 261 cpu-pmu-big { 262 compatible = BIG_CPU_PMU_COMPATIBLE; 263 interrupts = <GIC_PPI 7 IRQ_TYPE_LEVEL_HIGH &ppi_partition_big>; 264 status = "okay"; 265 }; 266 267 sram: sram@6000000 { 268 compatible = "mmio-sram"; 269 reg = <0x0 PLAT_ARM_NSRAM_BASE 0x0 PLAT_ARM_NSRAM_SIZE>; 270 271 #address-cells = <1>; 272 #size-cells = <1>; 273 ranges = <0 0x0 PLAT_ARM_NSRAM_BASE PLAT_ARM_NSRAM_SIZE>; 274 275 cpu_scp_scmi_a2p: scp-shmem@0 { 276 compatible = "arm,scmi-shmem"; 277 reg = <0x0 0x80>; 278 }; 279 }; 280 281 mbox_db_rx: mhu@MHU_RX_ADDR { 282 compatible = MHU_RX_COMPAT; 283 reg = <0x0 ADDRESSIFY(MHU_RX_ADDR) 0x0 MHU_OFFSET>; 284 clocks = <&soc_refclk>; 285 clock-names = "apb_pclk"; 286 #mbox-cells = <MHU_MBOX_CELLS>; 287 interrupts = <GIC_SPI MHU_RX_INT_NUM IRQ_TYPE_LEVEL_HIGH 0>; 288 interrupt-names = MHU_RX_INT_NAME; 289 }; 290 291 mbox_db_tx: mhu@MHU_TX_ADDR { 292 compatible = MHU_TX_COMPAT; 293 reg = <0x0 ADDRESSIFY(MHU_TX_ADDR) 0x0 MHU_OFFSET>; 294 clocks = <&soc_refclk>; 295 clock-names = "apb_pclk"; 296 #mbox-cells = <MHU_MBOX_CELLS>; 297 interrupt-names = MHU_TX_INT_NAME; 298 }; 299 300 firmware { 301 scmi { 302 compatible = "arm,scmi"; 303 mbox-names = "tx", "rx"; 304 #address-cells = <1>; 305 #size-cells = <0>; 306 307#if TC_SCMI_PD_CTRL_EN 308 scmi_devpd: protocol@11 { 309 reg = <0x11>; 310 #power-domain-cells = <1>; 311 }; 312#endif /* TC_SCMI_PD_CTRL_EN */ 313 314 scmi_dvfs: protocol@13 { 315 reg = <0x13>; 316 #clock-cells = <1>; 317 }; 318 319 scmi_clk: protocol@14 { 320 reg = <0x14>; 321 #clock-cells = <1>; 322 }; 323 }; 324 }; 325 326 gic: interrupt-controller@GIC_CTRL_ADDR { 327 compatible = "arm,gic-v3"; 328 #address-cells = <2>; 329 #interrupt-cells = <4>; 330 #size-cells = <2>; 331 ranges; 332 interrupt-controller; 333 reg = <0x0 0x30000000 0 0x10000>, /* GICD */ 334 <0x0 0x30080000 0 GIC_GICR_OFFSET>; /* GICR */ 335 interrupts = <GIC_PPI 0x9 IRQ_TYPE_LEVEL_LOW 0>; 336 }; 337 338 timer { 339 compatible = "arm,armv8-timer"; 340 interrupts = <GIC_PPI 13 IRQ_TYPE_LEVEL_LOW 0>, 341 <GIC_PPI 14 IRQ_TYPE_LEVEL_LOW 0>, 342 <GIC_PPI 11 IRQ_TYPE_LEVEL_LOW 0>, 343 <GIC_PPI 10 IRQ_TYPE_LEVEL_LOW 0>; 344 }; 345 346 spe-pmu-mid { 347 compatible = "arm,statistical-profiling-extension-v1"; 348 interrupts = <GIC_PPI 1 IRQ_TYPE_LEVEL_HIGH &ppi_partition_mid>; 349 status = "disabled"; 350 }; 351 352 spe-pmu-big { 353 compatible = "arm,statistical-profiling-extension-v1"; 354 interrupts = <GIC_PPI 1 IRQ_TYPE_LEVEL_HIGH &ppi_partition_big>; 355 status = "disabled"; 356 }; 357 358 soc_refclk: refclk { 359 compatible = "fixed-clock"; 360 #clock-cells = <0>; 361 clock-frequency = <1000000000>; 362 clock-output-names = "apb_pclk"; 363 }; 364 365 soc_refclk60mhz: refclk60mhz { 366 compatible = "fixed-clock"; 367 #clock-cells = <0>; 368 clock-frequency = <60000000>; 369 clock-output-names = "iofpga_clk"; 370 }; 371 372 soc_uartclk: uartclk { 373 compatible = "fixed-clock"; 374 #clock-cells = <0>; 375 clock-frequency = <TC_UARTCLK>; 376 clock-output-names = "uartclk"; 377 }; 378 379 /* soc_uart0 on FPGA, ap_ns_uart on FVP */ 380 os_uart: serial@2a400000 { 381 compatible = "arm,pl011", "arm,primecell"; 382 reg = <0x0 0x2A400000 0x0 UART_OFFSET>; 383 interrupts = <GIC_SPI 63 IRQ_TYPE_LEVEL_HIGH 0>; 384 clocks = <&soc_uartclk>, <&soc_refclk>; 385 clock-names = "uartclk", "apb_pclk"; 386 status = "okay"; 387 }; 388 389#if !TC_DPU_USE_SCMI_CLK 390 dpu_aclk: dpu_aclk { 391 compatible = "fixed-clock"; 392 #clock-cells = <0>; 393 clock-frequency = <LCD_TIMING_CLK>; 394 clock-output-names = "fpga:dpu_aclk"; 395 }; 396 397 dpu_pixel_clk: dpu-pixel-clk { 398 compatible = "fixed-clock"; 399 #clock-cells = <0>; 400 clock-frequency = <LCD_TIMING_CLK>; 401 clock-output-names = "pxclk"; 402 }; 403#endif /* !TC_DPU_USE_SCMI_CLK */ 404 405#if TC_DPU_USE_SIMPLE_PANEL 406 vpanel { 407 compatible = "panel-dpi"; 408 post-init-providers = <&pl0>; 409 port { 410 lcd_in: endpoint { 411 remote-endpoint = <&dp_pl0_out0>; 412 }; 413 }; 414 415 panel-timing { 416 LCD_TIMING; 417 }; 418 }; 419 420#else 421 vencoder { 422 compatible = "drm,virtual-encoder"; 423 port { 424 lcd_in: endpoint { 425 remote-endpoint = <&dp_pl0_out0>; 426 }; 427 }; 428 429 display-timings { 430 timing-panel { 431 LCD_TIMING; 432 }; 433 }; 434 435 }; 436#endif 437 ethernet: ethernet@ETHERNET_ADDR { 438 reg = <0x0 ADDRESSIFY(ETHERNET_ADDR) 0x0 0x10000>; 439 interrupts = <GIC_SPI ETHERNET_INT IRQ_TYPE_LEVEL_HIGH 0>; 440 441 reg-io-width = <2>; 442 smsc,irq-push-pull; 443 }; 444 445 bp_clock24mhz: clock24mhz { 446 compatible = "fixed-clock"; 447 #clock-cells = <0>; 448 clock-frequency = <24000000>; 449 clock-output-names = "bp:clock24mhz"; 450 }; 451 452 sysreg: sysreg@SYS_REGS_ADDR { 453 compatible = "arm,vexpress-sysreg"; 454 reg = <0x0 ADDRESSIFY(SYS_REGS_ADDR) 0x0 0x1000>; 455 gpio-controller; 456 #gpio-cells = <2>; 457 }; 458 459 fixed_3v3: v2m-3v3 { 460 compatible = "regulator-fixed"; 461 regulator-name = "3V3"; 462 regulator-min-microvolt = <3300000>; 463 regulator-max-microvolt = <3300000>; 464 regulator-always-on; 465 }; 466 467 mmci: mmci@MMC_ADDR { 468 compatible = "arm,pl180", "arm,primecell"; 469 reg = <0x0 ADDRESSIFY(MMC_ADDR) 0x0 0x1000>; 470 interrupts = <GIC_SPI MMC_INT_0 IRQ_TYPE_LEVEL_HIGH 0>, 471 <GIC_SPI MMC_INT_1 IRQ_TYPE_LEVEL_HIGH 0>; 472 wp-gpios = <&sysreg 1 0>; 473 bus-width = <4>; 474 max-frequency = <25000000>; 475 vmmc-supply = <&fixed_3v3>; 476 clocks = <&bp_clock24mhz>, <&bp_clock24mhz>; 477 clock-names = "mclk", "apb_pclk"; 478 }; 479 480 gpu_clk: gpu_clk { 481 compatible = "fixed-clock"; 482 #clock-cells = <0>; 483 clock-frequency = <1000000000>; 484 }; 485 486 gpu_core_clk: gpu_core_clk { 487 compatible = "fixed-clock"; 488 #clock-cells = <0>; 489 clock-frequency = <1000000000>; 490 }; 491 492 gpu: gpu@2d000000 { 493 compatible = "arm,mali-midgard"; 494 reg = <0x0 0x2d000000 0x0 0x200000>; 495 clocks = <&gpu_core_clk>; 496 clock-names = "shadercores"; 497#if TC_SCMI_PD_CTRL_EN 498 power-domains = <&scmi_devpd GPU_SCMI_PD_IDX>; 499 scmi-perf-domain = <3>; 500#endif /* TC_SCMI_PD_CTRL_EN */ 501 502 pbha { 503 int-id-override = <0 0x22>, <2 0x23>, <4 0x23>, <7 0x22>, 504 <8 0x22>, <9 0x22>, <10 0x22>, <11 0x22>, 505 <12 0x22>, <13 0x22>, <16 0x22>, <17 0x32>, 506 <18 0x32>, <19 0x22>, <20 0x22>, <21 0x32>, 507 <22 0x32>, <24 0x22>, <28 0x32>; 508 propagate-bits = <0x0f>; 509 }; 510 }; 511 512 power_model_simple { 513 /* 514 * Numbers used are irrelevant to Titan, 515 * it helps suppressing the kernel warnings. 516 */ 517 compatible = "arm,mali-simple-power-model"; 518 static-coefficient = <2427750>; 519 dynamic-coefficient = <4687>; 520 ts = <20000 2000 (-20) 2>; 521 thermal-zone = ""; 522 }; 523 524 smmu_600: smmu@2ce00000 { 525 compatible = "arm,smmu-v3"; 526 reg = <0 0x2ce00000 0 0x20000>; 527 interrupts = <GIC_SPI 75 IRQ_TYPE_EDGE_RISING 0>, 528 <GIC_SPI 74 IRQ_TYPE_EDGE_RISING 0>, 529 <GIC_SPI 76 IRQ_TYPE_EDGE_RISING 0>, 530 <GIC_SPI 77 IRQ_TYPE_EDGE_RISING 0>; 531 interrupt-names = "eventq", "priq", "cmdq-sync", "gerror"; 532 #iommu-cells = <1>; 533 status = "disabled"; 534 }; 535 536 smmu_700: iommu@3f000000 { 537 #iommu-cells = <1>; 538 compatible = "arm,smmu-v3"; 539 reg = <0x0 0x3f000000 0x0 0x5000000>; 540 interrupts = <GIC_SPI 228 IRQ_TYPE_EDGE_RISING 0>, 541 <GIC_SPI 229 IRQ_TYPE_EDGE_RISING 0>, 542 <GIC_SPI 230 IRQ_TYPE_EDGE_RISING 0>; 543 interrupt-names = "eventq", "cmdq-sync", "gerror"; 544 dma-coherent; 545 status = "disabled"; 546 }; 547 548 smmu_700_dpu: iommu@4002a00000 { 549 #iommu-cells = <1>; 550 compatible = "arm,smmu-v3"; 551 reg = <HI(0x4002a00000) LO(0x4002a00000) 0x0 0x5000000>; 552 interrupts = <GIC_SPI 481 IRQ_TYPE_EDGE_RISING 0>, 553 <GIC_SPI 482 IRQ_TYPE_EDGE_RISING 0>, 554 <GIC_SPI 483 IRQ_TYPE_EDGE_RISING 0>; 555 interrupt-names = "eventq", "cmdq-sync", "gerror"; 556 dma-coherent; 557 status = "disabled"; 558 }; 559 560 dp0: display@DPU_ADDR { 561 #address-cells = <1>; 562 #size-cells = <0>; 563 compatible = "arm,mali-d71"; 564 reg = <HI(ADDRESSIFY(DPU_ADDR)) LO(ADDRESSIFY(DPU_ADDR)) 0 0x20000>; 565 interrupts = <GIC_SPI DPU_IRQ IRQ_TYPE_LEVEL_HIGH 0>; 566 interrupt-names = "DPU"; 567 DPU_CLK_ATTR1; 568 569 pl0: pipeline@0 { 570 reg = <0>; 571 DPU_CLK_ATTR2; 572 pl_id = <0>; 573 ports { 574 #address-cells = <1>; 575 #size-cells = <0>; 576 port@0 { 577 reg = <0>; 578 dp_pl0_out0: endpoint { 579 remote-endpoint = <&lcd_in>; 580 }; 581 }; 582 }; 583 }; 584 585 pl1: pipeline@1 { 586 reg = <1>; 587 DPU_CLK_ATTR3; 588 pl_id = <1>; 589 ports { 590 #address-cells = <1>; 591 #size-cells = <0>; 592 port@0 { 593 reg = <0>; 594 }; 595 }; 596 }; 597 }; 598 599 /* 600 * L3 cache in the DSU is the Memory System Component (MSC) 601 * The MPAM registers are accessed through utility bus in the DSU 602 */ 603 dsu-msc0 { 604 compatible = "arm,mpam-msc"; 605 reg = <DSU_MPAM_ADDR 0x0 0x2000>; 606 }; 607 608 ete0 { 609 compatible = "arm,embedded-trace-extension"; 610 cpu = <&CPU0>; 611 }; 612 613 ete1 { 614 compatible = "arm,embedded-trace-extension"; 615 cpu = <&CPU1>; 616 }; 617 618 ete2 { 619 compatible = "arm,embedded-trace-extension"; 620 cpu = <&CPU2>; 621 }; 622 623 ete3 { 624 compatible = "arm,embedded-trace-extension"; 625 cpu = <&CPU3>; 626 }; 627 628 ete4 { 629 compatible = "arm,embedded-trace-extension"; 630 cpu = <&CPU4>; 631 }; 632 633 ete5 { 634 compatible = "arm,embedded-trace-extension"; 635 cpu = <&CPU5>; 636 }; 637 638 ete6 { 639 compatible = "arm,embedded-trace-extension"; 640 cpu = <&CPU6>; 641 }; 642 643 ete7 { 644 compatible = "arm,embedded-trace-extension"; 645 cpu = <&CPU7>; 646 }; 647 648 trbe { 649 compatible = "arm,trace-buffer-extension"; 650 interrupts = <GIC_PPI 2 IRQ_TYPE_LEVEL_LOW 0>; 651 }; 652 653 trusty { 654 #size-cells = <0x02>; 655 #address-cells = <0x02>; 656 ranges = <0x00>; 657 compatible = "android,trusty-v1"; 658 659 virtio { 660 compatible = "android,trusty-virtio-v1"; 661 }; 662 663 test { 664 compatible = "android,trusty-test-v1"; 665 }; 666 667 log { 668 compatible = "android,trusty-log-v1"; 669 }; 670 671 irq { 672 ipi-range = <0x08 0x0f 0x08>; 673 interrupt-ranges = <0x00 0x0f 0x00 0x10 0x1f 0x01 0x20 0x3f 0x02>; 674 interrupt-templates = <0x01 0x00 0x8001 0x01 0x01 0x04 0x8001 0x01 0x00 0x04>; 675 compatible = "android,trusty-irq-v1"; 676 }; 677 }; 678 679 /* used in U-boot, Linux doesn't care */ 680 arm_ffa { 681 compatible = "arm,ffa"; 682 method = "smc"; 683 }; 684}; 685