1/* 2 * Copyright (c) 2014-2025, Arm Limited and Contributors. All rights reserved. 3 * 4 * SPDX-License-Identifier: BSD-3-Clause 5 */ 6#include <arch.h> 7#include <asm_macros.S> 8#include <cpu_macros.S> 9#include <qemu_max.h> 10 11cpu_reset_prologue qemu_max 12 13func qemu_max_core_pwr_dwn 14 /* --------------------------------------------- 15 * Disable the Data Cache. 16 * --------------------------------------------- 17 */ 18 mrs x1, sctlr_el3 19 bic x1, x1, #SCTLR_C_BIT 20 msr sctlr_el3, x1 21 isb 22 23 /* --------------------------------------------- 24 * Flush L1 cache to L2. 25 * --------------------------------------------- 26 */ 27 mov x18, lr 28 mov x0, #DCCISW 29 bl dcsw_op_level1 30 mov lr, x18 31 ret 32endfunc qemu_max_core_pwr_dwn 33 34func qemu_max_cluster_pwr_dwn 35 /* --------------------------------------------- 36 * Disable the Data Cache. 37 * --------------------------------------------- 38 */ 39 mrs x1, sctlr_el3 40 bic x1, x1, #SCTLR_C_BIT 41 msr sctlr_el3, x1 42 isb 43 44 /* --------------------------------------------- 45 * Flush all caches to PoC. 46 * --------------------------------------------- 47 */ 48 mov x0, #DCCISW 49 b dcsw_op_all 50endfunc qemu_max_cluster_pwr_dwn 51 52cpu_reset_func_start qemu_max 53cpu_reset_func_end qemu_max 54 55 /* --------------------------------------------- 56 * This function provides cpu specific 57 * register information for crash reporting. 58 * It needs to return with x6 pointing to 59 * a list of register names in ascii and 60 * x8 - x15 having values of registers to be 61 * reported. 62 * --------------------------------------------- 63 */ 64.section .rodata.qemu_max_regs, "aS" 65qemu_max_regs: /* The ascii list of register names to be reported */ 66 .asciz "" /* no registers to report */ 67 68func qemu_max_cpu_reg_dump 69 adr x6, qemu_max_regs 70 ret 71endfunc qemu_max_cpu_reg_dump 72 73 74/* cpu_ops for QEMU MAX */ 75declare_cpu_ops qemu_max, QEMU_MAX_MIDR, qemu_max_reset_func, \ 76 qemu_max_core_pwr_dwn, \ 77 qemu_max_cluster_pwr_dwn 78