1/* 2 * Copyright (c) 2022-2025, Arm Limited. All rights reserved. 3 * 4 * SPDX-License-Identifier: BSD-3-Clause 5 */ 6 7#include <arch.h> 8#include <asm_macros.S> 9#include <common/bl_common.h> 10#include <cortex_x4.h> 11#include <cpu_macros.S> 12#include <plat_macros.S> 13#include "wa_cve_2022_23960_bhb_vector.S" 14 15/* Hardware handled coherency */ 16#if HW_ASSISTED_COHERENCY == 0 17#error "Cortex X4 must be compiled with HW_ASSISTED_COHERENCY enabled" 18#endif 19 20/* 64-bit only core */ 21#if CTX_INCLUDE_AARCH32_REGS == 1 22#error "Cortex X4 supports only AArch64. Compile with CTX_INCLUDE_AARCH32_REGS=0" 23#endif 24 25.global check_erratum_cortex_x4_2726228 26.global check_erratum_cortex_x4_3701758 27 28#if WORKAROUND_CVE_2022_23960 29 wa_cve_2022_23960_bhb_vector_table CORTEX_X4_BHB_LOOP_COUNT, cortex_x4 30#endif /* WORKAROUND_CVE_2022_23960 */ 31 32workaround_runtime_start cortex_x4, ERRATUM(2726228), ERRATA_X4_2726228, CORTEX_X4_MIDR 33workaround_runtime_end cortex_x4, ERRATUM(2726228) 34 35check_erratum_ls cortex_x4, ERRATUM(2726228), CPU_REV(0, 1) 36 37/* Disable hardware page aggregation. Enables mitigation for `CVE-2024-5660` */ 38workaround_reset_start cortex_x4, CVE(2024, 5660), WORKAROUND_CVE_2024_5660 39 sysreg_bit_set CORTEX_X4_CPUECTLR_EL1, BIT(46) 40workaround_reset_end cortex_x4, CVE(2024, 5660) 41 42check_erratum_ls cortex_x4, CVE(2024, 5660), CPU_REV(0, 2) 43 44workaround_runtime_start cortex_x4, ERRATUM(2740089), ERRATA_X4_2740089 45 /* dsb before isb of power down sequence */ 46 dsb sy 47workaround_runtime_end cortex_x4, ERRATUM(2740089) 48 49check_erratum_ls cortex_x4, ERRATUM(2740089), CPU_REV(0, 1) 50 51workaround_reset_start cortex_x4, ERRATUM(2763018), ERRATA_X4_2763018 52 sysreg_bit_set CORTEX_X4_CPUACTLR3_EL1, BIT(47) 53workaround_reset_end cortex_x4, ERRATUM(2763018) 54 55check_erratum_ls cortex_x4, ERRATUM(2763018), CPU_REV(0, 1) 56 57workaround_reset_start cortex_x4, ERRATUM(2816013), ERRATA_X4_2816013 58 mrs x1, id_aa64pfr1_el1 59 ubfx x2, x1, ID_AA64PFR1_EL1_MTE_SHIFT, #4 60 cbz x2, #1f 61 sysreg_bit_set CORTEX_X4_CPUACTLR5_EL1, BIT(14) 621: 63workaround_reset_end cortex_x4, ERRATUM(2816013) 64 65check_erratum_ls cortex_x4, ERRATUM(2816013), CPU_REV(0, 1) 66 67workaround_reset_start cortex_x4, ERRATUM(2897503), ERRATA_X4_2897503 68 sysreg_bit_set CORTEX_X4_CPUACTLR4_EL1, BIT(8) 69workaround_reset_end cortex_x4, ERRATUM(2897503) 70 71check_erratum_ls cortex_x4, ERRATUM(2897503), CPU_REV(0, 1) 72 73workaround_reset_start cortex_x4, ERRATUM(2923985), ERRATA_X4_2923985 74 sysreg_bit_set CORTEX_X4_CPUACTLR4_EL1, (BIT(11) | BIT(10)) 75workaround_reset_end cortex_x4, ERRATUM(2923985) 76 77check_erratum_ls cortex_x4, ERRATUM(2923985), CPU_REV(0, 1) 78 79workaround_reset_start cortex_x4, ERRATUM(2957258), ERRATA_X4_2957258 80 /* Add ISB before MRS reads of MPIDR_EL1/MIDR_EL1 */ 81 ldr x0, =0x1 82 msr S3_6_c15_c8_0, x0 /* msr CPUPSELR_EL3, X0 */ 83 ldr x0, =0xd5380000 84 msr S3_6_c15_c8_2, x0 /* msr CPUPOR_EL3, X0 */ 85 ldr x0, =0xFFFFFF40 86 msr S3_6_c15_c8_3,x0 /* msr CPUPMR_EL3, X0 */ 87 ldr x0, =0x000080010033f 88 msr S3_6_c15_c8_1, x0 /* msr CPUPCR_EL3, X0 */ 89 isb 90workaround_reset_end cortex_x4, ERRATUM(2957258) 91 92check_erratum_ls cortex_x4, ERRATUM(2957258), CPU_REV(0, 1) 93 94workaround_reset_start cortex_x4, ERRATUM(3076789), ERRATA_X4_3076789 95 sysreg_bit_set CORTEX_X4_CPUACTLR3_EL1, BIT(14) 96 sysreg_bit_set CORTEX_X4_CPUACTLR3_EL1, BIT(13) 97 sysreg_bit_set CORTEX_X4_CPUACTLR_EL1, BIT(52) 98workaround_reset_end cortex_x4, ERRATUM(3076789) 99 100check_erratum_ls cortex_x4, ERRATUM(3076789), CPU_REV(0, 1) 101 102workaround_reset_start cortex_x4, CVE(2022, 23960), WORKAROUND_CVE_2022_23960 103#if IMAGE_BL31 104 /* 105 * The Cortex X4 generic vectors are overridden to apply errata 106 * mitigation on exception entry from lower ELs. 107 */ 108 override_vector_table wa_cve_vbar_cortex_x4 109#endif /* IMAGE_BL31 */ 110workaround_reset_end cortex_x4, CVE(2022, 23960) 111 112check_erratum_chosen cortex_x4, CVE(2022, 23960), WORKAROUND_CVE_2022_23960 113 114workaround_reset_start cortex_x4, CVE(2024, 7881), WORKAROUND_CVE_2024_7881 115 /* --------------------------------- 116 * Sets BIT41 of CPUACTLR6_EL1 which 117 * disables L1 Data cache prefetcher 118 * --------------------------------- 119 */ 120 sysreg_bit_set CORTEX_X4_CPUACTLR6_EL1, BIT(41) 121workaround_reset_end cortex_x4, CVE(2024, 7881) 122 123check_erratum_chosen cortex_x4, CVE(2024, 7881), WORKAROUND_CVE_2024_7881 124 125add_erratum_entry cortex_x4, ERRATUM(3701758), ERRATA_X4_3701758, NO_APPLY_AT_RESET 126 127check_erratum_ls cortex_x4, ERRATUM(3701758), CPU_REV(0, 3) 128 129cpu_reset_func_start cortex_x4 130 /* Disable speculative loads */ 131 msr SSBS, xzr 132cpu_reset_func_end cortex_x4 133 134 /* ---------------------------------------------------- 135 * HW will do the cache maintenance while powering down 136 * ---------------------------------------------------- 137 */ 138func cortex_x4_core_pwr_dwn 139 /* --------------------------------------------------- 140 * Enable CPU power down bit in power control register 141 * --------------------------------------------------- 142 */ 143 sysreg_bit_set CORTEX_X4_CPUPWRCTLR_EL1, CORTEX_X4_CPUPWRCTLR_EL1_CORE_PWRDN_BIT 144 145 apply_erratum cortex_x4, ERRATUM(2740089), ERRATA_X4_2740089, NO_GET_CPU_REV 146 147 isb 148 ret 149endfunc cortex_x4_core_pwr_dwn 150 151 /* --------------------------------------------- 152 * This function provides Cortex X4-specific 153 * register information for crash reporting. 154 * It needs to return with x6 pointing to 155 * a list of register names in ascii and 156 * x8 - x15 having values of registers to be 157 * reported. 158 * --------------------------------------------- 159 */ 160.section .rodata.cortex_x4_regs, "aS" 161cortex_x4_regs: /* The ascii list of register names to be reported */ 162 .asciz "cpuectlr_el1", "" 163 164func cortex_x4_cpu_reg_dump 165 adr x6, cortex_x4_regs 166 mrs x8, CORTEX_X4_CPUECTLR_EL1 167 ret 168endfunc cortex_x4_cpu_reg_dump 169 170declare_cpu_ops_wa_4 cortex_x4, CORTEX_X4_MIDR, \ 171 cortex_x4_reset_func, \ 172 CPU_NO_EXTRA1_FUNC, \ 173 CPU_NO_EXTRA2_FUNC, \ 174 CPU_NO_EXTRA3_FUNC, \ 175 check_erratum_cortex_x4_7881, \ 176 cortex_x4_core_pwr_dwn 177