1/* 2 * Copyright (c) 2019-2025, Arm Limited. All rights reserved. 3 * 4 * SPDX-License-Identifier: BSD-3-Clause 5 */ 6 7#include <arch.h> 8#include <asm_macros.S> 9#include <common/bl_common.h> 10#include <cortex_a78.h> 11#include <cpu_macros.S> 12#include <plat_macros.S> 13#include "wa_cve_2022_23960_bhb_vector.S" 14 15/* Hardware handled coherency */ 16#if HW_ASSISTED_COHERENCY == 0 17#error "cortex_a78 must be compiled with HW_ASSISTED_COHERENCY enabled" 18#endif 19 20.globl cortex_a78_reset_func 21.globl cortex_a78_core_pwr_dwn 22 23#if WORKAROUND_CVE_2022_23960 24 wa_cve_2022_23960_bhb_vector_table CORTEX_A78_BHB_LOOP_COUNT, cortex_a78 25#endif /* WORKAROUND_CVE_2022_23960 */ 26 27cpu_reset_prologue cortex_a78 28 29workaround_reset_start cortex_a78, ERRATUM(1688305), ERRATA_A78_1688305 30 sysreg_bit_set CORTEX_A78_ACTLR2_EL1, CORTEX_A78_ACTLR2_EL1_BIT_1 31workaround_reset_end cortex_a78, ERRATUM(1688305) 32 33check_erratum_ls cortex_a78, ERRATUM(1688305), CPU_REV(1, 0) 34 35workaround_reset_start cortex_a78, ERRATUM(1821534), ERRATA_A78_1821534 36 sysreg_bit_set CORTEX_A78_ACTLR2_EL1, CORTEX_A78_ACTLR2_EL1_BIT_2 37workaround_reset_end cortex_a78, ERRATUM(1821534) 38 39check_erratum_ls cortex_a78, ERRATUM(1821534), CPU_REV(1, 0) 40 41workaround_reset_start cortex_a78, ERRATUM(1941498), ERRATA_A78_1941498 42 sysreg_bit_set CORTEX_A78_CPUECTLR_EL1, CORTEX_A78_CPUECTLR_EL1_BIT_8 43workaround_reset_end cortex_a78, ERRATUM(1941498) 44 45check_erratum_ls cortex_a78, ERRATUM(1941498), CPU_REV(1, 1) 46 47workaround_reset_start cortex_a78, ERRATUM(1951500), ERRATA_A78_1951500 48 msr S3_6_c15_c8_0, xzr 49 ldr x0, =0x10E3900002 50 msr S3_6_c15_c8_2, x0 51 ldr x0, =0x10FFF00083 52 msr S3_6_c15_c8_3, x0 53 ldr x0, =0x2001003FF 54 msr S3_6_c15_c8_1, x0 55 56 mov x0, #1 57 msr S3_6_c15_c8_0, x0 58 ldr x0, =0x10E3800082 59 msr S3_6_c15_c8_2, x0 60 ldr x0, =0x10FFF00083 61 msr S3_6_c15_c8_3, x0 62 ldr x0, =0x2001003FF 63 msr S3_6_c15_c8_1, x0 64 65 mov x0, #2 66 msr S3_6_c15_c8_0, x0 67 ldr x0, =0x10E3800200 68 msr S3_6_c15_c8_2, x0 69 ldr x0, =0x10FFF003E0 70 msr S3_6_c15_c8_3, x0 71 ldr x0, =0x2001003FF 72 msr S3_6_c15_c8_1, x0 73workaround_reset_end cortex_a78, ERRATUM(1951500) 74 75check_erratum_range cortex_a78, ERRATUM(1951500), CPU_REV(1, 0), CPU_REV(1, 1) 76 77workaround_reset_start cortex_a78, ERRATUM(1952683), ERRATA_A78_1952683 78 ldr x0,=0x5 79 msr S3_6_c15_c8_0,x0 80 ldr x0,=0xEEE10A10 81 msr S3_6_c15_c8_2,x0 82 ldr x0,=0xFFEF0FFF 83 msr S3_6_c15_c8_3,x0 84 ldr x0,=0x0010F000 85 msr S3_6_c15_c8_4,x0 86 ldr x0,=0x0010F000 87 msr S3_6_c15_c8_5,x0 88 ldr x0,=0x40000080023ff 89 msr S3_6_c15_c8_1,x0 90 ldr x0,=0x6 91 msr S3_6_c15_c8_0,x0 92 ldr x0,=0xEE640F34 93 msr S3_6_c15_c8_2,x0 94 ldr x0,=0xFFEF0FFF 95 msr S3_6_c15_c8_3,x0 96 ldr x0,=0x40000080023ff 97 msr S3_6_c15_c8_1,x0 98workaround_reset_end cortex_a78, ERRATUM(1952683) 99 100check_erratum_ls cortex_a78, ERRATUM(1952683), CPU_REV(0, 0) 101 102workaround_reset_start cortex_a78, ERRATUM(2242635), ERRATA_A78_2242635 103 ldr x0, =0x5 104 msr S3_6_c15_c8_0, x0 /* CPUPSELR_EL3 */ 105 ldr x0, =0x10F600E000 106 msr S3_6_c15_c8_2, x0 /* CPUPOR_EL3 */ 107 ldr x0, =0x10FF80E000 108 msr S3_6_c15_c8_3, x0 /* CPUPMR_EL3 */ 109 ldr x0, =0x80000000003FF 110 msr S3_6_c15_c8_1, x0 /* CPUPCR_EL3 */ 111workaround_reset_end cortex_a78, ERRATUM(2242635) 112 113check_erratum_range cortex_a78, ERRATUM(2242635), CPU_REV(1, 0), CPU_REV(1, 2) 114 115workaround_reset_start cortex_a78, ERRATUM(2376745), ERRATA_A78_2376745 116 sysreg_bit_set CORTEX_A78_ACTLR2_EL1, BIT(0) 117workaround_reset_end cortex_a78, ERRATUM(2376745) 118 119check_erratum_ls cortex_a78, ERRATUM(2376745), CPU_REV(1, 2) 120 121workaround_reset_start cortex_a78, ERRATUM(2395406), ERRATA_A78_2395406 122 sysreg_bit_set CORTEX_A78_ACTLR2_EL1, BIT(40) 123workaround_reset_end cortex_a78, ERRATUM(2395406) 124 125check_erratum_ls cortex_a78, ERRATUM(2395406), CPU_REV(1, 2) 126 127workaround_reset_start cortex_a78, ERRATUM(2742426), ERRATA_A78_2742426 128 /* Apply the workaround */ 129 mrs x1, CORTEX_A78_ACTLR5_EL1 130 bic x1, x1, #BIT(56) 131 orr x1, x1, #BIT(55) 132 msr CORTEX_A78_ACTLR5_EL1, x1 133workaround_reset_end cortex_a78, ERRATUM(2742426) 134 135check_erratum_ls cortex_a78, ERRATUM(2742426), CPU_REV(1, 2) 136 137workaround_runtime_start cortex_a78, ERRATUM(2772019), ERRATA_A78_2772019 138 /* dsb before isb of power down sequence */ 139 dsb sy 140workaround_runtime_end cortex_a78, ERRATUM(2772019) 141 142check_erratum_ls cortex_a78, ERRATUM(2772019), CPU_REV(1, 2) 143 144workaround_reset_start cortex_a78, ERRATUM(2779479), ERRATA_A78_2779479 145 sysreg_bit_set CORTEX_A78_ACTLR3_EL1, BIT(47) 146workaround_reset_end cortex_a78, ERRATUM(2779479) 147 148check_erratum_ls cortex_a78, ERRATUM(2779479), CPU_REV(1, 2) 149 150workaround_reset_start cortex_a78, CVE(2022, 23960), WORKAROUND_CVE_2022_23960 151#if IMAGE_BL31 152 /* 153 * The Cortex-X1 generic vectors are overridden to apply errata 154 * mitigation on exception entry from lower ELs. 155 */ 156 override_vector_table wa_cve_vbar_cortex_a78 157#endif /* IMAGE_BL31 */ 158workaround_reset_end cortex_a78, CVE(2022, 23960) 159 160check_erratum_chosen cortex_a78, CVE(2022, 23960), WORKAROUND_CVE_2022_23960 161 162/* Disable hardware page aggregation.Enables mitigation for `CVE-2024-5660` */ 163workaround_reset_start cortex_a78, CVE(2024, 5660), WORKAROUND_CVE_2024_5660 164 sysreg_bit_set CORTEX_A78_CPUECTLR_EL1, BIT(46) 165workaround_reset_end cortex_a78, CVE(2024, 5660) 166 167check_erratum_ls cortex_a78, CVE(2024, 5660), CPU_REV(1, 2) 168 169cpu_reset_func_start cortex_a78 170#if ENABLE_FEAT_AMU 171 /* Make sure accesses from EL0/EL1 and EL2 are not trapped to EL3 */ 172 sysreg_bit_clear actlr_el3, CORTEX_A78_ACTLR_TAM_BIT 173 174 /* Make sure accesses from non-secure EL0/EL1 are not trapped to EL2 */ 175 sysreg_bit_clear actlr_el2, CORTEX_A78_ACTLR_TAM_BIT 176 177 /* Enable group0 counters */ 178 mov x0, #CORTEX_A78_AMU_GROUP0_MASK 179 msr CPUAMCNTENSET0_EL0, x0 180 181 /* Enable group1 counters */ 182 mov x0, #CORTEX_A78_AMU_GROUP1_MASK 183 msr CPUAMCNTENSET1_EL0, x0 184#endif 185cpu_reset_func_end cortex_a78 186 187 /* --------------------------------------------- 188 * HW will do the cache maintenance while powering down 189 * --------------------------------------------- 190 */ 191func cortex_a78_core_pwr_dwn 192 sysreg_bit_set CORTEX_A78_CPUPWRCTLR_EL1, CORTEX_A78_CPUPWRCTLR_EL1_CORE_PWRDN_EN_BIT 193 194 apply_erratum cortex_a78, ERRATUM(2772019), ERRATA_A78_2772019, NO_GET_CPU_REV 195 196 isb 197 ret 198endfunc cortex_a78_core_pwr_dwn 199 200 /* --------------------------------------------- 201 * This function provides cortex_a78 specific 202 * register information for crash reporting. 203 * It needs to return with x6 pointing to 204 * a list of register names in ascii and 205 * x8 - x15 having values of registers to be 206 * reported. 207 * --------------------------------------------- 208 */ 209.section .rodata.cortex_a78_regs, "aS" 210cortex_a78_regs: /* The ascii list of register names to be reported */ 211 .asciz "cpuectlr_el1", "" 212 213func cortex_a78_cpu_reg_dump 214 adr x6, cortex_a78_regs 215 mrs x8, CORTEX_A78_CPUECTLR_EL1 216 ret 217endfunc cortex_a78_cpu_reg_dump 218 219declare_cpu_ops cortex_a78, CORTEX_A78_MIDR, \ 220 cortex_a78_reset_func, \ 221 cortex_a78_core_pwr_dwn 222