1/* 2 * Copyright (c) 2020-2025, Arm Limited. All rights reserved. 3 * 4 * SPDX-License-Identifier: BSD-3-Clause 5 */ 6 7#include <arch.h> 8#include <asm_macros.S> 9#include <cpu_macros.S> 10#include <dsu_macros.S> 11#include <neoverse_n2.h> 12#include "wa_cve_2022_23960_bhb_vector.S" 13 14/* Hardware handled coherency */ 15#if HW_ASSISTED_COHERENCY == 0 16#error "Neoverse N2 must be compiled with HW_ASSISTED_COHERENCY enabled" 17#endif 18 19/* 64-bit only core */ 20#if CTX_INCLUDE_AARCH32_REGS == 1 21#error "Neoverse-N2 supports only AArch64. Compile with CTX_INCLUDE_AARCH32_REGS=0" 22#endif 23 24.global check_erratum_neoverse_n2_3701773 25 26add_erratum_entry neoverse_n2, ERRATUM(3701773), ERRATA_N2_3701773, NO_APPLY_AT_RESET 27 28check_erratum_ls neoverse_n2, ERRATUM(3701773), CPU_REV(0, 3) 29 30#if WORKAROUND_CVE_2022_23960 31 wa_cve_2022_23960_bhb_vector_table NEOVERSE_N2_BHB_LOOP_COUNT, neoverse_n2 32#endif /* WORKAROUND_CVE_2022_23960 */ 33 34workaround_reset_start neoverse_n2, ERRATUM(2313941), ERRATA_DSU_2313941 35 errata_dsu_2313941_wa_impl 36workaround_reset_end neoverse_n2, ERRATUM(2313941) 37 38check_erratum_custom_start neoverse_n2, ERRATUM(2313941) 39 branch_if_scu_not_present 2f /* label 1 is used in the macro */ 40 check_errata_dsu_2313941_impl 41 2: 42 ret 43check_erratum_custom_end neoverse_n2, ERRATUM(2313941) 44 45/* Disable hardware page aggregation. Enables mitigation for `CVE-2024-5660` */ 46workaround_reset_start neoverse_n2, CVE(2024, 5660), WORKAROUND_CVE_2024_5660 47 sysreg_bit_set NEOVERSE_N2_CPUECTLR_EL1, BIT(46) 48workaround_reset_end neoverse_n2, CVE(2024, 5660) 49 50check_erratum_ls neoverse_n2, CVE(2024, 5660), CPU_REV(0, 3) 51 52workaround_reset_start neoverse_n2, ERRATUM(2002655), ERRATA_N2_2002655 53 /* Apply instruction patching sequence */ 54 ldr x0,=0x6 55 msr S3_6_c15_c8_0,x0 56 ldr x0,=0xF3A08002 57 msr S3_6_c15_c8_2,x0 58 ldr x0,=0xFFF0F7FE 59 msr S3_6_c15_c8_3,x0 60 ldr x0,=0x40000001003ff 61 msr S3_6_c15_c8_1,x0 62 ldr x0,=0x7 63 msr S3_6_c15_c8_0,x0 64 ldr x0,=0xBF200000 65 msr S3_6_c15_c8_2,x0 66 ldr x0,=0xFFEF0000 67 msr S3_6_c15_c8_3,x0 68 ldr x0,=0x40000001003f3 69 msr S3_6_c15_c8_1,x0 70workaround_reset_end neoverse_n2, ERRATUM(2002655) 71 72check_erratum_ls neoverse_n2, ERRATUM(2002655), CPU_REV(0, 0) 73 74workaround_reset_start neoverse_n2, ERRATUM(2025414), ERRATA_N2_2025414 75 sysreg_bit_set NEOVERSE_N2_CPUECTLR_EL1, NEOVERSE_N2_CPUECTLR_EL1_PFSTIDIS_BIT 76workaround_reset_end neoverse_n2, ERRATUM(2025414) 77 78check_erratum_ls neoverse_n2, ERRATUM(2025414), CPU_REV(0, 0) 79 80workaround_reset_start neoverse_n2, ERRATUM(2067956), ERRATA_N2_2067956 81 sysreg_bit_set NEOVERSE_N2_CPUACTLR_EL1, NEOVERSE_N2_CPUACTLR_EL1_BIT_46 82workaround_reset_end neoverse_n2, ERRATUM(2067956) 83 84check_erratum_ls neoverse_n2, ERRATUM(2067956), CPU_REV(0, 0) 85 86workaround_runtime_start neoverse_n2, ERRATUM(2009478), ERRATA_N2_2009478 87 /* Stash ERRSELR_EL1 in x2 */ 88 mrs x2, ERRSELR_EL1 89 90 /* Select error record 0 and clear ED bit */ 91 msr ERRSELR_EL1, xzr 92 mrs x1, ERXCTLR_EL1 93 bfi x1, xzr, #ERXCTLR_ED_SHIFT, #1 94 msr ERXCTLR_EL1, x1 95 96 /* Restore ERRSELR_EL1 from x2 */ 97 msr ERRSELR_EL1, x2 98workaround_runtime_end neoverse_n2, ERRATUM(2009478), NO_ISB 99 100check_erratum_ls neoverse_n2, ERRATUM(2009478), CPU_REV(0, 0) 101 102workaround_reset_start neoverse_n2, ERRATUM(2138953), ERRATA_N2_2138953 103 /* Apply instruction patching sequence */ 104 mrs x1, NEOVERSE_N2_CPUECTLR2_EL1 105 mov x0, #NEOVERSE_N2_CPUECTLR2_EL1_PF_MODE_CNSRV 106 bfi x1, x0, #CPUECTLR2_EL1_PF_MODE_LSB, #CPUECTLR2_EL1_PF_MODE_WIDTH 107 msr NEOVERSE_N2_CPUECTLR2_EL1, x1 108workaround_reset_end neoverse_n2, ERRATUM(2138953) 109 110check_erratum_ls neoverse_n2, ERRATUM(2138953), CPU_REV(0, 3) 111 112workaround_reset_start neoverse_n2, ERRATUM(2138956), ERRATA_N2_2138956 113 /* Apply instruction patching sequence */ 114 ldr x0,=0x3 115 msr S3_6_c15_c8_0,x0 116 ldr x0,=0xF3A08002 117 msr S3_6_c15_c8_2,x0 118 ldr x0,=0xFFF0F7FE 119 msr S3_6_c15_c8_3,x0 120 ldr x0,=0x10002001003FF 121 msr S3_6_c15_c8_1,x0 122 ldr x0,=0x4 123 msr S3_6_c15_c8_0,x0 124 ldr x0,=0xBF200000 125 msr S3_6_c15_c8_2,x0 126 ldr x0,=0xFFEF0000 127 msr S3_6_c15_c8_3,x0 128 ldr x0,=0x10002001003F3 129 msr S3_6_c15_c8_1,x0 130workaround_reset_end neoverse_n2, ERRATUM(2138956) 131 132check_erratum_ls neoverse_n2, ERRATUM(2138956), CPU_REV(0, 0) 133 134 135workaround_reset_start neoverse_n2, ERRATUM(2138958), ERRATA_N2_2138958 136 /* Apply instruction patching sequence */ 137 sysreg_bit_set NEOVERSE_N2_CPUACTLR5_EL1, NEOVERSE_N2_CPUACTLR5_EL1_BIT_13 138workaround_reset_end neoverse_n2, ERRATUM(2138958) 139 140check_erratum_ls neoverse_n2, ERRATUM(2138958), CPU_REV(0, 0) 141 142workaround_reset_start neoverse_n2, ERRATUM(2189731), ERRATA_N2_2189731 143 sysreg_bit_set NEOVERSE_N2_CPUACTLR5_EL1, NEOVERSE_N2_CPUACTLR5_EL1_BIT_44 144workaround_reset_end neoverse_n2, ERRATUM(2189731) 145 146check_erratum_ls neoverse_n2, ERRATUM(2189731), CPU_REV(0, 0) 147 148workaround_reset_start neoverse_n2, ERRATUM(2242400), ERRATA_N2_2242400 149 /* Apply instruction patching sequence */ 150 sysreg_bit_set NEOVERSE_N2_CPUACTLR5_EL1, NEOVERSE_N2_CPUACTLR5_EL1_BIT_17 151 ldr x0, =0x2 152 msr S3_6_c15_c8_0, x0 153 ldr x0, =0x10F600E000 154 msr S3_6_c15_c8_2, x0 155 ldr x0, =0x10FF80E000 156 msr S3_6_c15_c8_3, x0 157 ldr x0, =0x80000000003FF 158 msr S3_6_c15_c8_1, x0 159workaround_reset_end neoverse_n2, ERRATUM(2242400) 160 161check_erratum_ls neoverse_n2, ERRATUM(2242400), CPU_REV(0, 0) 162 163workaround_reset_start neoverse_n2, ERRATUM(2242415), ERRATA_N2_2242415 164 sysreg_bit_set NEOVERSE_N2_CPUACTLR_EL1, NEOVERSE_N2_CPUACTLR_EL1_BIT_22 165workaround_reset_end neoverse_n2, ERRATUM(2242415) 166 167check_erratum_ls neoverse_n2, ERRATUM(2242415), CPU_REV(0, 0) 168 169workaround_reset_start neoverse_n2, ERRATUM(2280757), ERRATA_N2_2280757 170 /* Apply instruction patching sequence */ 171 sysreg_bit_set NEOVERSE_N2_CPUACTLR_EL1, NEOVERSE_N2_CPUACTLR_EL1_BIT_22 172workaround_reset_end neoverse_n2, ERRATUM(2280757) 173 174check_erratum_ls neoverse_n2, ERRATUM(2280757), CPU_REV(0, 0) 175 176.global erratum_neoverse_n2_2326639_wa 177workaround_runtime_start neoverse_n2, ERRATUM(2326639), ERRATA_N2_2326639 178 /* Set/unset bit 36 in ACTLR2_EL1. The first call will set it, applying 179 * the workaround. Second call clears it to undo it. */ 180 sysreg_bit_toggle NEOVERSE_N2_CPUACTLR2_EL1, NEOVERSE_N2_CPUACTLR2_EL1_BIT_36 181workaround_runtime_end neoverse_n2, ERRATUM(2326639) 182 183check_erratum_ls neoverse_n2, ERRATUM(2326639), CPU_REV(0, 0) 184 185workaround_reset_start neoverse_n2, ERRATUM(2340933), ERRATA_N2_2340933 186 /* Set bit 61 in CPUACTLR5_EL1 */ 187 sysreg_bit_set NEOVERSE_N2_CPUACTLR5_EL1, BIT(61) 188workaround_reset_end neoverse_n2, ERRATUM(2340933) 189 190check_erratum_ls neoverse_n2, ERRATUM(2340933), CPU_REV(0, 0) 191 192workaround_reset_start neoverse_n2, ERRATUM(2346952), ERRATA_N2_2346952 193 /* Set TXREQ to STATIC and full L2 TQ size */ 194 mrs x1, NEOVERSE_N2_CPUECTLR2_EL1 195 mov x0, #CPUECTLR2_EL1_TXREQ_STATIC_FULL 196 bfi x1, x0, #CPUECTLR2_EL1_TXREQ_LSB, #CPUECTLR2_EL1_TXREQ_WIDTH 197 msr NEOVERSE_N2_CPUECTLR2_EL1, x1 198workaround_reset_end neoverse_n2, ERRATUM(2346952) 199 200check_erratum_ls neoverse_n2, ERRATUM(2346952), CPU_REV(0, 2) 201 202workaround_reset_start neoverse_n2, ERRATUM(2376738), ERRATA_N2_2376738 203 /* Set CPUACTLR2_EL1[0] to 1 to force PLDW/PFRM 204 * ST to behave like PLD/PFRM LD and not cause 205 * invalidations to other PE caches. 206 */ 207 sysreg_bit_set NEOVERSE_N2_CPUACTLR2_EL1, NEOVERSE_N2_CPUACTLR2_EL1_BIT_0 208workaround_reset_end neoverse_n2, ERRATUM(2376738) 209 210check_erratum_ls neoverse_n2, ERRATUM(2376738), CPU_REV(0, 3) 211 212workaround_reset_start neoverse_n2, ERRATUM(2388450), ERRATA_N2_2388450 213 /*Set bit 40 in ACTLR2_EL1 */ 214 sysreg_bit_set NEOVERSE_N2_CPUACTLR2_EL1, NEOVERSE_N2_CPUACTLR2_EL1_BIT_40 215workaround_reset_end neoverse_n2, ERRATUM(2388450) 216 217check_erratum_ls neoverse_n2, ERRATUM(2388450), CPU_REV(0, 0) 218 219workaround_reset_start neoverse_n2, ERRATUM(2743014), ERRATA_N2_2743014 220 /* Set CPUACTLR5_EL1[56:55] to 2'b01 */ 221 sysreg_bit_set NEOVERSE_N2_CPUACTLR5_EL1, NEOVERSE_N2_CPUACTLR5_EL1_BIT_55 222 sysreg_bit_clear NEOVERSE_N2_CPUACTLR5_EL1, NEOVERSE_N2_CPUACTLR5_EL1_BIT_56 223workaround_reset_end neoverse_n2, ERRATUM(2743014) 224 225check_erratum_ls neoverse_n2, ERRATUM(2743014), CPU_REV(0, 2) 226 227workaround_runtime_start neoverse_n2, ERRATUM(2743089), ERRATA_N2_2743089 228 /* dsb before isb of power down sequence */ 229 dsb sy 230workaround_runtime_end neoverse_n2, ERRATUM(2743089) 231 232check_erratum_ls neoverse_n2, ERRATUM(2743089), CPU_REV(0, 2) 233 234workaround_reset_start neoverse_n2, ERRATUM(2779511), ERRATA_N2_2779511 235 /* Set bit 47 in ACTLR3_EL1 */ 236 sysreg_bit_set NEOVERSE_N2_CPUACTLR3_EL1, NEOVERSE_N2_CPUACTLR3_EL1_BIT_47 237workaround_reset_end neoverse_n2, ERRATUM(2779511) 238 239check_erratum_ls neoverse_n2, ERRATUM(2779511), CPU_REV(0, 2) 240 241workaround_reset_start neoverse_n2, CVE(2022,23960), WORKAROUND_CVE_2022_23960 242#if IMAGE_BL31 243 /* 244 * The Neoverse-N2 generic vectors are overridden to apply errata 245 * mitigation on exception entry from lower ELs. 246 */ 247 override_vector_table wa_cve_vbar_neoverse_n2 248#endif /* IMAGE_BL31 */ 249workaround_reset_end neoverse_n2, CVE(2022,23960) 250 251check_erratum_chosen neoverse_n2, CVE(2022, 23960), WORKAROUND_CVE_2022_23960 252 253 /* ------------------------------------------- 254 * The CPU Ops reset function for Neoverse N2. 255 * ------------------------------------------- 256 */ 257cpu_reset_func_start neoverse_n2 258 259 /* Check if the PE implements SSBS */ 260 mrs x0, id_aa64pfr1_el1 261 tst x0, #(ID_AA64PFR1_EL1_SSBS_MASK << ID_AA64PFR1_EL1_SSBS_SHIFT) 262 b.eq 1f 263 264 /* Disable speculative loads */ 265 msr SSBS, xzr 2661: 267 /* Force all cacheable atomic instructions to be near */ 268 sysreg_bit_set NEOVERSE_N2_CPUACTLR2_EL1, NEOVERSE_N2_CPUACTLR2_EL1_BIT_2 269 270#if ENABLE_FEAT_AMU 271 /* Make sure accesses from EL0/EL1 and EL2 are not trapped to EL3 */ 272 sysreg_bit_clear cptr_el3, TAM_BIT 273 /* Make sure accesses from EL0/EL1 are not trapped to EL2 */ 274 sysreg_bit_clear cptr_el2, TAM_BIT 275 /* No need to enable the counters as this would be done at el3 exit */ 276#endif 277 278#if NEOVERSE_Nx_EXTERNAL_LLC 279 /* Some systems may have External LLC, core needs to be made aware */ 280 sysreg_bit_set NEOVERSE_N2_CPUECTLR_EL1, NEOVERSE_N2_CPUECTLR_EL1_EXTLLC_BIT 281#endif 282cpu_reset_func_end neoverse_n2 283 284func neoverse_n2_core_pwr_dwn 285 apply_erratum neoverse_n2, ERRATUM(2009478), ERRATA_N2_2009478, NO_GET_CPU_REV 286 apply_erratum neoverse_n2, ERRATUM(2326639), ERRATA_N2_2326639, NO_GET_CPU_REV 287 288 /* --------------------------------------------------- 289 * Enable CPU power down bit in power control register 290 * No need to do cache maintenance here. 291 * --------------------------------------------------- 292 */ 293 sysreg_bit_set NEOVERSE_N2_CPUPWRCTLR_EL1, NEOVERSE_N2_CORE_PWRDN_EN_BIT 294 295 apply_erratum neoverse_n2, ERRATUM(2743089), ERRATA_N2_2743089, NO_GET_CPU_REV 296 297 isb 298 ret 299endfunc neoverse_n2_core_pwr_dwn 300 301 /* --------------------------------------------- 302 * This function provides Neoverse N2 specific 303 * register information for crash reporting. 304 * It needs to return with x6 pointing to 305 * a list of register names in ASCII and 306 * x8 - x15 having values of registers to be 307 * reported. 308 * --------------------------------------------- 309 */ 310.section .rodata.neoverse_n2_regs, "aS" 311neoverse_n2_regs: /* The ASCII list of register names to be reported */ 312 .asciz "cpupwrctlr_el1", "" 313 314func neoverse_n2_cpu_reg_dump 315 adr x6, neoverse_n2_regs 316 mrs x8, NEOVERSE_N2_CPUPWRCTLR_EL1 317 ret 318endfunc neoverse_n2_cpu_reg_dump 319 320declare_cpu_ops neoverse_n2, NEOVERSE_N2_MIDR, \ 321 neoverse_n2_reset_func, \ 322 neoverse_n2_core_pwr_dwn 323