1 /* 2 * Copyright (c) 2015-2024, ARM Limited and Contributors. All rights reserved. 3 * 4 * Copyright (C) 2017-2023 Nuvoton Ltd. 5 * 6 * SPDX-License-Identifier: BSD-3-Clause 7 */ 8 9 #ifndef NPCM845x_ARM_DEF_H 10 #define NPCM845x_ARM_DEF_H 11 12 #include <arch.h> 13 #include <common/interrupt_props.h> 14 #include <common/tbbr/tbbr_img_def.h> 15 #include <drivers/arm/gic_common.h> 16 #include <lib/utils_def.h> 17 #include <lib/xlat_tables/xlat_tables_defs.h> 18 #include <plat/arm/common/smccc_def.h> 19 #include <plat/common/common_def.h> 20 21 /* This flag will add zones to the MMU so that it will be possible to debug */ 22 #ifdef NPCM845X_DEBUG 23 #define ALLOW_DEBUG_MMU 24 #undef ALLOW_DEBUG_MMU 25 #endif /* NPCM845X_DEBUG */ 26 27 #undef CONFIG_TARGET_ARBEL_PALLADIUM 28 /****************************************************************************** 29 * Definitions common to all ARM standard platforms 30 *****************************************************************************/ 31 32 /* 33 * Length of the header for a hashed DER ROTPK. 34 */ 35 #define ARM_ROTPK_HASH_DER_HEADER_LEN 19 36 37 /* Special value used to verify platform parameters from BL2 to BL31 */ 38 #define ARM_BL31_PLAT_PARAM_VAL ULL(0x0f1e2d3c4b5a6978) 39 40 /* No need for system because we have only one cluster */ 41 #define ARM_SYSTEM_COUNT U(0) 42 43 #define ARM_CACHE_WRITEBACK_SHIFT 6 44 45 /* 46 * Macros mapping the MPIDR Affinity levels to ARM Platform Power levels. 47 * The power levels have a 1:1 mapping with the MPIDR affinity levels. 48 */ 49 /* In NPCM845x - refers to cores */ 50 #define ARM_PWR_LVL0 MPIDR_AFFLVL0 51 52 /* In NPCM845x - refers to cluster */ 53 #define ARM_PWR_LVL1 MPIDR_AFFLVL1 54 55 /* No need for additional settings because the platform doesn't have system */ 56 57 /* 58 * Macros for local power states in ARM platforms encoded by State-ID field 59 * within the power-state parameter. 60 */ 61 #define NPCM845x_PLAT_PRIMARY_CPU U(0x0) 62 #define NPCM845x_CLUSTER_COUNT U(1) 63 64 #ifdef SECONDARY_BRINGUP 65 #define NPCM845x_MAX_CPU_PER_CLUSTER U(2) 66 #define NPCM845x_PLATFORM_CORE_COUNT U(2) 67 #define NPCM845x_PLATFORM_CLUSTER0_CORE_COUNT U(2) 68 #else 69 #define NPCM845x_MAX_CPU_PER_CLUSTER U(4) 70 #define NPCM845x_PLATFORM_CORE_COUNT U(4) 71 #define NPCM845x_PLATFORM_CLUSTER0_CORE_COUNT U(4) 72 #endif /* SECONDARY_BRINGUP */ 73 74 #define NPCM845x_SYSTEM_COUNT U(0) 75 76 /* Memory mapping for NPCM845x */ 77 #define NPCM845x_REG_BASE 0xf0000000 78 #define NPCM845x_REG_SIZE 0x0ff16000 79 80 /* 81 * DRAM 82 * 0x3fffffff +-------------+ 83 * | BL33 | (non-secure) 84 * 0x06200000 +-------------+ 85 * | BL32 SHARED | (non-secure) 86 * 0x06000000 +-------------+ 87 * | BL32 | (secure) 88 * 0x02100000 +-------------+ 89 * | BL31 | (secure) 90 * 0x02000000 +-------------+ 91 * | | (non-secure) 92 * 0x00000000 +-------------+ 93 * 94 * Trusted ROM 95 * 0xfff50000 +-------------+ 96 * | BL1 (ro) | 97 * 0xfff40000 +-------------+ 98 */ 99 100 #define ARM_DRAM1_BASE ULL(0x00000000) 101 #ifndef CONFIG_TARGET_ARBEL_PALLADIUM 102 /* 103 * Although npcm845x is 4G, 104 * consider only 2G Trusted Firmware memory allocation 105 */ 106 #define ARM_DRAM1_SIZE ULL(0x37000000) 107 #else 108 #define ARM_DRAM1_SIZE ULL(0x10000000) 109 #define ARM_DRAM1_END (ARM_DRAM1_BASE + ARM_DRAM1_SIZE - 1U) 110 #endif /* CONFIG_TARGET_ARBEL_PALLADIUM */ 111 112 /* 113 * The top 16MB of DRAM1 is configured as secure access only using the TZC 114 * - SCP TZC DRAM: If present, DRAM reserved for SCP use 115 * - AP TZC DRAM: The remaining TZC secured DRAM reserved for AP use 116 */ 117 118 /* Check for redundancy */ 119 #ifdef NPCM845X_DEBUG 120 #define PLAT_ARM_NS_IMAGE_BASE 0x0 121 #endif /* NPCM845X_DEBUG */ 122 123 #define ARM_TZC_DRAM1_SIZE UL(0x01000000) 124 #define ARM_SCP_TZC_DRAM1_SIZE PLAT_ARM_SCP_TZC_DRAM1_SIZE 125 #define ARM_SCP_TZC_DRAM1_END (ARM_SCP_TZC_DRAM1_BASE + \ 126 ARM_SCP_TZC_DRAM1_SIZE - 1U) 127 128 /* 129 * Define a 2MB region within the TZC secured DRAM for use by EL3 runtime 130 * firmware. This region is meant to be NOLOAD and will not be zero 131 * initialized. Data sections with the attribute `arm_el3_tzc_dram` 132 * will be placed here. 133 * 134 * NPCM845x - Currently the platform doesn't have EL3 implementation 135 * on secured DRAM. 136 */ 137 #define ARM_EL3_TZC_DRAM1_BASE (ARM_SCP_TZC_DRAM1_BASE - \ 138 ARM_EL3_TZC_DRAM1_SIZE) 139 #define ARM_EL3_TZC_DRAM1_SIZE UL(0x00200000) /* 2 MB */ 140 #define ARM_EL3_TZC_DRAM1_END (ARM_EL3_TZC_DRAM1_BASE + \ 141 ARM_EL3_TZC_DRAM1_SIZE - 1U) 142 143 #define ARM_AP_TZC_DRAM1_BASE 0x02100000 144 #define ARM_AP_TZC_DRAM1_SIZE (ARM_TZC_DRAM1_SIZE - \ 145 (ARM_SCP_TZC_DRAM1_SIZE + \ 146 ARM_EL3_TZC_DRAM1_SIZE)) 147 #define ARM_AP_TZC_DRAM1_END (ARM_AP_TZC_DRAM1_BASE + \ 148 ARM_AP_TZC_DRAM1_SIZE - 1U) 149 150 /* Define the Access permissions for Secure peripherals to NS_DRAM */ 151 #if ARM_CRYPTOCELL_INTEG 152 /* 153 * Allow Secure peripheral to read NS DRAM when integrated with CryptoCell. 154 * This is required by CryptoCell to authenticate BL33 which is loaded 155 * into the Non Secure DDR. 156 */ 157 #define ARM_TZC_NS_DRAM_S_ACCESS TZC_REGION_S_RD 158 #else 159 #define ARM_TZC_NS_DRAM_S_ACCESS TZC_REGION_S_NONE 160 #endif /* ARM_CRYPTOCELL_INTEG */ 161 162 #ifdef SPD_opteed 163 /* 164 * BL2 needs to map 4MB at the end of TZC_DRAM1 in order to 165 * load/authenticate the trusted os extra image. The first 512KB of 166 * TZC_DRAM1 are reserved for trusted os (OPTEE). The extra image loading 167 * for OPTEE is paged image which only include the paging part using 168 * virtual memory but without "init" data. OPTEE will copy the "init" data 169 * (from pager image) to the first 512KB of TZC_DRAM, and then copy the 170 * extra image behind the "init" data. 171 */ 172 #define TSP_SEC_MEM_BASE ARM_AP_TZC_DRAM1_BASE 173 #define TSP_SEC_MEM_SIZE ARM_AP_TZC_DRAM1_SIZE 174 #define BL32_BASE ARM_AP_TZC_DRAM1_BASE 175 #define BL32_LIMIT (ARM_AP_TZC_DRAM1_BASE + \ 176 ARM_AP_TZC_DRAM1_SIZE) 177 178 #define ARM_OPTEE_PAGEABLE_LOAD_BASE ( \ 179 ARM_AP_TZC_DRAM1_BASE + ARM_AP_TZC_DRAM1_SIZE - \ 180 ARM_OPTEE_PAGEABLE_LOAD_SIZE) 181 #define ARM_OPTEE_PAGEABLE_LOAD_SIZE UL(0x400000) 182 #define ARM_OPTEE_PAGEABLE_LOAD_MEM MAP_REGION_FLAT( \ 183 ARM_OPTEE_PAGEABLE_LOAD_BASE, \ 184 ARM_OPTEE_PAGEABLE_LOAD_SIZE, \ 185 MT_MEMORY | MT_RW | MT_SECURE) 186 187 /* 188 * Map the memory for the OP-TEE core (also known as OP-TEE pager 189 * when paging support is enabled). 190 */ 191 #define ARM_MAP_OPTEE_CORE_MEM MAP_REGION_FLAT( \ 192 BL32_BASE, BL32_LIMIT - BL32_BASE, \ 193 MT_MEMORY | MT_RW | MT_SECURE) 194 #endif /* SPD_opteed */ 195 196 #define ARM_NS_DRAM1_BASE ARM_DRAM1_BASE 197 #define ARM_NS_DRAM1_SIZE (ARM_DRAM1_SIZE - \ 198 ARM_TZC_DRAM1_SIZE) 199 #define ARM_NS_DRAM1_END (ARM_NS_DRAM1_BASE + \ 200 ARM_NS_DRAM1_SIZE - 1U) 201 202 /* The platform doesn't use DRAM2 but it has to have a value for calculation */ 203 #define ARM_DRAM2_BASE 0 /* PLAT_ARM_DRAM_BASE */ 204 #define ARM_DRAM2_SIZE 1 /* PLAT_ARM_DRAM_SIZE */ 205 #define ARM_DRAM2_END (ARM_DRAM2_BASE + ARM_DRAM2_SIZE - 1U) 206 207 #define FIRST_EXT_INTERRUPT_NUM U(32) 208 #define ARM_IRQ_SEC_PHY_TIMER (U(29) + FIRST_EXT_INTERRUPT_NUM) 209 210 #define ARM_IRQ_SEC_SGI_0 8 211 #define ARM_IRQ_SEC_SGI_1 9 212 #define ARM_IRQ_SEC_SGI_2 10 213 #define ARM_IRQ_SEC_SGI_3 11 214 #define ARM_IRQ_SEC_SGI_4 12 215 #define ARM_IRQ_SEC_SGI_5 13 216 #define ARM_IRQ_SEC_SGI_6 14 217 #define ARM_IRQ_SEC_SGI_7 15 218 219 /* 220 * Define a list of Group 1 Secure and Group 0 interrupt properties 221 * as per GICv3 terminology. On a GICv2 system or mode, 222 * the lists will be merged and treated as Group 0 interrupts. 223 */ 224 #define ARM_G1S_IRQ_PROPS(grp) \ 225 INTR_PROP_DESC(ARM_IRQ_SEC_PHY_TIMER, \ 226 GIC_HIGHEST_SEC_PRIORITY, (grp), GIC_INTR_CFG_LEVEL), \ 227 INTR_PROP_DESC(ARM_IRQ_SEC_SGI_1, \ 228 GIC_HIGHEST_SEC_PRIORITY, (grp), GIC_INTR_CFG_EDGE), \ 229 INTR_PROP_DESC(ARM_IRQ_SEC_SGI_2, \ 230 GIC_HIGHEST_SEC_PRIORITY, (grp), GIC_INTR_CFG_EDGE), \ 231 INTR_PROP_DESC(ARM_IRQ_SEC_SGI_3, \ 232 GIC_HIGHEST_SEC_PRIORITY, (grp), GIC_INTR_CFG_EDGE), \ 233 INTR_PROP_DESC(ARM_IRQ_SEC_SGI_4, \ 234 GIC_HIGHEST_SEC_PRIORITY, (grp), GIC_INTR_CFG_EDGE), \ 235 INTR_PROP_DESC(ARM_IRQ_SEC_SGI_5, \ 236 GIC_HIGHEST_SEC_PRIORITY, (grp), GIC_INTR_CFG_EDGE), \ 237 INTR_PROP_DESC(ARM_IRQ_SEC_SGI_7, \ 238 GIC_HIGHEST_SEC_PRIORITY, (grp), GIC_INTR_CFG_EDGE) 239 240 #define ARM_G0_IRQ_PROPS(grp) \ 241 INTR_PROP_DESC(ARM_IRQ_SEC_SGI_0, \ 242 PLAT_SDEI_NORMAL_PRI, (grp), GIC_INTR_CFG_EDGE), \ 243 INTR_PROP_DESC(ARM_IRQ_SEC_SGI_6, \ 244 GIC_HIGHEST_SEC_PRIORITY, (grp), GIC_INTR_CFG_EDGE) 245 246 #define ARM_MAP_SHARED_RAM MAP_REGION_FLAT( \ 247 ARM_SHARED_RAM_BASE, ARM_SHARED_RAM_SIZE, \ 248 MT_DEVICE | MT_RW | MT_SECURE) 249 250 #ifdef ALLOW_DEBUG_MMU 251 /* In order to be able to debug, 252 * the platform needs to add BL33 and BL32 to MMU as well. 253 */ 254 #define ARM_MAP_NS_DRAM1 MAP_REGION_FLAT( \ 255 ARM_NS_DRAM1_BASE, ARM_NS_DRAM1_SIZE, \ 256 MT_MEMORY | MT_RW | MT_NS) 257 258 #ifdef BL32_BASE 259 #define ARM_MAP_BL32_CORE_MEM MAP_REGION_FLAT( \ 260 BL32_BASE, BL32_LIMIT - BL32_BASE, \ 261 MT_MEMORY | MT_RW | MT_SECURE) 262 #endif /* BL32_BASE */ 263 264 #ifdef NPCM845X_DEBUG 265 #define ARM_MAP_SEC_BB_MEM MAP_REGION_FLAT( \ 266 0xFFFB0000, 0x20000, \ 267 MT_MEMORY | MT_RW | MT_NS) 268 #endif /* NPCM845X_DEBUG */ 269 #endif /* BL32_BASE */ 270 271 #define ARM_MAP_DRAM2 MAP_REGION_FLAT( \ 272 ARM_DRAM2_BASE, ARM_DRAM2_SIZE, \ 273 MT_MEMORY | MT_RW | MT_NS) 274 275 #define ARM_MAP_TSP_SEC_MEM MAP_REGION_FLAT( \ 276 TSP_SEC_MEM_BASE, TSP_SEC_MEM_SIZE, \ 277 MT_MEMORY | MT_RW | MT_SECURE) 278 279 #if ARM_BL31_IN_DRAM 280 #define ARM_MAP_BL31_SEC_DRAM MAP_REGION_FLAT( \ 281 BL31_BASE, PLAT_ARM_MAX_BL31_SIZE, \ 282 MT_MEMORY | MT_RW | MT_SECURE) 283 #endif /* ARM_BL31_IN_DRAM */ 284 285 /* Currently the platform doesn't have EL3 implementation on secured DRAM. */ 286 #define ARM_MAP_EL3_TZC_DRAM MAP_REGION_FLAT( \ 287 ARM_EL3_TZC_DRAM1_BASE, \ 288 ARM_EL3_TZC_DRAM1_SIZE, \ 289 MT_MEMORY | MT_RW | MT_SECURE) 290 291 #if defined(SPD_spmd) 292 #define ARM_MAP_TRUSTED_DRAM MAP_REGION_FLAT( \ 293 PLAT_ARM_TRUSTED_DRAM_BASE, \ 294 PLAT_ARM_TRUSTED_DRAM_SIZE, \ 295 MT_MEMORY | MT_RW | MT_SECURE) 296 #endif /* SPD_spmd */ 297 298 /* 299 * Mapping for the BL1 RW region. This mapping is needed by BL2 300 * in order to share the Mbed TLS heap. Since the heap is allocated 301 * inside BL1, it resides in the BL1 RW region. Hence, BL2 needs access 302 * to the BL1 RW region in order to be able to access the heap. 303 */ 304 #define ARM_MAP_BL1_RW MAP_REGION_FLAT( \ 305 BL1_RW_BASE, BL1_RW_LIMIT - BL1_RW_BASE, \ 306 MT_MEMORY | MT_RW | EL3_PAS) 307 308 /* 309 * If SEPARATE_CODE_AND_RODATA=1 the platform will define a region 310 * for each section, otherwise one region containing both sections 311 * is defined. 312 */ 313 #if SEPARATE_CODE_AND_RODATA 314 #define ARM_MAP_BL_RO MAP_REGION_FLAT( \ 315 BL_CODE_BASE, BL_CODE_END - BL_CODE_BASE, \ 316 MT_CODE | EL3_PAS), \ 317 MAP_REGION_FLAT(BL_RO_DATA_BASE, \ 318 BL_RO_DATA_END - BL_RO_DATA_BASE, \ 319 MT_RO_DATA | EL3_PAS) 320 #else 321 #define ARM_MAP_BL_RO_NOT_USED MAP_REGION_FLAT( \ 322 BL_CODE_BASE, BL_CODE_END - BL_CODE_BASE, \ 323 MT_CODE | EL3_PAS) 324 #endif /* SEPARATE_CODE_AND_RODATA */ 325 326 #if USE_COHERENT_MEM 327 #define ARM_MAP_BL_COHERENT_RAM MAP_REGION_FLAT( \ 328 BL_COHERENT_RAM_BASE, \ 329 BL_COHERENT_RAM_END - BL_COHERENT_RAM_BASE, \ 330 MT_DEVICE | MT_RW | EL3_PAS) 331 #endif /* USE_COHERENT_MEM */ 332 333 #if USE_ROMLIB 334 #define ARM_MAP_ROMLIB_CODE MAP_REGION_FLAT( \ 335 ROMLIB_RO_BASE, \ 336 ROMLIB_RO_LIMIT - ROMLIB_RO_BASE, \ 337 MT_CODE | MT_SECURE) 338 339 #define ARM_MAP_ROMLIB_DATA MAP_REGION_FLAT( \ 340 ROMLIB_RW_BASE, \ 341 ROMLIB_RW_END - ROMLIB_RW_BASE, \ 342 MT_MEMORY | MT_RW | MT_SECURE) 343 #endif /* USE_ROMLIB */ 344 345 /* 346 * Map mem_protect flash region with read and write permissions 347 */ 348 #define ARM_V2M_MAP_MEM_PROTECT MAP_REGION_FLAT( \ 349 PLAT_ARM_MEM_PROT_ADDR, \ 350 V2M_FLASH_BLOCK_SIZE, \ 351 MT_DEVICE | MT_RW | MT_SECURE) 352 /* 353 * Map the region for device tree configuration with read and write permissions 354 */ 355 #define ARM_MAP_BL_CONFIG_REGION MAP_REGION_FLAT( \ 356 ARM_BL_RAM_BASE, \ 357 (ARM_FW_CONFIGS_LIMIT - ARM_BL_RAM_BASE), \ 358 MT_MEMORY | MT_RW | MT_SECURE) 359 360 /* 361 * The max number of regions like RO(code), coherent and data required by 362 * different BL stages which need to be mapped in the MMU. 363 */ 364 #define ARM_BL_REGIONS 10 365 366 #define MAX_MMAP_REGIONS ( \ 367 PLAT_ARM_MMAP_ENTRIES + ARM_BL_REGIONS) 368 369 /* Memory mapped Generic timer interfaces */ 370 #define ARM_SYS_CNTCTL_BASE UL(0XF07FC000) 371 372 #define ARM_CONSOLE_BAUDRATE 115200 373 374 /* 375 * The TBBR document specifies a watchdog timeout of 256 seconds. SP805 376 * asserts reset after two consecutive countdowns (2 x 128 = 256 sec) 377 */ 378 #define ARM_TWDG_TIMEOUT_SEC 128 379 #define ARM_TWDG_LOAD_VAL (ARM_SP805_TWDG_CLK_HZ * \ 380 ARM_TWDG_TIMEOUT_SEC) 381 382 /****************************************************************************** 383 * Required platform porting definitions common to all ARM standard platforms 384 *****************************************************************************/ 385 386 /* 387 * Some data must be aligned on the biggest cache line size in the platform. 388 * This is known only to the platform as it might have a combination of 389 * integrated and external caches (64 on Arbel). 390 */ 391 #define CACHE_WRITEBACK_GRANULE (U(1) << ARM_CACHE_WRITEBACK_SHIFT) 392 393 /* 394 * To enable FW_CONFIG to be loaded by BL1, define the corresponding base 395 * and limit. Leave enough space of BL2 meminfo. 396 */ 397 #define ARM_FW_CONFIG_BASE (ARM_BL_RAM_BASE + sizeof(meminfo_t)) 398 #define ARM_FW_CONFIG_LIMIT ( \ 399 (ARM_BL_RAM_BASE + PAGE_SIZE) + (PAGE_SIZE / 2U)) 400 401 /* 402 * Boot parameters passed from BL2 to BL31/BL32 are stored here 403 */ 404 #define ARM_BL2_MEM_DESC_BASE (ARM_FW_CONFIG_LIMIT) 405 #define ARM_BL2_MEM_DESC_LIMIT ( \ 406 ARM_BL2_MEM_DESC_BASE + (PAGE_SIZE / 2U)) 407 408 /* 409 * Define limit of firmware configuration memory: 410 * ARM_FW_CONFIG + ARM_BL2_MEM_DESC memory 411 */ 412 #define ARM_FW_CONFIGS_LIMIT (ARM_BL_RAM_BASE + (PAGE_SIZE * 2)) 413 414 /******************************************************************************* 415 * BL1 specific defines. 416 * BL1 RW data is relocated from ROM to RAM at runtime so we need 417 * two sets of addresses. 418 ******************************************************************************/ 419 #define BL1_RO_BASE PLAT_ARM_TRUSTED_ROM_BASE 420 #define BL1_RO_LIMIT (PLAT_ARM_TRUSTED_ROM_BASE + \ 421 (PLAT_ARM_TRUSTED_ROM_SIZE - PLAT_ARM_MAX_ROMLIB_RO_SIZE)) 422 /* 423 * Put BL1 RW at the top of the Trusted SRAM. 424 */ 425 #define BL1_RW_BASE (ARM_BL_RAM_BASE + ARM_BL_RAM_SIZE - \ 426 (PLAT_ARM_MAX_BL1_RW_SIZE + PLAT_ARM_MAX_ROMLIB_RW_SIZE)) 427 #define BL1_RW_LIMIT (ARM_BL_RAM_BASE + \ 428 (ARM_BL_RAM_SIZE - PLAT_ARM_MAX_ROMLIB_RW_SIZE)) 429 430 #define ROMLIB_RO_BASE BL1_RO_LIMIT 431 #define ROMLIB_RO_LIMIT ( \ 432 PLAT_ARM_TRUSTED_ROM_BASE + PLAT_ARM_TRUSTED_ROM_SIZE) 433 434 #define ROMLIB_RW_BASE (BL1_RW_BASE + PLAT_ARM_MAX_BL1_RW_SIZE) 435 #define ROMLIB_RW_END ( \ 436 ROMLIB_RW_BASE + PLAT_ARM_MAX_ROMLIB_RW_SIZE) 437 438 /****************************************************************************** 439 * BL2 specific defines. 440 *****************************************************************************/ 441 #if BL2_AT_EL3 442 /* Put BL2 towards the middle of the Trusted SRAM */ 443 #define BL2_BASE (ARM_TRUSTED_SRAM_BASE + \ 444 PLAT_ARM_TRUSTED_SRAM_SIZE >> 1) + 0x2000) 445 #define BL2_LIMIT (ARM_BL_RAM_BASE + ARM_BL_RAM_SIZE) 446 #else 447 /* 448 * Put BL2 just below BL1. 449 */ 450 #define BL2_BASE (BL1_RW_BASE - PLAT_ARM_MAX_BL2_SIZE) 451 #define BL2_LIMIT BL1_RW_BASE 452 #endif /* BL2_AT_EL3 */ 453 454 /******************************************************************************* 455 * BL31 specific defines. 456 ******************************************************************************/ 457 #if ARM_BL31_IN_DRAM || SEPARATE_NOBITS_REGION 458 /* 459 * Put BL31 at the bottom of TZC secured DRAM 460 */ 461 #define BL31_BASE ARM_AP_TZC_DRAM1_BASE 462 #define BL31_LIMIT ( \ 463 ARM_AP_TZC_DRAM1_BASE + PLAT_ARM_MAX_BL31_SIZE) 464 465 /* 466 * For SEPARATE_NOBITS_REGION, BL31 PROGBITS are loaded in TZC secured DRAM. 467 * And BL31 NOBITS are loaded in Trusted SRAM such that BL2 is overwritten. 468 */ 469 #if SEPARATE_NOBITS_REGION 470 #define BL31_NOBITS_BASE BL2_BASE 471 #define BL31_NOBITS_LIMIT BL2_LIMIT 472 #endif /* SEPARATE_NOBITS_REGION */ 473 #elif (RESET_TO_BL31) 474 /* Ensure Position Independent support (PIE) is enabled for this config.*/ 475 #if !ENABLE_PIE 476 #error "BL31 must be a PIE if RESET_TO_BL31=1." 477 #endif /* !ENABLE_PIE */ 478 /* 479 * Since this is PIE, we can define BL31_BASE to 0x0 since this macro is solely 480 * used for building BL31 and not used for loading BL31. 481 */ 482 #define NEW_SRAM_ALLOCATION 483 484 #ifdef NEW_SRAM_ALLOCATION 485 #define BL31_BASE 0x02000000 486 #else 487 #define BL31_BASE 0x02001000 488 #endif /* NEW_SRAM_ALLOCATION */ 489 490 #define BL31_LIMIT BL2_BASE /* PLAT_ARM_MAX_BL31_SIZE */ 491 #else 492 /* Put BL31 below BL2 in the Trusted SRAM.*/ 493 #define BL31_BASE ((ARM_BL_RAM_BASE + ARM_BL_RAM_SIZE) - \ 494 PLAT_ARM_MAX_BL31_SIZE) 495 #define BL31_PROGBITS_LIMIT BL2_BASE 496 497 /* 498 * For BL2_AT_EL3 make sure the BL31 can grow up until BL2_BASE. 499 * This is because in the BL2_AT_EL3 configuration, BL2 is always resident. 500 */ 501 #if BL2_AT_EL3 502 #define BL31_LIMIT BL2_BASE 503 #else 504 #define BL31_LIMIT (ARM_BL_RAM_BASE + ARM_BL_RAM_SIZE) 505 #endif /* BL2_AT_EL3 */ 506 #endif /* ARM_BL31_IN_DRAM || SEPARATE_NOBITS_REGION */ 507 508 /* 509 * BL32 is mandatory in AArch32. In AArch64, undefine BL32_BASE if there is 510 * no SPD and no SPM-MM, as they are the only ones that can be used as BL32. 511 */ 512 #if defined(SPD_none) && !SPM_MM 513 #error BL32_BASE is not defined 514 #undef BL32_BASE 515 #endif /* SPD_none && !SPM_MM */ 516 517 /****************************************************************************** 518 * FWU Images: NS_BL1U, BL2U & NS_BL2U defines. 519 *****************************************************************************/ 520 #define BL2U_BASE BL2_BASE 521 #define BL2U_LIMIT BL2_LIMIT 522 523 #define NS_BL2U_BASE ARM_NS_DRAM1_BASE 524 #define NS_BL1U_BASE (PLAT_ARM_NVM_BASE + UL(0x03EB8000)) 525 526 /* 527 * ID of the secure physical generic timer interrupt used by the TSP. 528 */ 529 #define TSP_IRQ_SEC_PHY_TIMER ARM_IRQ_SEC_PHY_TIMER 530 531 /* 532 * One cache line needed for bakery locks on ARM platforms 533 */ 534 #define PLAT_PERCPU_BAKERY_LOCK_SIZE (1 * CACHE_WRITEBACK_GRANULE) 535 536 /* Priority levels for ARM platforms */ 537 #define PLAT_RAS_PRI 0x10 538 #define PLAT_SDEI_CRITICAL_PRI 0x60 539 #define PLAT_SDEI_NORMAL_PRI 0x70 540 541 /* ARM platforms use 3 upper bits of secure interrupt priority */ 542 #define ARM_PRI_BITS 3 543 544 /* SGI used for SDEI signalling */ 545 #define ARM_SDEI_SGI ARM_IRQ_SEC_SGI_0 546 547 #if SDEI_IN_FCONF 548 /* ARM SDEI dynamic private event max count */ 549 #define ARM_SDEI_DP_EVENT_MAX_CNT 3 550 551 /* ARM SDEI dynamic shared event max count */ 552 #define ARM_SDEI_DS_EVENT_MAX_CNT 3 553 #else 554 /* ARM SDEI dynamic private event numbers */ 555 #define ARM_SDEI_DP_EVENT_0 1000 556 #define ARM_SDEI_DP_EVENT_1 1001 557 #define ARM_SDEI_DP_EVENT_2 1002 558 559 /* ARM SDEI dynamic shared event numbers */ 560 #define ARM_SDEI_DS_EVENT_0 2000 561 #define ARM_SDEI_DS_EVENT_1 2001 562 #define ARM_SDEI_DS_EVENT_2 2002 563 564 #define ARM_SDEI_PRIVATE_EVENTS \ 565 SDEI_DEFINE_EVENT_0(ARM_SDEI_SGI), \ 566 SDEI_PRIVATE_EVENT(ARM_SDEI_DP_EVENT_0, SDEI_DYN_IRQ, SDEI_MAPF_DYNAMIC), \ 567 SDEI_PRIVATE_EVENT(ARM_SDEI_DP_EVENT_1, SDEI_DYN_IRQ, SDEI_MAPF_DYNAMIC), \ 568 SDEI_PRIVATE_EVENT(ARM_SDEI_DP_EVENT_2, SDEI_DYN_IRQ, SDEI_MAPF_DYNAMIC) 569 570 #define ARM_SDEI_SHARED_EVENTS \ 571 SDEI_SHARED_EVENT(ARM_SDEI_DS_EVENT_0, SDEI_DYN_IRQ, SDEI_MAPF_DYNAMIC), \ 572 SDEI_SHARED_EVENT(ARM_SDEI_DS_EVENT_1, SDEI_DYN_IRQ, SDEI_MAPF_DYNAMIC), \ 573 SDEI_SHARED_EVENT(ARM_SDEI_DS_EVENT_2, SDEI_DYN_IRQ, SDEI_MAPF_DYNAMIC) 574 #endif /* SDEI_IN_FCONF */ 575 576 #endif /* ARM_DEF_H */ 577