1/* 2 * Copyright (c) 2021-2025, Arm Limited. All rights reserved. 3 * 4 * SPDX-License-Identifier: BSD-3-Clause 5 */ 6 7#include <arch.h> 8#include <asm_macros.S> 9#include <common/bl_common.h> 10#include <cortex_x3.h> 11#include <cpu_macros.S> 12#include <plat_macros.S> 13#include "wa_cve_2022_23960_bhb_vector.S" 14 15/* Hardware handled coherency */ 16#if HW_ASSISTED_COHERENCY == 0 17#error "Cortex-X3 must be compiled with HW_ASSISTED_COHERENCY enabled" 18#endif 19 20/* 64-bit only core */ 21#if CTX_INCLUDE_AARCH32_REGS == 1 22#error "Cortex-X3 supports only AArch64. Compile with CTX_INCLUDE_AARCH32_REGS=0" 23#endif 24 25.global check_erratum_cortex_x3_3701769 26 27add_erratum_entry cortex_x3, ERRATUM(3701769), ERRATA_X3_3701769, NO_APPLY_AT_RESET 28 29check_erratum_ls cortex_x3, ERRATUM(3701769), CPU_REV(1, 2) 30 31#if WORKAROUND_CVE_2022_23960 32 wa_cve_2022_23960_bhb_vector_table CORTEX_X3_BHB_LOOP_COUNT, cortex_x3 33#endif /* WORKAROUND_CVE_2022_23960 */ 34 35/* Disable hardware page aggregation. Enables mitigation for `CVE-2024-5660` */ 36workaround_reset_start cortex_x3, CVE(2024, 5660), WORKAROUND_CVE_2024_5660 37 sysreg_bit_set CORTEX_X3_CPUECTLR_EL1, BIT(46) 38workaround_reset_end cortex_x3, CVE(2024, 5660) 39 40check_erratum_ls cortex_x3, CVE(2024, 5660), CPU_REV(1, 2) 41 42workaround_reset_start cortex_x3, ERRATUM(2070301), ERRATA_X3_2070301 43 sysreg_bitfield_insert CORTEX_X3_CPUECTLR2_EL1, CORTEX_X3_CPUECTLR2_EL1_PF_MODE_CNSRV, \ 44 CORTEX_X3_CPUECTLR2_EL1_PF_MODE_LSB, CORTEX_X3_CPUECTLR2_EL1_PF_MODE_WIDTH 45workaround_reset_end cortex_x3, ERRATUM(2070301) 46 47check_erratum_ls cortex_x3, ERRATUM(2070301), CPU_REV(1, 2) 48 49workaround_reset_start cortex_x3, ERRATUM(2266875), ERRATA_X3_2266875 50 sysreg_bit_set CORTEX_X3_CPUACTLR_EL1, BIT(22) 51workaround_reset_end cortex_x3, ERRATUM(2266875) 52 53check_erratum_ls cortex_x3, ERRATUM(2266875), CPU_REV(1, 0) 54 55workaround_reset_start cortex_x3, ERRATUM(2302506), ERRATA_X3_2302506 56 sysreg_bit_set CORTEX_X3_CPUACTLR2_EL1, BIT(0) 57workaround_reset_end cortex_x3, ERRATUM(2302506) 58 59check_erratum_ls cortex_x3, ERRATUM(2302506), CPU_REV(1, 1) 60 61.global erratum_cortex_x3_2313909_wa 62workaround_runtime_start cortex_x3, ERRATUM(2313909), ERRATA_X3_2313909 63 /* Set/unset bit 36 in ACTLR2_EL1. The first call will set it, applying 64 * the workaround. Second call clears it to undo it. */ 65 sysreg_bit_toggle CORTEX_X3_CPUACTLR2_EL1, CORTEX_X3_CPUACTLR2_EL1_BIT_36 66workaround_runtime_end cortex_x3, ERRATUM(2313909), NO_ISB 67 68check_erratum_ls cortex_x3, ERRATUM(2313909), CPU_REV(1, 0) 69 70workaround_reset_start cortex_x3, ERRATUM(2372204), ERRATA_X3_2372204 71 /* Set bit 40 in CPUACTLR2_EL1 */ 72 sysreg_bit_set CORTEX_X3_CPUACTLR2_EL1, BIT(40) 73workaround_reset_end cortex_x3, ERRATUM(2372204) 74 75check_erratum_ls cortex_x3, ERRATUM(2372204), CPU_REV(1, 0) 76 77workaround_reset_start cortex_x3, ERRATUM(2615812), ERRATA_X3_2615812 78 /* Disable retention control for WFI and WFE. */ 79 mrs x0, CORTEX_X3_CPUPWRCTLR_EL1 80 bfi x0, xzr, #CORTEX_X3_CPUPWRCTLR_EL1_WFI_RET_CTRL_BITS_SHIFT, #3 81 bfi x0, xzr, #CORTEX_X3_CPUPWRCTLR_EL1_WFE_RET_CTRL_BITS_SHIFT, #3 82 msr CORTEX_X3_CPUPWRCTLR_EL1, x0 83workaround_reset_end cortex_x3, ERRATUM(2615812) 84 85check_erratum_ls cortex_x3, ERRATUM(2615812), CPU_REV(1, 1) 86 87workaround_reset_start cortex_x3, ERRATUM(2641945), ERRATA_X3_2641945 88 sysreg_bit_set CORTEX_X3_CPUACTLR6_EL1, BIT(41) 89workaround_reset_end cortex_x3, ERRATUM(2641945) 90 91check_erratum_ls cortex_x3, ERRATUM(2641945), CPU_REV(1, 0) 92 93workaround_reset_start cortex_x3, ERRATUM(2742421), ERRATA_X3_2742421 94 /* Set CPUACTLR5_EL1[56:55] to 2'b01 */ 95 sysreg_bit_set CORTEX_X3_CPUACTLR5_EL1, CORTEX_X3_CPUACTLR5_EL1_BIT_55 96 sysreg_bit_clear CORTEX_X3_CPUACTLR5_EL1, CORTEX_X3_CPUACTLR5_EL1_BIT_56 97workaround_reset_end cortex_x3, ERRATUM(2742421) 98 99check_erratum_ls cortex_x3, ERRATUM(2742421), CPU_REV(1, 1) 100 101workaround_runtime_start cortex_x3, ERRATUM(2743088), ERRATA_X3_2743088 102 /* dsb before isb of power down sequence */ 103 dsb sy 104workaround_runtime_end cortex_x3, ERRATUM(2743088), NO_ISB 105 106check_erratum_ls cortex_x3, ERRATUM(2743088), CPU_REV(1, 1) 107 108workaround_reset_start cortex_x3, ERRATUM(2779509), ERRATA_X3_2779509 109 /* Set CPUACTLR3_EL1 bit 47 */ 110 sysreg_bit_set CORTEX_X3_CPUACTLR3_EL1, CORTEX_X3_CPUACTLR3_EL1_BIT_47 111workaround_reset_end cortex_x3, ERRATUM(2779509) 112 113check_erratum_ls cortex_x3, ERRATUM(2779509), CPU_REV(1, 1) 114 115workaround_reset_start cortex_x3, CVE(2022, 23960), WORKAROUND_CVE_2022_23960 116#if IMAGE_BL31 117 override_vector_table wa_cve_vbar_cortex_x3 118#endif /* IMAGE_BL31 */ 119workaround_reset_end cortex_x3, CVE(2022, 23960) 120 121check_erratum_chosen cortex_x3, CVE(2022, 23960), WORKAROUND_CVE_2022_23960 122 123workaround_reset_start cortex_x3, CVE(2024, 7881), WORKAROUND_CVE_2024_7881 124 /* --------------------------------- 125 * Sets BIT41 of CPUACTLR6_EL1 which 126 * disables L1 Data cache prefetcher 127 * --------------------------------- 128 */ 129 sysreg_bit_set CORTEX_X3_CPUACTLR6_EL1, BIT(41) 130workaround_reset_end cortex_x3, CVE(2024, 7881) 131 132check_erratum_chosen cortex_x3, CVE(2024, 7881), WORKAROUND_CVE_2024_7881 133 134cpu_reset_func_start cortex_x3 135 /* Disable speculative loads */ 136 msr SSBS, xzr 137cpu_reset_func_end cortex_x3 138 139 /* ---------------------------------------------------- 140 * HW will do the cache maintenance while powering down 141 * ---------------------------------------------------- 142 */ 143func cortex_x3_core_pwr_dwn 144 apply_erratum cortex_x3, ERRATUM(2313909), ERRATA_X3_2313909, NO_GET_CPU_REV 145 /* --------------------------------------------------- 146 * Enable CPU power down bit in power control register 147 * --------------------------------------------------- 148 */ 149 sysreg_bit_set CORTEX_X3_CPUPWRCTLR_EL1, CORTEX_X3_CPUPWRCTLR_EL1_CORE_PWRDN_BIT 150 apply_erratum cortex_x3, ERRATUM(2743088), ERRATA_X3_2743088, NO_GET_CPU_REV 151 isb 152 ret 153endfunc cortex_x3_core_pwr_dwn 154 155 /* --------------------------------------------- 156 * This function provides Cortex-X3- 157 * specific register information for crash 158 * reporting. It needs to return with x6 159 * pointing to a list of register names in ascii 160 * and x8 - x15 having values of registers to be 161 * reported. 162 * --------------------------------------------- 163 */ 164.section .rodata.cortex_x3_regs, "aS" 165cortex_x3_regs: /* The ascii list of register names to be reported */ 166 .asciz "cpuectlr_el1", "" 167 168func cortex_x3_cpu_reg_dump 169 adr x6, cortex_x3_regs 170 mrs x8, CORTEX_X3_CPUECTLR_EL1 171 ret 172endfunc cortex_x3_cpu_reg_dump 173 174declare_cpu_ops_wa_4 cortex_x3, CORTEX_X3_MIDR, \ 175 cortex_x3_reset_func, \ 176 CPU_NO_EXTRA1_FUNC, \ 177 CPU_NO_EXTRA2_FUNC, \ 178 CPU_NO_EXTRA3_FUNC, \ 179 check_erratum_cortex_x3_7881, \ 180 cortex_x3_core_pwr_dwn 181