1 /* SPDX-License-Identifier: BSD-3-Clause */ 2 /* 3 * Copyright (c) 2025, Rockchip Electronics Co., Ltd. 4 */ 5 6 #ifndef __PMU_H__ 7 #define __PMU_H__ 8 9 #include <assert.h> 10 11 #include <mmio.h> 12 13 /* PMU */ 14 #define PMU1_OFFSET 0x10000 15 #define PMU2_OFFSET 0x20000 16 17 #define PMU0_PWR_CON 0x0000 18 #define PMU0_PWR_STATUS 0x0004 19 #define PMU0_WAKEUP_INT_CON 0x0008 20 #define PMU0_WAKEUP_INT_ST 0x000c 21 #define PMU0_PMIC_STABLE_CNT_THRES 0x0010 22 #define PMU0_WAKEUP_RST_CLR_CNT_THRES 0x0014 23 #define PMU0_OSC_STABLE_CNT_THRES 0x0018 24 #define PMU0_PWR_C0_STABLE_CON 0x001c 25 #define PMU0_DDR_RET_CON(i) (0x0020 + (i) * 4) 26 #define PMU0_INFO_TX_CON 0x0030 27 28 #define PMU1_VERSION_ID (PMU1_OFFSET + 0x0000) 29 #define PMU1_PWR_CON (PMU1_OFFSET + 0x0004) 30 #define PMU1_PWR_FSM (PMU1_OFFSET + 0x0008) 31 #define PMU1_INT_MASK_CON (PMU1_OFFSET + 0x000c) 32 #define PMU1_WAKEUP_INT_CON (PMU1_OFFSET + 0x0010) 33 #define PMU1_WAKEUP_INT_ST (PMU1_OFFSET + 0x0014) 34 #define PMU1_DDR_PWR_CON(i) (PMU1_OFFSET + 0x0100 + (i) * 4) 35 #define PMU1_DDR_PWR_SFTCON(i) (PMU1_OFFSET + 0x0110 + (i) * 4) 36 #define PMU1_DDR_AXIPWR_CON(i) (PMU1_OFFSET + 0x0120 + (i) * 4) 37 #define PMU1_DDR_AXIPWR_SFTCON(i) (PMU1_OFFSET + 0x0130 + (i) * 4) 38 #define PMU1_DDR_PWR_FSM (PMU1_OFFSET + 0x0140) 39 #define PMU1_DDR_PWR_ST (PMU1_OFFSET + 0x0144) 40 #define PMU1_DDR_AXIPWR_ST (PMU1_OFFSET + 0x0148) 41 #define PMU1_CRU_PWR_CON(i) (PMU1_OFFSET + 0x0200 + (i) * 4) 42 #define PMU1_CRU_PWR_SFTCON(i) (PMU1_OFFSET + 0x0208 + (i) * 4) 43 #define PMU1_CRU_PWR_FSM (PMU1_OFFSET + 0x0210) 44 #define PMU1_PLLPD_CON(i) (PMU1_OFFSET + 0x0220 + (i) * 4) 45 #define PMU1_PLLPD_SFTCON(i) (PMU1_OFFSET + 0x0228 + (i) * 4) 46 #define PMU1_STABLE_CNT_THRESH (PMU1_OFFSET + 0x0300) 47 #define PMU1_OSC_STABLE_CNT_THRESH (PMU1_OFFSET + 0x0304) 48 #define PMU1_WAKEUP_RST_CLR_CNT_THRESH (PMU1_OFFSET + 0x0308) 49 #define PMU1_PLL_LOCK_CNT_THRESH (PMU1_OFFSET + 0x030c) 50 #define PMU1_WAKEUP_TIMEOUT_THRESH (PMU1_OFFSET + 0x0310) 51 #define PMU1_PWM_SWITCH_CNT_THRESH (PMU1_OFFSET + 0x0314) 52 #define PMU1_SLEEP_CNT_THRESH (PMU1_OFFSET + 0x0318) 53 #define PMU1_INFO_TX_CON (PMU1_OFFSET + 0x0400) 54 55 #define PMU2_SCU0_PWR_CON (PMU2_OFFSET + 0x0000) 56 #define PMU2_SCU1_PWR_CON (PMU2_OFFSET + 0x0004) 57 #define PMU2_SCU0_PWR_SFTCON (PMU2_OFFSET + 0x0008) 58 #define PMU2_SCU1_PWR_SFTCON (PMU2_OFFSET + 0x000c) 59 #define PMU2_SCU0_AUTO_PWR_CON (PMU2_OFFSET + 0x0010) 60 #define PMU2_SCU1_AUTO_PWR_CON (PMU2_OFFSET + 0x0014) 61 #define PMU2_SCU_PWR_FSM_STATUS (PMU2_OFFSET + 0x0018) 62 #define PMU2_DBG_PWR_CON(i) (PMU2_OFFSET + 0x001c + (i) * 4) 63 #define PMU2_CLUSTER_PWR_ST (PMU2_OFFSET + 0x0024) 64 #define PMU2_CLUSTER0_IDLE_CON (PMU2_OFFSET + 0x0028) 65 #define PMU2_CLUSTER1_IDLE_CON (PMU2_OFFSET + 0x002c) 66 #define PMU2_CLUSTER0_IDLE_SFTCON (PMU2_OFFSET + 0x0030) 67 #define PMU2_CLUSTER1_IDLE_SFTCON (PMU2_OFFSET + 0x0034) 68 #define PMU2_CLUSTER_IDLE_ACK (PMU2_OFFSET + 0x0038) 69 #define PMU2_CLUSTER_IDLE_ST (PMU2_OFFSET + 0x003c) 70 #define PMU2_SCU0_PWRUP_CNT_THRESH (PMU2_OFFSET + 0x0040) 71 #define PMU2_SCU0_PWRDN_CNT_THRESH (PMU2_OFFSET + 0x0044) 72 #define PMU2_SCU0_STABLE_CNT_THRESH (PMU2_OFFSET + 0x0048) 73 #define PMU2_SCU1_PWRUP_CNT_THRESH (PMU2_OFFSET + 0x004c) 74 #define PMU2_SCU1_PWRDN_CNT_THRESH (PMU2_OFFSET + 0x0050) 75 #define PMU2_SCU1_STABLE_CNT_THRESH (PMU2_OFFSET + 0x0054) 76 #define PMU2_CPU_AUTO_PWR_CON(i) (PMU2_OFFSET + 0x0080 + ((i)) * 4) 77 #define PMU2_CPU_PWR_SFTCON(i) (PMU2_OFFSET + 0x00a0 + ((i)) * 4) 78 #define PMU2_CCI_PWR_CON (PMU2_OFFSET + 0x00e0) 79 #define PMU2_CCI_PWR_SFTCON (PMU2_OFFSET + 0x00e4) 80 #define PMU2_CCI_PWR_ST (PMU2_OFFSET + 0x00e8) 81 #define PMU2_CCI_POWER_STATE (PMU2_OFFSET + 0x00ec) 82 #define PMU2_BUS_IDLE_CON(i) (PMU2_OFFSET + 0x0100 + (i) * 4) 83 #define PMU2_BUS_IDLE_SFTCON(i) (PMU2_OFFSET + 0x0110 + (i) * 4) 84 #define PMU2_BUS_IDLE_ACK (PMU2_OFFSET + 0x0120) 85 #define PMU2_BUS_IDLE_ST (PMU2_OFFSET + 0x0128) 86 #define PMU2_NOC_AUTO_CON(i) (PMU2_OFFSET + 0x0130 + (i) * 4) 87 #define PMU2_NOC_AUTO_SFTCON(i) (PMU2_OFFSET + 0x0140 + (i) * 4) 88 #define PMU2_BUS_IDLEACK_BYPASS_CON (PMU2_OFFSET + 0x0150) 89 #define PMU2_PWR_GATE_CON(i) (PMU2_OFFSET + 0x0200 + (i) * 4) 90 #define PMU2_PWR_GATE_SFTCON(i) (PMU2_OFFSET + 0x0210 + (i) * 4) 91 #define PMU2_VOL_GATE_SFTCON(i) (PMU2_OFFSET + 0x0220 + (i) * 4) 92 #define PMU2_PWR_GATE_ST (PMU2_OFFSET + 0x0230) 93 #define PMU2_PWR_GATE_FSM (PMU2_OFFSET + 0x0238) 94 #define PMU2_PD_DWN_ACK_STATE(i) (PMU2_OFFSET + 0x0240 + (i) * 4) 95 #define PMU2_PD_DWN_LC_ACK_STATE(i) (PMU2_OFFSET + 0x0248 + (i) * 4) 96 #define PMU2_PD_DWN_MEM_ACK_STATE(i) (PMU2_OFFSET + 0x0250 + (i) * 4) 97 #define PMU2_PWR_UP_C0_STABLE_CON(i) (PMU2_OFFSET + 0x0260 + (i) * 4) 98 #define PMU2_PWR_DWN_C0_STABLE_CON(i) (PMU2_OFFSET + 0x0270 + (i) * 4) 99 #define PMU2_PWR_STABLE_C0_CNT_THRES (PMU2_OFFSET + 0x027c) 100 #define PMU2_FAST_POWER_CON (PMU2_OFFSET + 0x0284) 101 #define PMU2_FAST_PWRUP_CNT_THRESH_0 (PMU2_OFFSET + 0x0288) 102 #define PMU2_FAST_PWRDN_CNT_THRESH_0 (PMU2_OFFSET + 0x028c) 103 #define PMU2_FAST_PWRUP_CNT_THRESH_1 (PMU2_OFFSET + 0x0290) 104 #define PMU2_FAST_PWRDN_CNT_THRESH_1 (PMU2_OFFSET + 0x0294) 105 #define PMU2_FAST_PWRUP_CNT_THRESH_2 (PMU2_OFFSET + 0x0298) 106 #define PMU2_FAST_PWRDN_CNT_THRESH_2 (PMU2_OFFSET + 0x029c) 107 #define PMU2_MEM_PWR_GATE_SFTCON(i) (PMU2_OFFSET + 0x0300) 108 #define PMU2_SUBMEM_PWR_GATE_SFTCON(i) (PMU2_OFFSET + 0x0310) 109 #define PMU2_SUBMEM_PWR_ACK_BYPASS_SFTCON(i) (PMU2_OFFSET + 0x0320) 110 #define PMU2_SUBMEM_PWR_GATE_STATUS (PMU2_OFFSET + 0x0328) 111 #define PMU2_QCHANNEL_PWR_CON0 (PMU2_OFFSET + 0x0400) 112 #define PMU2_QCHANNEL_PWR_SFTCON0 (PMU2_OFFSET + 0x0404) 113 #define PMU2_QCHANNEL_STATUS0 (PMU2_OFFSET + 0x0408) 114 #define PMU2_C0_PWRACK_BYPASS_CON(i) (PMU2_OFFSET + 0x0380 + (i) * 4) 115 #define PMU2_C1_PWRACK_BYPASS_CON(i) (PMU2_OFFSET + 0x0390 + (i) * 4) 116 #define PMU2_C2_PWRACK_BYPASS_CON(i) (PMU2_OFFSET + 0x03a0 + (i) * 4) 117 #define PMU2_DEBUG_INFO_SEL (PMU2_OFFSET + 0x03f0) 118 #define PMU2_BISR_GLB_CON (PMU2_OFFSET + 0x500) 119 #define PMU2_BISR_TIMEOUT_THRES (PMU2_OFFSET + 0x504) 120 #define PMU2_BISR_PDGEN_CON(i) (PMU2_OFFSET + 0x510 + (i) * 4) 121 #define PMU2_BISR_PDGEN_SFTCON(i) (PMU2_OFFSET + 0x520 + (i) * 4) 122 #define PMU2_BISR_PDGDONE_CON(i) (PMU2_OFFSET + 0x530 + (i) * 4) 123 #define PMU2_BISR_PDGINIT_CON(i) (PMU2_OFFSET + 0x540 + (i) * 4) 124 #define PMU2_BISR_PDGDONE_STATUS(i) (PMU2_OFFSET + 0x550 + (i) * 4) 125 #define PMU2_BISR_PDGCEDIS_STATUS(i) (PMU2_OFFSET + 0x560 + (i) * 4) 126 #define PMU2_BISR_PWR_REPAIR_STATUS(i) (PMU2_OFFSET + 0x570 + (i) * 4) 127 128 /* PMU1CRU */ 129 #define PMU1CRU_CLKSEL_CON(i) ((i) * 0x4 + 0x300) 130 #define PMU1CRU_CLKSEL_CON_CNT 22 131 #define PMU1CRU_CLKGATE_CON(i) ((i) * 0x4 + 0x800) 132 #define PMU1CRU_CLKGATE_CON_CNT 8 133 #define PMU1CRU_SOFTRST_CON(i) ((i) * 0x4 + 0xa00) 134 #define PMU1CRU_SOFTRST_CON_CNT 8 135 #define PMU1CRU_DEEPSLOW_DET_CON 0xb40 136 #define PMU1CRU_DEEPSLOW_DET_ST 0xb44 137 138 /* PMU1SCRU */ 139 #define PMU1SCRU_CLKSEL_CON(i) ((i) * 0x4 + 0x4000) 140 #define PMU1SCRU_CLKSEL_CON_CNT 3 141 #define PMU1SCRU_CLKGATE_CON(i) ((i) * 0x4 + 0x4028) 142 #define PMU1SCRU_CLKGATE_CON_CNT 3 143 #define PMU1SCRU_SOFTRST_CON(i) ((i) * 0x4 + 0x4050) 144 #define PMU1SCRU_SOFTRST_CONCNT 3 145 146 /* PMU0GRF */ 147 #define PMU0GRF_SOC_CON(i) ((i) * 4) 148 #define PMU0GRF_IO_RET_CON(i) (0x20 + (i) * 4) 149 #define PMU0GRF_OS_REG(i) ((i) * 4) 150 151 /* PMU1GRF */ 152 #define PMU1GRF_SOC_CON(i) ((i) * 4) 153 #define PMU1GRF_SOC_ST 0x60 154 #define PMU1GRF_MEM_CON(i) (0x80 + (i) * 4) 155 #define PMU1GRF_OS_REG(i) (0x200 + (i) * 4) 156 157 #define PMU_MCU_HALT BIT(7) 158 #define PMU_MCU_SLEEP BIT(9) 159 #define PMU_MCU_DEEPSLEEP BIT(10) 160 #define PMU_MCU_STOP_MSK \ 161 (PMU_MCU_HALT | PMU_MCU_SLEEP | PMU_MCU_DEEPSLEEP) 162 163 #define CORES_PM_DISABLE 0x0 164 165 /* pmuioc */ 166 #define PMUIO0_IOC_GPIO0A_IOMUX_SEL_L 0x000 167 #define PMUIO0_IOC_GPIO0A_IOMUX_SEL_H 0x004 168 #define PMUIO0_IOC_GPIO0B_IOMUX_SEL_L 0x008 169 170 #define PMUIO1_IOC_GPIO0B_IOMUX_SEL_H 0x000 171 #define PMUIO1_IOC_GPIO0C_IOMUX_SEL_L 0x004 172 #define PMUIO1_IOC_GPIO0C_IOMUX_SEL_H 0x008 173 #define PMUIO1_IOC_GPIO0D_IOMUX_SEL_L 0x00c 174 #define PMUIO1_IOC_GPIO0D_IOMUX_SEL_H 0x010 175 176 /* PMU_PWR_CON */ 177 enum pmu0_pwr_con { 178 pmu_powermode0_en = 0, 179 pmu_pmu1_pd_byp = 1, 180 pmu_pmu1_bus_byp = 2, 181 pmu_pmu0_wkup_byp = 3, 182 pmu_pmu0_pmic_byp = 4, 183 pmu_pmu0_reset_byp = 5, 184 pmu_pmu0_freq_switch_byp = 6, 185 pmu_pmu0_osc_dis_byp = 7, 186 pmu_pmu1_pwrgt = 8, 187 pmu_pmu1_pwrgt_sft = 9, 188 pmu_pmu1_mempwr_sft_gt = 10, 189 pmu_pmu1_idle_en = 11, 190 pmu_pmu1_idle_sft_en = 12, 191 pmu_pmu1_noc_auto_en = 13, 192 pmu_pmu1_off_io_en = 14, 193 }; 194 195 enum pmu1_pwr_con { 196 pmu_powermode_en = 0, 197 pmu_scu0_byp = 1, 198 pmu_scu1_byp = 2, 199 pmu_cci_byp = 3, 200 pmu_bus_byp = 4, 201 pmu_ddr_byp = 5, 202 pmu_pwrgt_byp = 6, 203 pmu_cru_byp = 7, 204 pmu_qch_byp = 8, 205 pmu_wfi_byp = 12, 206 pmu_slp_cnt_en = 13, 207 }; 208 209 enum pmu_wakeup_int { 210 pmu_wkup_cpu0_int = 0, 211 pmu_wkup_cpu1_int = 1, 212 pmu_wkup_cpu2_int = 2, 213 pmu_wkup_cpu3_int = 3, 214 pmu_wkup_cpu4_int = 4, 215 pmu_wkup_cpu5_int = 5, 216 pmu_wkup_cpu6_int = 6, 217 pmu_wkup_cpu7_int = 7, 218 pmu_wkup_gpio0_int = 8, 219 pmu_wkup_sdmmc_int = 9, 220 pmu_wkup_sdio_int = 10, 221 pmu_wkup_usbdev_int = 11, 222 pmu_wkup_uart_int = 12, 223 pmu_wkup_mcu_int = 13, 224 pmu_wkup_timer_int = 14, 225 pmu_wkup_sys_int = 15, 226 pmu_wkup_pwm_int = 16, 227 pmu_wkup_tsadc_int = 17, 228 pmu_wkup_hptimer_int = 18, 229 pmu_wkup_saradc_int = 19, 230 pmu_wkup_timeout = 20, 231 }; 232 233 /* PMU_DDR_PWR_CON */ 234 enum pmu_ddr_pwr_con { 235 pmu_ddr_sref_c_en = 0, 236 pmu_ddr_ioret_en = 1, 237 pmu_ddr_ioret_exit_en = 2, 238 pmu_ddr_rstiov_en = 3, 239 pmu_ddr_rstiov_exit_en = 4, 240 pmu_ddr_gating_c_en = 5, 241 pmu_ddr_gating_p_en = 6, 242 }; 243 244 /* PMU_CRU_PWR_CON0 */ 245 enum pmu_cru_pwr_con0 { 246 pmu_alive_32k_en = 0, 247 pmu_osc_dis_en = 1, 248 pmu_wakeup_rst_en = 2, 249 pmu_input_clamp_en = 3, 250 pmu_alive_osc_mode_en = 4, 251 pmu_power_off_en = 5, 252 pmu_pwm_switch_en = 6, 253 pmu_pwm_gpio_ioe_en = 7, 254 pmu_pwm_switch_io = 8, 255 pmu_io_sleep_en = 9, 256 }; 257 258 /* PMU_CRU_PWR_CON1 */ 259 enum pmu_cru_pwr_con1 { 260 pmu_bus_clksrc_gt_en = 0, 261 pmu_vpu_clksrc_gt_en = 1, 262 pmu_vo_clksrc_gt_en = 2, 263 pmu_gpu_clksrc_gt_en = 3, 264 pmu_rkenc_clksrc_gt_en = 4, 265 pmu_rkvdec_clksrc_gt_en = 5, 266 pmu_core_clksrc_gt_en = 6, 267 pmu_ddr_clksrc_gt_en = 7, 268 }; 269 270 /* PMU_SCU_PWR_CON */ 271 enum pmu_scu_pwr_con { 272 pmu_l2_flush_en = 0, 273 pmu_l2_ilde_en = 1, 274 pmu_scu_pd_en = 2, 275 pmu_scu_pwroff_en = 3, 276 pmu_clst_cpu_pd_en = 5, 277 pmu_std_wfi_bypass = 8, 278 pmu_std_wfil2_bypass = 9, 279 pmu_scu_vol_gt_en = 10, 280 }; 281 282 /* PMU_PLLPD_CON */ 283 enum pmu_pllpd_con { 284 pmu_d0apll_pd_en = 0, 285 pmu_d0bpll_pd_en = 1, 286 pmu_d1apll_pd_en = 2, 287 pmu_d1bpll_pd_en = 3, 288 pmu_bpll_pd_en = 4, 289 pmu_lpll_pd_en = 5, 290 pmu_spll_pd_en = 6, 291 pmu_gpll_pd_en = 7, 292 pmu_cpll_pd_en = 8, 293 pmu_ppll_pd_en = 9, 294 pmu_aupll_pd_en = 10, 295 pmu_vpll_pd_en = 11, 296 }; 297 298 /* PMU_CLST_PWR_ST */ 299 enum pmu_clst_pwr_st { 300 pmu_cpu0_wfi = 0, 301 pmu_cpu1_wfi = 1, 302 pmu_cpu2_wfi = 2, 303 pmu_cpu3_wfi = 3, 304 pmu_cpu4_wfi = 4, 305 pmu_cpu5_wfi = 5, 306 pmu_cpu6_wfi = 6, 307 pmu_cpu7_wfi = 7, 308 pmu_scu0_standbywfil2 = 8, 309 pmu_scu1_standbywfil2 = 9, 310 pmu_scu0_l2flushdone = 10, 311 pmu_scu1_l2flushdone = 11, 312 pmu_cpu0_pd_st = 16, 313 pmu_cpu1_pd_st = 17, 314 pmu_cpu2_pd_st = 18, 315 pmu_cpu3_pd_st = 19, 316 pmu_cpu4_pd_st = 20, 317 pmu_cpu5_pd_st = 21, 318 pmu_cpu6_pd_st = 22, 319 pmu_cpu7_pd_st = 23, 320 pmu_scu0_pd_st = 24, 321 pmu_scu1_pd_st = 25, 322 }; 323 324 /* PMU_CLST_IDLE_CON */ 325 enum pmu_clst_idle_con { 326 pmu_adb400s_idle_req = 0, 327 pmu_clst_biu_idle_req = 1, 328 pmu_clst_clk_gt_msk = 2, 329 }; 330 331 enum cores_pm_ctr_mode { 332 core_pwr_pd = 0, 333 core_pwr_wfi = 1, 334 core_pwr_wfi_int = 2, 335 core_pwr_wfi_reset = 3, 336 }; 337 338 /* PMU_CPUX_AUTO_PWR_CON */ 339 enum pmu_cpu_auto_pwr_con { 340 pmu_cpu_pm_en = 0, 341 pmu_cpu_pm_int_wakeup_en = 1, 342 pmu_cpu_pm_dis_int = 2, 343 pmu_cpu_pm_sft_wakeup_en = 3, 344 }; 345 346 enum qos_id { 347 qos_decom = 0, 348 qos_dmac0 = 1, 349 qos_dmac1 = 2, 350 qos_dmac2 = 3, 351 qos_bus_mcu = 4, 352 qos_can0 = 5, 353 qos_can1 = 6, 354 qos_cci_m0 = 7, 355 qos_cci_m1 = 8, 356 qos_cci_m2 = 9, 357 qos_dap_lite = 10, 358 qos_hdcp1 = 11, 359 qos_ddr_mcu = 12, 360 qos_fspi1 = 13, 361 qos_gmac0 = 14, 362 qos_gmac1 = 15, 363 qos_sdio = 16, 364 qos_sdmmc = 17, 365 qos_flexbus = 18, 366 qos_gpu = 19, 367 qos_vepu1 = 20, 368 qos_npu_mcu = 21, 369 qos_npu_nsp0 = 22, 370 qos_npu_nsp1 = 23, 371 qos_npu_m0 = 24, 372 qos_npu_m1 = 25, 373 qos_npu_m0ro = 26, 374 qos_npu_m1ro = 27, 375 qos_emmc = 28, 376 qos_fspi0 = 29, 377 qos_mmu0 = 30, 378 qos_mmu1 = 31, 379 qos_pmu_mcu = 32, 380 qos_rkvdec = 33, 381 qos_crypto = 34, 382 qos_mmu2 = 35, 383 qos_ufshc = 36, 384 qos_vepu0 = 37, 385 qos_isp_mro = 38, 386 qos_isp_mwo = 39, 387 qos_vicap_m0 = 40, 388 qos_vpss_mro = 41, 389 qos_vpss_mwo = 42, 390 qos_hdcp0 = 43, 391 qos_vop_m0 = 44, 392 qos_vop_m1ro = 45, 393 qos_ebc = 46, 394 qos_rga0 = 47, 395 qos_rga1 = 48, 396 qos_jpeg = 49, 397 qos_vdpp = 50, 398 qos_dma2ddr = 51, 399 }; 400 401 enum pmu_bus_id { 402 pmu_bus_id_gpu = 0, 403 pmu_bus_id_npu0 = 1, 404 pmu_bus_id_npu1 = 2, 405 pmu_bus_id_nputop = 3, 406 pmu_bus_id_npusys = 4, 407 pmu_bus_id_vpu = 5, 408 pmu_bus_id_vdec = 6, 409 pmu_bus_id_vepu0 = 7, 410 pmu_bus_id_vepu1 = 8, 411 pmu_bus_id_vi = 9, 412 pmu_bus_id_usb = 10, 413 pmu_bus_id_vo0 = 11, 414 pmu_bus_id_vo1 = 12, 415 pmu_bus_id_vop = 13, 416 pmu_bus_id_vop_nocddrsch = 14, 417 pmu_bus_id_php = 15, 418 pmu_bus_id_audio = 16, 419 pmu_bus_id_gmac = 17, 420 pmu_bus_id_nvm = 18, 421 pmu_bus_id_center_nocddrsch = 19, 422 pmu_bus_id_center_nocmain = 20, 423 pmu_bus_id_ddr = 21, 424 pmu_bus_id_ddrsch0 = 22, 425 pmu_bus_id_ddrsch1 = 23, 426 pmu_bus_id_bus = 24, 427 pmu_bus_id_secure = 25, 428 pmu_bus_id_top = 26, 429 pmu_bus_id_vo0vop_chn = 27, 430 pmu_bus_id_cci = 28, 431 pmu_bus_id_cci_nocddrsch = 29, 432 pmu_bus_id_max, 433 }; 434 435 enum pmu_pd_id { 436 pmu_pd_npu = 0, 437 pmu_pd_bus = 1, 438 pmu_pd_secure = 2, 439 pmu_pd_center = 3, 440 pmu_pd_ddr = 4, 441 pmu_pd_cci = 5, 442 pmu_pd_nvm = 6, 443 pmu_pd_sd_gmac = 7, 444 pmu_pd_audio = 8, 445 pmu_pd_php = 9, 446 pmu_pd_subphp = 10, 447 pmu_pd_vop = 11, 448 pmu_pd_vop_smart = 12, 449 pmu_pd_vop_clst = 13, 450 pmu_pd_vo1 = 14, 451 pmu_pd_vo0 = 15, 452 pmu_pd_usb = 16, 453 pmu_pd_vi = 17, 454 pmu_pd_vepu0 = 18, 455 pmu_pd_vepu1 = 19, 456 pmu_pd_vdec = 20, 457 pmu_pd_vpu = 21, 458 pmu_pd_nputop = 22, 459 pmu_pd_npu0 = 23, 460 pmu_pd_npu1 = 24, 461 pmu_pd_gpu = 25, 462 pmu_pd_id_max, 463 }; 464 465 enum pmu_vd_id { 466 pmu_vd_npu = 0, 467 pmu_vd_ddr = 1, 468 pmu_vd_cci = 2, 469 pmu_vd_gpu = 3, 470 }; 471 472 enum pmu_bus_state { 473 pmu_bus_active = 0, 474 pmu_bus_idle = 1, 475 }; 476 477 enum pmu_pd_state { 478 pmu_pd_on = 0, 479 pmu_pd_off = 1 480 }; 481 482 enum pmu_scu_fsm_st { 483 pmu_scu_fsm_normal = 0, 484 pmu_scu_fsm_cpu_pwr_down = 1, 485 pmu_scu_fsm_l2_flush = 2, 486 pmu_scu_fsm_l2_idle = 3, 487 pmu_scu_fsm_clust_idle = 4, 488 pmu_scu_fsm_scu_pwr_down = 5, 489 pmu_scu_fsm_sleep = 6, 490 pmu_scu_fsm_wkup = 7, 491 pmu_scu_fsm_scu_pwr_up = 8, 492 pmu_scu_fsm_clust_resume = 9, 493 pmu_scu_fsm_cpu_pwr_up = 10, 494 }; 495 496 #define MAX_MEM_OS_REG_NUM 32 497 #define MEM_OS_REG_BASE \ 498 (PMUSRAM_BASE + PMUSRAM_RSIZE - MAX_MEM_OS_REG_NUM * 4) 499 500 #define PSRAM_SP_TOP MEM_OS_REG_BASE 501 502 #define PD_CTR_LOOP 5000 503 #define WFEI_CHECK_LOOP 5000 504 #define BUS_IDLE_LOOP 1000 505 #define NONBOOT_CPUS_OFF_LOOP 500000 506 507 #define REBOOT_FLAG 0x5242C300 508 #define BOOT_BROM_DOWNLOAD 0xef08a53c 509 510 #define BOOTROM_SUSPEND_MAGIC 0x02468ace 511 #define BOOTROM_RESUME_MAGIC 0x13579bdf 512 #define WARM_BOOT_MAGIC 0x76543210 513 #define VALID_GLB_RST_MSK 0xbfff 514 515 #define DEFAULT_BOOT_CPU 0 516 517 /******************************************************* 518 * sleep mode define 519 *******************************************************/ 520 #define SLP_ARMPD BIT(0) 521 #define SLP_ARMOFF BIT(1) 522 #define SLP_ARMOFF_DDRPD BIT(2) 523 #define SLP_ARMOFF_LOGOFF BIT(3) 524 #define SLP_ARMOFF_PMUOFF BIT(4) 525 #define SLP_FROM_UBOOT BIT(5) 526 527 /* all plls except ddr's pll*/ 528 #define SLP_PMU_HW_PLLS_PD BIT(8) 529 #define SLP_PMU_PMUALIVE_32K BIT(9) 530 #define SLP_PMU_DIS_OSC BIT(10) 531 532 #define SLP_CLK_GT BIT(16) 533 #define SLP_PMIC_LP BIT(17) 534 535 #define SLP_32K_EXT BIT(24) 536 #define SLP_TIME_OUT_WKUP BIT(25) 537 #define SLP_PMU_DBG BIT(26) 538 #define SLP_ARCH_TIMER_RESET BIT(27) 539 540 #define PM_INVALID_GPIO 0xffff 541 #define MAX_GPIO_POWER_CFG_CNT 10 542 #define MAX_VIRTUAL_PWROFF_IRQ_CNT 20 543 544 enum { 545 RK_PM_VIRT_PWROFF_EN = 0, 546 RK_PM_VIRT_PWROFF_IRQ_CFG = 1, 547 RK_PM_VIRT_PWROFF_MAX, 548 }; 549 550 /* sleep pin */ 551 #define RKPM_SLEEP_PIN0_EN BIT(0) /* GPIO0_A3 */ 552 #define RKPM_SLEEP_PIN1_EN BIT(1) /* GPIO0_A4 */ 553 #define RKPM_SLEEP_PIN2_EN BIT(2) /* GPIO0_A5 */ 554 555 #define RKPM_SLEEP_PIN0_ACT_LOW BIT(0) /* GPIO0_A3 */ 556 #define RKPM_SLEEP_PIN1_ACT_LOW BIT(1) /* GPIO0_A4 */ 557 #define RKPM_SLEEP_PIN2_ACT_LOW BIT(2) /* GPIO0_A5 */ 558 559 #define pmu_bus_idle_st(id) \ 560 (!!(mmio_read_32(PMU_BASE + PMU2_BUS_IDLE_ST) & BIT(id))) 561 562 #define pmu_bus_idle_ack(id) \ 563 (!!(mmio_read_32(PMU_BASE + PMU2_BUS_IDLE_ACK) & BIT(id))) 564 565 static inline uint32_t read_mem_os_reg(uint32_t id) 566 { 567 assert((id) < MAX_MEM_OS_REG_NUM); 568 569 return mmio_read_32(MEM_OS_REG_BASE + 4 * (id)); 570 } 571 572 static inline void write_mem_os_reg(uint32_t id, uint32_t val) 573 { 574 assert((id) < MAX_MEM_OS_REG_NUM); 575 576 mmio_write_32(MEM_OS_REG_BASE + 4 * (id), val); 577 } 578 #endif /* __PMU_H__ */ 579