1/* 2 * Copyright (c) 2018-2024, Arm Limited and Contributors. All rights reserved. 3 * 4 * SPDX-License-Identifier: BSD-3-Clause 5 */ 6 7#include <arch.h> 8#include <asm_macros.S> 9#include <common/bl_common.h> 10#include <cortex_a77.h> 11#include <cpu_macros.S> 12#include <plat_macros.S> 13#include "wa_cve_2022_23960_bhb_vector.S" 14 15/* Hardware handled coherency */ 16#if HW_ASSISTED_COHERENCY == 0 17#error "Cortex-A77 must be compiled with HW_ASSISTED_COHERENCY enabled" 18#endif 19 20/* 64-bit only core */ 21#if CTX_INCLUDE_AARCH32_REGS == 1 22#error "Cortex-A77 supports only AArch64. Compile with CTX_INCLUDE_AARCH32_REGS=0" 23#endif 24 25#if WORKAROUND_CVE_2022_23960 26 wa_cve_2022_23960_bhb_vector_table CORTEX_A77_BHB_LOOP_COUNT, cortex_a77 27#endif /* WORKAROUND_CVE_2022_23960 */ 28 29/* Disable hardware page aggregation. Enables mitigation for `CVE-2024-5660` */ 30workaround_reset_start cortex_a77, CVE(2024, 5660), WORKAROUND_CVE_2024_5660 31 sysreg_bit_set CORTEX_A77_CPUECTLR_EL1, BIT(46) 32workaround_reset_end cortex_a77, CVE(2024, 5660) 33 34check_erratum_ls cortex_a77, CVE(2024, 5660), CPU_REV(1, 1) 35 36workaround_reset_start cortex_a77, ERRATUM(1508412), ERRATA_A77_1508412 37 /* move cpu revision in again and compare against r0p0 */ 38 mov x0, x7 39 mov x1, #CPU_REV(0, 0) 40 bl cpu_rev_var_ls 41 cbz x0, 1f 42 43 ldr x0, =0x0 44 msr CORTEX_A77_CPUPSELR_EL3, x0 45 ldr x0, =0x00E8400000 46 msr CORTEX_A77_CPUPOR_EL3, x0 47 ldr x0, =0x00FFE00000 48 msr CORTEX_A77_CPUPMR_EL3, x0 49 ldr x0, =0x4004003FF 50 msr CORTEX_A77_CPUPCR_EL3, x0 51 ldr x0, =0x1 52 msr CORTEX_A77_CPUPSELR_EL3, x0 53 ldr x0, =0x00E8C00040 54 msr CORTEX_A77_CPUPOR_EL3, x0 55 ldr x0, =0x00FFE00040 56 msr CORTEX_A77_CPUPMR_EL3, x0 57 b 2f 581: 59 ldr x0, =0x0 60 msr CORTEX_A77_CPUPSELR_EL3, x0 61 ldr x0, =0x00E8400000 62 msr CORTEX_A77_CPUPOR_EL3, x0 63 ldr x0, =0x00FF600000 64 msr CORTEX_A77_CPUPMR_EL3, x0 65 ldr x0, =0x00E8E00080 66 msr CORTEX_A77_CPUPOR2_EL3, x0 67 ldr x0, =0x00FFE000C0 68 msr CORTEX_A77_CPUPMR2_EL3, x0 692: 70 ldr x0, =0x04004003FF 71 msr CORTEX_A77_CPUPCR_EL3, x0 72workaround_reset_end cortex_a77, ERRATUM(1508412) 73 74check_erratum_ls cortex_a77, ERRATUM(1508412), CPU_REV(1, 0) 75 76workaround_reset_start cortex_a77, ERRATUM(1791578), ERRATA_A77_1791578 77 sysreg_bit_set CORTEX_A77_ACTLR2_EL1, CORTEX_A77_ACTLR2_EL1_BIT_2 78workaround_reset_end cortex_a77, ERRATUM(1791578) 79 80check_erratum_ls cortex_a77, ERRATUM(1791578), CPU_REV(1, 1) 81 82workaround_reset_start cortex_a77, ERRATUM(1800714), ERRATA_A77_1800714 83 /* Disable allocation of splintered pages in the L2 TLB */ 84 sysreg_bit_set CORTEX_A77_CPUECTLR_EL1, CORTEX_A77_CPUECTLR_EL1_BIT_53 85workaround_reset_end cortex_a77, ERRATUM(1800714) 86 87check_erratum_ls cortex_a77, ERRATUM(1800714), CPU_REV(1, 1) 88 89workaround_reset_start cortex_a77, ERRATUM(1925769), ERRATA_A77_1925769 90 sysreg_bit_set CORTEX_A77_CPUECTLR_EL1, CORTEX_A77_CPUECTLR_EL1_BIT_8 91workaround_reset_end cortex_a77, ERRATUM(1925769) 92 93check_erratum_ls cortex_a77, ERRATUM(1925769), CPU_REV(1, 1) 94 95workaround_reset_start cortex_a77, ERRATUM(1946167), ERRATA_A77_1946167 96 ldr x0,=0x4 97 msr CORTEX_A77_CPUPSELR_EL3,x0 98 ldr x0,=0x10E3900002 99 msr CORTEX_A77_CPUPOR_EL3,x0 100 ldr x0,=0x10FFF00083 101 msr CORTEX_A77_CPUPMR_EL3,x0 102 ldr x0,=0x2001003FF 103 msr CORTEX_A77_CPUPCR_EL3,x0 104 105 ldr x0,=0x5 106 msr CORTEX_A77_CPUPSELR_EL3,x0 107 ldr x0,=0x10E3800082 108 msr CORTEX_A77_CPUPOR_EL3,x0 109 ldr x0,=0x10FFF00083 110 msr CORTEX_A77_CPUPMR_EL3,x0 111 ldr x0,=0x2001003FF 112 msr CORTEX_A77_CPUPCR_EL3,x0 113 114 ldr x0,=0x6 115 msr CORTEX_A77_CPUPSELR_EL3,x0 116 ldr x0,=0x10E3800200 117 msr CORTEX_A77_CPUPOR_EL3,x0 118 ldr x0,=0x10FFF003E0 119 msr CORTEX_A77_CPUPMR_EL3,x0 120 ldr x0,=0x2001003FF 121 msr CORTEX_A77_CPUPCR_EL3,x0 122workaround_reset_end cortex_a77, ERRATUM(1946167) 123 124check_erratum_ls cortex_a77, ERRATUM(1946167), CPU_REV(1, 1) 125 126workaround_reset_start cortex_a77, ERRATUM(2356587), ERRATA_A77_2356587 127 sysreg_bit_set CORTEX_A77_ACTLR2_EL1, CORTEX_A77_ACTLR2_EL1_BIT_0 128workaround_reset_end cortex_a77, ERRATUM(2356587) 129 130check_erratum_ls cortex_a77, ERRATUM(2356587), CPU_REV(1, 1) 131 132workaround_runtime_start cortex_a77, ERRATUM(2743100), ERRATA_A77_2743100 133 /* dsb before isb of power down sequence */ 134 dsb sy 135workaround_runtime_end cortex_a77, ERRATUM(2743100), NO_ISB 136 137check_erratum_ls cortex_a77, ERRATUM(2743100), CPU_REV(1, 1) 138 139workaround_reset_start cortex_a77, CVE(2022, 23960), WORKAROUND_CVE_2022_23960 140#if IMAGE_BL31 141 /* 142 * The Cortex-A77 generic vectors are overridden to apply errata 143 * mitigation on exception entry from lower ELs. 144 */ 145 adr x0, wa_cve_vbar_cortex_a77 146 msr vbar_el3, x0 147#endif /* IMAGE_BL31 */ 148workaround_reset_end cortex_a77, CVE(2022, 23960) 149 150check_erratum_chosen cortex_a77, CVE(2022, 23960), WORKAROUND_CVE_2022_23960 151 152 /* ------------------------------------------------- 153 * The CPU Ops reset function for Cortex-A77. Must follow AAPCS. 154 * ------------------------------------------------- 155 */ 156cpu_reset_func_start cortex_a77 157cpu_reset_func_end cortex_a77 158 159 /* --------------------------------------------- 160 * HW will do the cache maintenance while powering down 161 * --------------------------------------------- 162 */ 163func cortex_a77_core_pwr_dwn 164 /* --------------------------------------------- 165 * Enable CPU power down bit in power control register 166 * --------------------------------------------- 167 */ 168 sysreg_bit_set CORTEX_A77_CPUPWRCTLR_EL1, \ 169 CORTEX_A77_CPUPWRCTLR_EL1_CORE_PWRDN_BIT 170 171 apply_erratum cortex_a77, ERRATUM(2743100), ERRATA_A77_2743100, NO_GET_CPU_REV 172 173 isb 174 ret 175endfunc cortex_a77_core_pwr_dwn 176 177 /* --------------------------------------------- 178 * This function provides Cortex-A77 specific 179 * register information for crash reporting. 180 * It needs to return with x6 pointing to 181 * a list of register names in ascii and 182 * x8 - x15 having values of registers to be 183 * reported. 184 * --------------------------------------------- 185 */ 186.section .rodata.cortex_a77_regs, "aS" 187cortex_a77_regs: /* The ascii list of register names to be reported */ 188 .asciz "cpuectlr_el1", "" 189 190func cortex_a77_cpu_reg_dump 191 adr x6, cortex_a77_regs 192 mrs x8, CORTEX_A77_CPUECTLR_EL1 193 ret 194endfunc cortex_a77_cpu_reg_dump 195 196declare_cpu_ops cortex_a77, CORTEX_A77_MIDR, \ 197 cortex_a77_reset_func, \ 198 cortex_a77_core_pwr_dwn 199