1 /* 2 * Copyright (c) 2013-2025, Arm Limited and Contributors. All rights reserved. 3 * Copyright (c) 2022, NVIDIA Corporation. All rights reserved. 4 * 5 * SPDX-License-Identifier: BSD-3-Clause 6 */ 7 8 #include <assert.h> 9 #include <stdbool.h> 10 #include <string.h> 11 12 #include <platform_def.h> 13 14 #include <arch.h> 15 #include <arch_helpers.h> 16 #include <arch_features.h> 17 #include <bl31/interrupt_mgmt.h> 18 #include <common/bl_common.h> 19 #include <common/debug.h> 20 #include <context.h> 21 #include <drivers/arm/gicv3.h> 22 #include <lib/cpus/cpu_ops.h> 23 #include <lib/cpus/errata.h> 24 #include <lib/el3_runtime/context_mgmt.h> 25 #include <lib/el3_runtime/cpu_data.h> 26 #include <lib/el3_runtime/pubsub_events.h> 27 #include <lib/extensions/amu.h> 28 #include <lib/extensions/brbe.h> 29 #include <lib/extensions/debug_v8p9.h> 30 #include <lib/extensions/fgt2.h> 31 #include <lib/extensions/fpmr.h> 32 #include <lib/extensions/mpam.h> 33 #include <lib/extensions/pmuv3.h> 34 #include <lib/extensions/sme.h> 35 #include <lib/extensions/spe.h> 36 #include <lib/extensions/sve.h> 37 #include <lib/extensions/sysreg128.h> 38 #include <lib/extensions/sys_reg_trace.h> 39 #include <lib/extensions/tcr2.h> 40 #include <lib/extensions/trbe.h> 41 #include <lib/extensions/trf.h> 42 #include <lib/utils.h> 43 44 #if ENABLE_FEAT_TWED 45 /* Make sure delay value fits within the range(0-15) */ 46 CASSERT(((TWED_DELAY & ~SCR_TWEDEL_MASK) == 0U), assert_twed_delay_value_check); 47 #endif /* ENABLE_FEAT_TWED */ 48 49 per_world_context_t per_world_context[CPU_DATA_CONTEXT_NUM]; 50 static bool has_secure_perworld_init; 51 52 static void manage_extensions_nonsecure(cpu_context_t *ctx); 53 static void manage_extensions_secure(cpu_context_t *ctx); 54 static void manage_extensions_secure_per_world(void); 55 56 #if ((IMAGE_BL1) || (IMAGE_BL31 && (!CTX_INCLUDE_EL2_REGS))) 57 static void setup_el1_context(cpu_context_t *ctx, const struct entry_point_info *ep) 58 { 59 u_register_t sctlr_elx, actlr_elx; 60 61 /* 62 * Initialise SCTLR_EL1 to the reset value corresponding to the target 63 * execution state setting all fields rather than relying on the hw. 64 * Some fields have architecturally UNKNOWN reset values and these are 65 * set to zero. 66 * 67 * SCTLR.EE: Endianness is taken from the entrypoint attributes. 68 * 69 * SCTLR.M, SCTLR.C and SCTLR.I: These fields must be zero (as 70 * required by PSCI specification) 71 */ 72 sctlr_elx = (EP_GET_EE(ep->h.attr) != 0U) ? SCTLR_EE_BIT : 0UL; 73 if (GET_RW(ep->spsr) == MODE_RW_64) { 74 sctlr_elx |= SCTLR_EL1_RES1; 75 } else { 76 /* 77 * If the target execution state is AArch32 then the following 78 * fields need to be set. 79 * 80 * SCTRL_EL1.nTWE: Set to one so that EL0 execution of WFE 81 * instructions are not trapped to EL1. 82 * 83 * SCTLR_EL1.nTWI: Set to one so that EL0 execution of WFI 84 * instructions are not trapped to EL1. 85 * 86 * SCTLR_EL1.CP15BEN: Set to one to enable EL0 execution of the 87 * CP15DMB, CP15DSB, and CP15ISB instructions. 88 */ 89 sctlr_elx |= SCTLR_AARCH32_EL1_RES1 | SCTLR_CP15BEN_BIT 90 | SCTLR_NTWI_BIT | SCTLR_NTWE_BIT; 91 } 92 93 /* 94 * If workaround of errata 764081 for Cortex-A75 is used then set 95 * SCTLR_EL1.IESB to enable Implicit Error Synchronization Barrier. 96 */ 97 if (errata_a75_764081_applies()) { 98 sctlr_elx |= SCTLR_IESB_BIT; 99 } 100 101 /* Store the initialised SCTLR_EL1 value in the cpu_context */ 102 write_ctx_sctlr_el1_reg_errata(ctx, sctlr_elx); 103 104 /* 105 * Base the context ACTLR_EL1 on the current value, as it is 106 * implementation defined. The context restore process will write 107 * the value from the context to the actual register and can cause 108 * problems for processor cores that don't expect certain bits to 109 * be zero. 110 */ 111 actlr_elx = read_actlr_el1(); 112 write_el1_ctx_common(get_el1_sysregs_ctx(ctx), actlr_el1, actlr_elx); 113 } 114 #endif /* (IMAGE_BL1) || (IMAGE_BL31 && (!CTX_INCLUDE_EL2_REGS)) */ 115 116 /****************************************************************************** 117 * This function performs initializations that are specific to SECURE state 118 * and updates the cpu context specified by 'ctx'. 119 *****************************************************************************/ 120 static void setup_secure_context(cpu_context_t *ctx, const struct entry_point_info *ep) 121 { 122 u_register_t scr_el3; 123 el3_state_t *state; 124 125 state = get_el3state_ctx(ctx); 126 scr_el3 = read_ctx_reg(state, CTX_SCR_EL3); 127 128 #if defined(IMAGE_BL31) && !defined(SPD_spmd) 129 /* 130 * SCR_EL3.IRQ, SCR_EL3.FIQ: Enable the physical FIQ and IRQ routing as 131 * indicated by the interrupt routing model for BL31. 132 */ 133 scr_el3 |= get_scr_el3_from_routing_model(SECURE); 134 #endif 135 136 /* Allow access to Allocation Tags when FEAT_MTE2 is implemented and enabled. */ 137 if (is_feat_mte2_supported()) { 138 scr_el3 |= SCR_ATA_BIT; 139 } 140 141 write_ctx_reg(state, CTX_SCR_EL3, scr_el3); 142 143 /* 144 * Initialize EL1 context registers unless SPMC is running 145 * at S-EL2. 146 */ 147 #if (!SPMD_SPM_AT_SEL2) 148 setup_el1_context(ctx, ep); 149 #endif 150 151 manage_extensions_secure(ctx); 152 153 /** 154 * manage_extensions_secure_per_world api has to be executed once, 155 * as the registers getting initialised, maintain constant value across 156 * all the cpus for the secure world. 157 * Henceforth, this check ensures that the registers are initialised once 158 * and avoids re-initialization from multiple cores. 159 */ 160 if (!has_secure_perworld_init) { 161 manage_extensions_secure_per_world(); 162 } 163 } 164 165 #if ENABLE_RME 166 /****************************************************************************** 167 * This function performs initializations that are specific to REALM state 168 * and updates the cpu context specified by 'ctx'. 169 *****************************************************************************/ 170 static void setup_realm_context(cpu_context_t *ctx, const struct entry_point_info *ep) 171 { 172 u_register_t scr_el3; 173 el3_state_t *state; 174 175 state = get_el3state_ctx(ctx); 176 scr_el3 = read_ctx_reg(state, CTX_SCR_EL3); 177 178 scr_el3 |= SCR_NS_BIT | SCR_NSE_BIT; 179 180 /* CSV2 version 2 and above */ 181 if (is_feat_csv2_2_supported()) { 182 /* Enable access to the SCXTNUM_ELx registers. */ 183 scr_el3 |= SCR_EnSCXT_BIT; 184 } 185 186 if (is_feat_sctlr2_supported()) { 187 /* Set the SCTLR2En bit in SCR_EL3 to enable access to 188 * SCTLR2_ELx registers. 189 */ 190 scr_el3 |= SCR_SCTLR2En_BIT; 191 } 192 193 write_ctx_reg(state, CTX_SCR_EL3, scr_el3); 194 195 if (is_feat_fgt2_supported()) { 196 fgt2_enable(ctx); 197 } 198 199 if (is_feat_debugv8p9_supported()) { 200 debugv8p9_extended_bp_wp_enable(ctx); 201 } 202 203 204 } 205 #endif /* ENABLE_RME */ 206 207 /****************************************************************************** 208 * This function performs initializations that are specific to NON-SECURE state 209 * and updates the cpu context specified by 'ctx'. 210 *****************************************************************************/ 211 static void setup_ns_context(cpu_context_t *ctx, const struct entry_point_info *ep) 212 { 213 u_register_t scr_el3; 214 el3_state_t *state; 215 216 state = get_el3state_ctx(ctx); 217 scr_el3 = read_ctx_reg(state, CTX_SCR_EL3); 218 219 /* SCR_NS: Set the NS bit */ 220 scr_el3 |= SCR_NS_BIT; 221 222 /* Allow access to Allocation Tags when FEAT_MTE2 is implemented and enabled. */ 223 if (is_feat_mte2_supported()) { 224 scr_el3 |= SCR_ATA_BIT; 225 } 226 227 #if !CTX_INCLUDE_PAUTH_REGS 228 /* 229 * Pointer Authentication feature, if present, is always enabled by default 230 * for Non secure lower exception levels. We do not have an explicit 231 * flag to set it. 232 * CTX_INCLUDE_PAUTH_REGS flag, is explicitly used to enable for lower 233 * exception levels of secure and realm worlds. 234 * 235 * To prevent the leakage between the worlds during world switch, 236 * we enable it only for the non-secure world. 237 * 238 * If the Secure/realm world wants to use pointer authentication, 239 * CTX_INCLUDE_PAUTH_REGS must be explicitly set to 1, in which case 240 * it will be enabled globally for all the contexts. 241 * 242 * SCR_EL3.API: Set to one to not trap any PAuth instructions at ELs 243 * other than EL3 244 * 245 * SCR_EL3.APK: Set to one to not trap any PAuth key values at ELs other 246 * than EL3 247 */ 248 if (is_armv8_3_pauth_present()) { 249 scr_el3 |= SCR_API_BIT | SCR_APK_BIT; 250 } 251 #endif /* CTX_INCLUDE_PAUTH_REGS */ 252 253 #if HANDLE_EA_EL3_FIRST_NS 254 /* SCR_EL3.EA: Route External Abort and SError Interrupt to EL3. */ 255 scr_el3 |= SCR_EA_BIT; 256 #endif 257 258 #if RAS_TRAP_NS_ERR_REC_ACCESS 259 /* 260 * SCR_EL3.TERR: Trap Error record accesses. Accesses to the RAS ERR 261 * and RAS ERX registers from EL1 and EL2(from any security state) 262 * are trapped to EL3. 263 * Set here to trap only for NS EL1/EL2 264 */ 265 scr_el3 |= SCR_TERR_BIT; 266 #endif 267 268 /* CSV2 version 2 and above */ 269 if (is_feat_csv2_2_supported()) { 270 /* Enable access to the SCXTNUM_ELx registers. */ 271 scr_el3 |= SCR_EnSCXT_BIT; 272 } 273 274 #ifdef IMAGE_BL31 275 /* 276 * SCR_EL3.IRQ, SCR_EL3.FIQ: Enable the physical FIQ and IRQ routing as 277 * indicated by the interrupt routing model for BL31. 278 */ 279 scr_el3 |= get_scr_el3_from_routing_model(NON_SECURE); 280 #endif 281 282 if (is_feat_the_supported()) { 283 /* Set the RCWMASKEn bit in SCR_EL3 to enable access to 284 * RCWMASK_EL1 and RCWSMASK_EL1 registers. 285 */ 286 scr_el3 |= SCR_RCWMASKEn_BIT; 287 } 288 289 if (is_feat_sctlr2_supported()) { 290 /* Set the SCTLR2En bit in SCR_EL3 to enable access to 291 * SCTLR2_ELx registers. 292 */ 293 scr_el3 |= SCR_SCTLR2En_BIT; 294 } 295 296 if (is_feat_d128_supported()) { 297 /* Set the D128En bit in SCR_EL3 to enable access to 128-bit 298 * versions of TTBR0_EL1, TTBR1_EL1, RCWMASK_EL1, RCWSMASK_EL1, 299 * PAR_EL1 and TTBR1_EL2, TTBR0_EL2 and VTTBR_EL2 registers. 300 */ 301 scr_el3 |= SCR_D128En_BIT; 302 } 303 304 if (is_feat_fpmr_supported()) { 305 /* Set the EnFPM bit in SCR_EL3 to enable access to FPMR 306 * register. 307 */ 308 scr_el3 |= SCR_EnFPM_BIT; 309 } 310 311 write_ctx_reg(state, CTX_SCR_EL3, scr_el3); 312 313 /* Initialize EL2 context registers */ 314 #if (CTX_INCLUDE_EL2_REGS && IMAGE_BL31) 315 316 /* 317 * Initialize SCTLR_EL2 context register with reset value. 318 */ 319 write_el2_ctx_common(get_el2_sysregs_ctx(ctx), sctlr_el2, SCTLR_EL2_RES1); 320 321 if (is_feat_hcx_supported()) { 322 /* 323 * Initialize register HCRX_EL2 with its init value. 324 * As the value of HCRX_EL2 is UNKNOWN on reset, there is a 325 * chance that this can lead to unexpected behavior in lower 326 * ELs that have not been updated since the introduction of 327 * this feature if not properly initialized, especially when 328 * it comes to those bits that enable/disable traps. 329 */ 330 write_el2_ctx_hcx(get_el2_sysregs_ctx(ctx), hcrx_el2, 331 HCRX_EL2_INIT_VAL); 332 } 333 334 if (is_feat_fgt_supported()) { 335 /* 336 * Initialize HFG*_EL2 registers with a default value so legacy 337 * systems unaware of FEAT_FGT do not get trapped due to their lack 338 * of initialization for this feature. 339 */ 340 write_el2_ctx_fgt(get_el2_sysregs_ctx(ctx), hfgitr_el2, 341 HFGITR_EL2_INIT_VAL); 342 write_el2_ctx_fgt(get_el2_sysregs_ctx(ctx), hfgrtr_el2, 343 HFGRTR_EL2_INIT_VAL); 344 write_el2_ctx_fgt(get_el2_sysregs_ctx(ctx), hfgwtr_el2, 345 HFGWTR_EL2_INIT_VAL); 346 } 347 #else 348 /* Initialize EL1 context registers */ 349 setup_el1_context(ctx, ep); 350 #endif /* (CTX_INCLUDE_EL2_REGS && IMAGE_BL31) */ 351 352 manage_extensions_nonsecure(ctx); 353 } 354 355 /******************************************************************************* 356 * The following function performs initialization of the cpu_context 'ctx' 357 * for first use that is common to all security states, and sets the 358 * initial entrypoint state as specified by the entry_point_info structure. 359 * 360 * The EE and ST attributes are used to configure the endianness and secure 361 * timer availability for the new execution context. 362 ******************************************************************************/ 363 static void setup_context_common(cpu_context_t *ctx, const entry_point_info_t *ep) 364 { 365 u_register_t scr_el3; 366 u_register_t mdcr_el3; 367 el3_state_t *state; 368 gp_regs_t *gp_regs; 369 370 state = get_el3state_ctx(ctx); 371 372 /* Clear any residual register values from the context */ 373 zeromem(ctx, sizeof(*ctx)); 374 375 /* 376 * The lower-EL context is zeroed so that no stale values leak to a world. 377 * It is assumed that an all-zero lower-EL context is good enough for it 378 * to boot correctly. However, there are very few registers where this 379 * is not true and some values need to be recreated. 380 */ 381 #if (CTX_INCLUDE_EL2_REGS && IMAGE_BL31) 382 el2_sysregs_t *el2_ctx = get_el2_sysregs_ctx(ctx); 383 384 /* 385 * These bits are set in the gicv3 driver. Losing them (especially the 386 * SRE bit) is problematic for all worlds. Henceforth recreate them. 387 */ 388 u_register_t icc_sre_el2_val = ICC_SRE_DIB_BIT | ICC_SRE_DFB_BIT | 389 ICC_SRE_EN_BIT | ICC_SRE_SRE_BIT; 390 write_el2_ctx_common(el2_ctx, icc_sre_el2, icc_sre_el2_val); 391 392 /* 393 * The actlr_el2 register can be initialized in platform's reset handler 394 * and it may contain access control bits (e.g. CLUSTERPMUEN bit). 395 */ 396 write_el2_ctx_common(el2_ctx, actlr_el2, read_actlr_el2()); 397 #endif /* (CTX_INCLUDE_EL2_REGS && IMAGE_BL31) */ 398 399 /* Start with a clean SCR_EL3 copy as all relevant values are set */ 400 scr_el3 = SCR_RESET_VAL; 401 402 /* 403 * SCR_EL3.TWE: Set to zero so that execution of WFE instructions at 404 * EL2, EL1 and EL0 are not trapped to EL3. 405 * 406 * SCR_EL3.TWI: Set to zero so that execution of WFI instructions at 407 * EL2, EL1 and EL0 are not trapped to EL3. 408 * 409 * SCR_EL3.SMD: Set to zero to enable SMC calls at EL1 and above, from 410 * both Security states and both Execution states. 411 * 412 * SCR_EL3.SIF: Set to one to disable secure instruction execution from 413 * Non-secure memory. 414 */ 415 scr_el3 &= ~(SCR_TWE_BIT | SCR_TWI_BIT | SCR_SMD_BIT); 416 417 scr_el3 |= SCR_SIF_BIT; 418 419 /* 420 * SCR_EL3.RW: Set the execution state, AArch32 or AArch64, for next 421 * Exception level as specified by SPSR. 422 */ 423 if (GET_RW(ep->spsr) == MODE_RW_64) { 424 scr_el3 |= SCR_RW_BIT; 425 } 426 427 /* 428 * SCR_EL3.ST: Traps Secure EL1 accesses to the Counter-timer Physical 429 * Secure timer registers to EL3, from AArch64 state only, if specified 430 * by the entrypoint attributes. If SEL2 is present and enabled, the ST 431 * bit always behaves as 1 (i.e. secure physical timer register access 432 * is not trapped) 433 */ 434 if (EP_GET_ST(ep->h.attr) != 0U) { 435 scr_el3 |= SCR_ST_BIT; 436 } 437 438 /* 439 * If FEAT_HCX is enabled, enable access to HCRX_EL2 by setting 440 * SCR_EL3.HXEn. 441 */ 442 if (is_feat_hcx_supported()) { 443 scr_el3 |= SCR_HXEn_BIT; 444 } 445 446 /* 447 * If FEAT_LS64_ACCDATA is enabled, enable access to ACCDATA_EL1 by 448 * setting SCR_EL3.ADEn and allow the ST64BV0 instruction by setting 449 * SCR_EL3.EnAS0. 450 */ 451 if (is_feat_ls64_accdata_supported()) { 452 scr_el3 |= SCR_ADEn_BIT | SCR_EnAS0_BIT; 453 } 454 455 /* 456 * If FEAT_RNG_TRAP is enabled, all reads of the RNDR and RNDRRS 457 * registers are trapped to EL3. 458 */ 459 if (is_feat_rng_trap_supported()) { 460 scr_el3 |= SCR_TRNDR_BIT; 461 } 462 463 #if FAULT_INJECTION_SUPPORT 464 /* Enable fault injection from lower ELs */ 465 scr_el3 |= SCR_FIEN_BIT; 466 #endif 467 468 #if CTX_INCLUDE_PAUTH_REGS 469 /* 470 * Enable Pointer Authentication globally for all the worlds. 471 * 472 * SCR_EL3.API: Set to one to not trap any PAuth instructions at ELs 473 * other than EL3 474 * 475 * SCR_EL3.APK: Set to one to not trap any PAuth key values at ELs other 476 * than EL3 477 */ 478 if (is_armv8_3_pauth_present()) { 479 scr_el3 |= SCR_API_BIT | SCR_APK_BIT; 480 } 481 #endif /* CTX_INCLUDE_PAUTH_REGS */ 482 483 /* 484 * SCR_EL3.TCR2EN: Enable access to TCR2_ELx for AArch64 if present. 485 */ 486 if (is_feat_tcr2_supported() && (GET_RW(ep->spsr) == MODE_RW_64)) { 487 scr_el3 |= SCR_TCR2EN_BIT; 488 } 489 490 /* 491 * SCR_EL3.PIEN: Enable permission indirection and overlay 492 * registers for AArch64 if present. 493 */ 494 if (is_feat_sxpie_supported() || is_feat_sxpoe_supported()) { 495 scr_el3 |= SCR_PIEN_BIT; 496 } 497 498 /* 499 * SCR_EL3.GCSEn: Enable GCS registers for AArch64 if present. 500 */ 501 if ((is_feat_gcs_supported()) && (GET_RW(ep->spsr) == MODE_RW_64)) { 502 scr_el3 |= SCR_GCSEn_BIT; 503 } 504 505 /* 506 * SCR_EL3.HCE: Enable HVC instructions if next execution state is 507 * AArch64 and next EL is EL2, or if next execution state is AArch32 and 508 * next mode is Hyp. 509 * SCR_EL3.FGTEn: Enable Fine Grained Virtualization Traps under the 510 * same conditions as HVC instructions and when the processor supports 511 * ARMv8.6-FGT. 512 * SCR_EL3.ECVEn: Enable Enhanced Counter Virtualization (ECV) 513 * CNTPOFF_EL2 register under the same conditions as HVC instructions 514 * and when the processor supports ECV. 515 */ 516 if (((GET_RW(ep->spsr) == MODE_RW_64) && (GET_EL(ep->spsr) == MODE_EL2)) 517 || ((GET_RW(ep->spsr) != MODE_RW_64) 518 && (GET_M32(ep->spsr) == MODE32_hyp))) { 519 scr_el3 |= SCR_HCE_BIT; 520 521 if (is_feat_fgt_supported()) { 522 scr_el3 |= SCR_FGTEN_BIT; 523 } 524 525 if (is_feat_ecv_supported()) { 526 scr_el3 |= SCR_ECVEN_BIT; 527 } 528 } 529 530 /* Enable WFE trap delay in SCR_EL3 if supported and configured */ 531 if (is_feat_twed_supported()) { 532 /* Set delay in SCR_EL3 */ 533 scr_el3 &= ~(SCR_TWEDEL_MASK << SCR_TWEDEL_SHIFT); 534 scr_el3 |= ((TWED_DELAY & SCR_TWEDEL_MASK) 535 << SCR_TWEDEL_SHIFT); 536 537 /* Enable WFE delay */ 538 scr_el3 |= SCR_TWEDEn_BIT; 539 } 540 541 #if IMAGE_BL31 && defined(SPD_spmd) && SPMD_SPM_AT_SEL2 542 /* Enable S-EL2 if FEAT_SEL2 is implemented for all the contexts. */ 543 if (is_feat_sel2_supported()) { 544 scr_el3 |= SCR_EEL2_BIT; 545 } 546 #endif /* (IMAGE_BL31 && defined(SPD_spmd) && SPMD_SPM_AT_SEL2) */ 547 548 /* 549 * Populate EL3 state so that we've the right context 550 * before doing ERET 551 */ 552 write_ctx_reg(state, CTX_SCR_EL3, scr_el3); 553 write_ctx_reg(state, CTX_ELR_EL3, ep->pc); 554 write_ctx_reg(state, CTX_SPSR_EL3, ep->spsr); 555 556 /* Start with a clean MDCR_EL3 copy as all relevant values are set */ 557 mdcr_el3 = MDCR_EL3_RESET_VAL; 558 559 /* --------------------------------------------------------------------- 560 * Initialise MDCR_EL3, setting all fields rather than relying on hw. 561 * Some fields are architecturally UNKNOWN on reset. 562 * 563 * MDCR_EL3.SDD: Set to one to disable AArch64 Secure self-hosted debug. 564 * Debug exceptions, other than Breakpoint Instruction exceptions, are 565 * disabled from all ELs in Secure state. 566 * 567 * MDCR_EL3.SPD32: Set to 0b10 to disable AArch32 Secure self-hosted 568 * privileged debug from S-EL1. 569 * 570 * MDCR_EL3.TDOSA: Set to zero so that EL2 and EL2 System register 571 * access to the powerdown debug registers do not trap to EL3. 572 * 573 * MDCR_EL3.TDA: Set to zero to allow EL0, EL1 and EL2 access to the 574 * debug registers, other than those registers that are controlled by 575 * MDCR_EL3.TDOSA. 576 */ 577 mdcr_el3 |= ((MDCR_SDD_BIT | MDCR_SPD32(MDCR_SPD32_DISABLE)) 578 & ~(MDCR_TDA_BIT | MDCR_TDOSA_BIT)) ; 579 write_ctx_reg(state, CTX_MDCR_EL3, mdcr_el3); 580 581 #if IMAGE_BL31 582 /* Enable FEAT_TRF for Non-Secure and prohibit for Secure state. */ 583 if (is_feat_trf_supported()) { 584 trf_enable(ctx); 585 } 586 587 pmuv3_enable(ctx); 588 #endif /* IMAGE_BL31 */ 589 590 /* 591 * Store the X0-X7 value from the entrypoint into the context 592 * Use memcpy as we are in control of the layout of the structures 593 */ 594 gp_regs = get_gpregs_ctx(ctx); 595 memcpy(gp_regs, (void *)&ep->args, sizeof(aapcs64_params_t)); 596 } 597 598 /******************************************************************************* 599 * Context management library initialization routine. This library is used by 600 * runtime services to share pointers to 'cpu_context' structures for secure 601 * non-secure and realm states. Management of the structures and their associated 602 * memory is not done by the context management library e.g. the PSCI service 603 * manages the cpu context used for entry from and exit to the non-secure state. 604 * The Secure payload dispatcher service manages the context(s) corresponding to 605 * the secure state. It also uses this library to get access to the non-secure 606 * state cpu context pointers. 607 * Lastly, this library provides the API to make SP_EL3 point to the cpu context 608 * which will be used for programming an entry into a lower EL. The same context 609 * will be used to save state upon exception entry from that EL. 610 ******************************************************************************/ 611 void __init cm_init(void) 612 { 613 /* 614 * The context management library has only global data to initialize, but 615 * that will be done when the BSS is zeroed out. 616 */ 617 } 618 619 /******************************************************************************* 620 * This is the high-level function used to initialize the cpu_context 'ctx' for 621 * first use. It performs initializations that are common to all security states 622 * and initializations specific to the security state specified in 'ep' 623 ******************************************************************************/ 624 void cm_setup_context(cpu_context_t *ctx, const entry_point_info_t *ep) 625 { 626 unsigned int security_state; 627 628 assert(ctx != NULL); 629 630 /* 631 * Perform initializations that are common 632 * to all security states 633 */ 634 setup_context_common(ctx, ep); 635 636 security_state = GET_SECURITY_STATE(ep->h.attr); 637 638 /* Perform security state specific initializations */ 639 switch (security_state) { 640 case SECURE: 641 setup_secure_context(ctx, ep); 642 break; 643 #if ENABLE_RME 644 case REALM: 645 setup_realm_context(ctx, ep); 646 break; 647 #endif 648 case NON_SECURE: 649 setup_ns_context(ctx, ep); 650 break; 651 default: 652 ERROR("Invalid security state\n"); 653 panic(); 654 break; 655 } 656 } 657 658 /******************************************************************************* 659 * Enable architecture extensions for EL3 execution. This function only updates 660 * registers in-place which are expected to either never change or be 661 * overwritten by el3_exit. 662 ******************************************************************************/ 663 #if IMAGE_BL31 664 void cm_manage_extensions_el3(void) 665 { 666 if (is_feat_amu_supported()) { 667 amu_init_el3(); 668 } 669 670 if (is_feat_sme_supported()) { 671 sme_init_el3(); 672 } 673 674 pmuv3_init_el3(); 675 } 676 #endif /* IMAGE_BL31 */ 677 678 /****************************************************************************** 679 * Function to initialise the registers with the RESET values in the context 680 * memory, which are maintained per world. 681 ******************************************************************************/ 682 #if IMAGE_BL31 683 void cm_el3_arch_init_per_world(per_world_context_t *per_world_ctx) 684 { 685 /* 686 * Initialise CPTR_EL3, setting all fields rather than relying on hw. 687 * 688 * CPTR_EL3.TFP: Set to zero so that accesses to the V- or Z- registers 689 * by Advanced SIMD, floating-point or SVE instructions (if 690 * implemented) do not trap to EL3. 691 * 692 * CPTR_EL3.TCPAC: Set to zero so that accesses to CPACR_EL1, 693 * CPTR_EL2,CPACR, or HCPTR do not trap to EL3. 694 */ 695 uint64_t cptr_el3 = CPTR_EL3_RESET_VAL & ~(TCPAC_BIT | TFP_BIT); 696 697 per_world_ctx->ctx_cptr_el3 = cptr_el3; 698 699 /* 700 * Initialize MPAM3_EL3 to its default reset value 701 * 702 * MPAM3_EL3_RESET_VAL sets the MPAM3_EL3.TRAPLOWER bit that forces 703 * all lower ELn MPAM3_EL3 register access to, trap to EL3 704 */ 705 706 per_world_ctx->ctx_mpam3_el3 = MPAM3_EL3_RESET_VAL; 707 } 708 #endif /* IMAGE_BL31 */ 709 710 /******************************************************************************* 711 * Initialise per_world_context for Non-Secure world. 712 * This function enables the architecture extensions, which have same value 713 * across the cores for the non-secure world. 714 ******************************************************************************/ 715 #if IMAGE_BL31 716 void manage_extensions_nonsecure_per_world(void) 717 { 718 cm_el3_arch_init_per_world(&per_world_context[CPU_CONTEXT_NS]); 719 720 if (is_feat_sme_supported()) { 721 sme_enable_per_world(&per_world_context[CPU_CONTEXT_NS]); 722 } 723 724 if (is_feat_sve_supported()) { 725 sve_enable_per_world(&per_world_context[CPU_CONTEXT_NS]); 726 } 727 728 if (is_feat_amu_supported()) { 729 amu_enable_per_world(&per_world_context[CPU_CONTEXT_NS]); 730 } 731 732 if (is_feat_sys_reg_trace_supported()) { 733 sys_reg_trace_enable_per_world(&per_world_context[CPU_CONTEXT_NS]); 734 } 735 736 if (is_feat_mpam_supported()) { 737 mpam_enable_per_world(&per_world_context[CPU_CONTEXT_NS]); 738 } 739 740 if (is_feat_fpmr_supported()) { 741 fpmr_enable_per_world(&per_world_context[CPU_CONTEXT_NS]); 742 } 743 } 744 #endif /* IMAGE_BL31 */ 745 746 /******************************************************************************* 747 * Initialise per_world_context for Secure world. 748 * This function enables the architecture extensions, which have same value 749 * across the cores for the secure world. 750 ******************************************************************************/ 751 static void manage_extensions_secure_per_world(void) 752 { 753 #if IMAGE_BL31 754 cm_el3_arch_init_per_world(&per_world_context[CPU_CONTEXT_SECURE]); 755 756 if (is_feat_sme_supported()) { 757 758 if (ENABLE_SME_FOR_SWD) { 759 /* 760 * Enable SME, SVE, FPU/SIMD in secure context, SPM must ensure 761 * SME, SVE, and FPU/SIMD context properly managed. 762 */ 763 sme_enable_per_world(&per_world_context[CPU_CONTEXT_SECURE]); 764 } else { 765 /* 766 * Disable SME, SVE, FPU/SIMD in secure context so non-secure 767 * world can safely use the associated registers. 768 */ 769 sme_disable_per_world(&per_world_context[CPU_CONTEXT_SECURE]); 770 } 771 } 772 if (is_feat_sve_supported()) { 773 if (ENABLE_SVE_FOR_SWD) { 774 /* 775 * Enable SVE and FPU in secure context, SPM must ensure 776 * that the SVE and FPU register contexts are properly managed. 777 */ 778 sve_enable_per_world(&per_world_context[CPU_CONTEXT_SECURE]); 779 } else { 780 /* 781 * Disable SVE and FPU in secure context so non-secure world 782 * can safely use them. 783 */ 784 sve_disable_per_world(&per_world_context[CPU_CONTEXT_SECURE]); 785 } 786 } 787 788 /* NS can access this but Secure shouldn't */ 789 if (is_feat_sys_reg_trace_supported()) { 790 sys_reg_trace_disable_per_world(&per_world_context[CPU_CONTEXT_SECURE]); 791 } 792 793 has_secure_perworld_init = true; 794 #endif /* IMAGE_BL31 */ 795 } 796 797 /******************************************************************************* 798 * Enable architecture extensions on first entry to Non-secure world. 799 ******************************************************************************/ 800 static void manage_extensions_nonsecure(cpu_context_t *ctx) 801 { 802 #if IMAGE_BL31 803 if (is_feat_amu_supported()) { 804 amu_enable(ctx); 805 } 806 807 if (is_feat_sme_supported()) { 808 sme_enable(ctx); 809 } 810 811 if (is_feat_fgt2_supported()) { 812 fgt2_enable(ctx); 813 } 814 815 if (is_feat_debugv8p9_supported()) { 816 debugv8p9_extended_bp_wp_enable(ctx); 817 } 818 819 /* 820 * SPE, TRBE, and BRBE have multi-field enables that affect which world 821 * they apply to. Despite this, it is useful to ignore these for 822 * simplicity in determining the feature's per world enablement status. 823 * This is only possible when context is written per-world. Relied on 824 * by SMCCC_ARCH_FEATURE_AVAILABILITY 825 */ 826 if (is_feat_spe_supported()) { 827 spe_enable(ctx); 828 } 829 830 if (is_feat_trbe_supported()) { 831 trbe_enable(ctx); 832 } 833 834 if (is_feat_brbe_supported()) { 835 brbe_enable(ctx); 836 } 837 #endif /* IMAGE_BL31 */ 838 } 839 840 /* TODO: move to lib/extensions/pauth when it has been ported to FEAT_STATE */ 841 static __unused void enable_pauth_el2(void) 842 { 843 u_register_t hcr_el2 = read_hcr_el2(); 844 /* 845 * For Armv8.3 pointer authentication feature, disable traps to EL2 when 846 * accessing key registers or using pointer authentication instructions 847 * from lower ELs. 848 */ 849 hcr_el2 |= (HCR_API_BIT | HCR_APK_BIT); 850 851 write_hcr_el2(hcr_el2); 852 } 853 854 #if INIT_UNUSED_NS_EL2 855 /******************************************************************************* 856 * Enable architecture extensions in-place at EL2 on first entry to Non-secure 857 * world when EL2 is empty and unused. 858 ******************************************************************************/ 859 static void manage_extensions_nonsecure_el2_unused(void) 860 { 861 #if IMAGE_BL31 862 if (is_feat_spe_supported()) { 863 spe_init_el2_unused(); 864 } 865 866 if (is_feat_amu_supported()) { 867 amu_init_el2_unused(); 868 } 869 870 if (is_feat_mpam_supported()) { 871 mpam_init_el2_unused(); 872 } 873 874 if (is_feat_trbe_supported()) { 875 trbe_init_el2_unused(); 876 } 877 878 if (is_feat_sys_reg_trace_supported()) { 879 sys_reg_trace_init_el2_unused(); 880 } 881 882 if (is_feat_trf_supported()) { 883 trf_init_el2_unused(); 884 } 885 886 pmuv3_init_el2_unused(); 887 888 if (is_feat_sve_supported()) { 889 sve_init_el2_unused(); 890 } 891 892 if (is_feat_sme_supported()) { 893 sme_init_el2_unused(); 894 } 895 896 if (is_feat_mops_supported()) { 897 write_hcrx_el2(read_hcrx_el2() | HCRX_EL2_MSCEn_BIT); 898 } 899 900 #if ENABLE_PAUTH 901 enable_pauth_el2(); 902 #endif /* ENABLE_PAUTH */ 903 #endif /* IMAGE_BL31 */ 904 } 905 #endif /* INIT_UNUSED_NS_EL2 */ 906 907 /******************************************************************************* 908 * Enable architecture extensions on first entry to Secure world. 909 ******************************************************************************/ 910 static void manage_extensions_secure(cpu_context_t *ctx) 911 { 912 #if IMAGE_BL31 913 if (is_feat_sme_supported()) { 914 if (ENABLE_SME_FOR_SWD) { 915 /* 916 * Enable SME, SVE, FPU/SIMD in secure context, secure manager 917 * must ensure SME, SVE, and FPU/SIMD context properly managed. 918 */ 919 sme_init_el3(); 920 sme_enable(ctx); 921 } else { 922 /* 923 * Disable SME, SVE, FPU/SIMD in secure context so non-secure 924 * world can safely use the associated registers. 925 */ 926 sme_disable(ctx); 927 } 928 } 929 930 /* 931 * SPE and TRBE cannot be fully disabled from EL3 registers alone, only 932 * sysreg access can. In case the EL1 controls leave them active on 933 * context switch, we want the owning security state to be NS so Secure 934 * can't be DOSed. 935 */ 936 if (is_feat_spe_supported()) { 937 spe_disable(ctx); 938 } 939 940 if (is_feat_trbe_supported()) { 941 trbe_disable(ctx); 942 } 943 #endif /* IMAGE_BL31 */ 944 } 945 946 #if !IMAGE_BL1 947 /******************************************************************************* 948 * The following function initializes the cpu_context for a CPU specified by 949 * its `cpu_idx` for first use, and sets the initial entrypoint state as 950 * specified by the entry_point_info structure. 951 ******************************************************************************/ 952 void cm_init_context_by_index(unsigned int cpu_idx, 953 const entry_point_info_t *ep) 954 { 955 cpu_context_t *ctx; 956 ctx = cm_get_context_by_index(cpu_idx, GET_SECURITY_STATE(ep->h.attr)); 957 cm_setup_context(ctx, ep); 958 } 959 #endif /* !IMAGE_BL1 */ 960 961 /******************************************************************************* 962 * The following function initializes the cpu_context for the current CPU 963 * for first use, and sets the initial entrypoint state as specified by the 964 * entry_point_info structure. 965 ******************************************************************************/ 966 void cm_init_my_context(const entry_point_info_t *ep) 967 { 968 cpu_context_t *ctx; 969 ctx = cm_get_context(GET_SECURITY_STATE(ep->h.attr)); 970 cm_setup_context(ctx, ep); 971 } 972 973 /* EL2 present but unused, need to disable safely. SCTLR_EL2 can be ignored */ 974 static void init_nonsecure_el2_unused(cpu_context_t *ctx) 975 { 976 #if INIT_UNUSED_NS_EL2 977 u_register_t hcr_el2 = HCR_RESET_VAL; 978 u_register_t mdcr_el2; 979 u_register_t scr_el3; 980 981 scr_el3 = read_ctx_reg(get_el3state_ctx(ctx), CTX_SCR_EL3); 982 983 /* Set EL2 register width: Set HCR_EL2.RW to match SCR_EL3.RW */ 984 if ((scr_el3 & SCR_RW_BIT) != 0U) { 985 hcr_el2 |= HCR_RW_BIT; 986 } 987 988 write_hcr_el2(hcr_el2); 989 990 /* 991 * Initialise CPTR_EL2 setting all fields rather than relying on the hw. 992 * All fields have architecturally UNKNOWN reset values. 993 */ 994 write_cptr_el2(CPTR_EL2_RESET_VAL); 995 996 /* 997 * Initialise CNTHCTL_EL2. All fields are architecturally UNKNOWN on 998 * reset and are set to zero except for field(s) listed below. 999 * 1000 * CNTHCTL_EL2.EL1PTEN: Set to one to disable traps to Hyp mode of 1001 * Non-secure EL0 and EL1 accesses to the physical timer registers. 1002 * 1003 * CNTHCTL_EL2.EL1PCTEN: Set to one to disable traps to Hyp mode of 1004 * Non-secure EL0 and EL1 accesses to the physical counter registers. 1005 */ 1006 write_cnthctl_el2(CNTHCTL_RESET_VAL | EL1PCEN_BIT | EL1PCTEN_BIT); 1007 1008 /* 1009 * Initialise CNTVOFF_EL2 to zero as it resets to an architecturally 1010 * UNKNOWN value. 1011 */ 1012 write_cntvoff_el2(0); 1013 1014 /* 1015 * Set VPIDR_EL2 and VMPIDR_EL2 to match MIDR_EL1 and MPIDR_EL1 1016 * respectively. 1017 */ 1018 write_vpidr_el2(read_midr_el1()); 1019 write_vmpidr_el2(read_mpidr_el1()); 1020 1021 /* 1022 * Initialise VTTBR_EL2. All fields are architecturally UNKNOWN on reset. 1023 * 1024 * VTTBR_EL2.VMID: Set to zero. Even though EL1&0 stage 2 address 1025 * translation is disabled, cache maintenance operations depend on the 1026 * VMID. 1027 * 1028 * VTTBR_EL2.BADDR: Set to zero as EL1&0 stage 2 address translation is 1029 * disabled. 1030 */ 1031 write_vttbr_el2(VTTBR_RESET_VAL & 1032 ~((VTTBR_VMID_MASK << VTTBR_VMID_SHIFT) | 1033 (VTTBR_BADDR_MASK << VTTBR_BADDR_SHIFT))); 1034 1035 /* 1036 * Initialise MDCR_EL2, setting all fields rather than relying on hw. 1037 * Some fields are architecturally UNKNOWN on reset. 1038 * 1039 * MDCR_EL2.TDRA: Set to zero so that Non-secure EL0 and EL1 System 1040 * register accesses to the Debug ROM registers are not trapped to EL2. 1041 * 1042 * MDCR_EL2.TDOSA: Set to zero so that Non-secure EL1 System register 1043 * accesses to the powerdown debug registers are not trapped to EL2. 1044 * 1045 * MDCR_EL2.TDA: Set to zero so that System register accesses to the 1046 * debug registers do not trap to EL2. 1047 * 1048 * MDCR_EL2.TDE: Set to zero so that debug exceptions are not routed to 1049 * EL2. 1050 */ 1051 mdcr_el2 = MDCR_EL2_RESET_VAL & 1052 ~(MDCR_EL2_TDRA_BIT | MDCR_EL2_TDOSA_BIT | MDCR_EL2_TDA_BIT | 1053 MDCR_EL2_TDE_BIT); 1054 1055 write_mdcr_el2(mdcr_el2); 1056 1057 /* 1058 * Initialise HSTR_EL2. All fields are architecturally UNKNOWN on reset. 1059 * 1060 * HSTR_EL2.T<n>: Set all these fields to zero so that Non-secure EL0 or 1061 * EL1 accesses to System registers do not trap to EL2. 1062 */ 1063 write_hstr_el2(HSTR_EL2_RESET_VAL & ~(HSTR_EL2_T_MASK)); 1064 1065 /* 1066 * Initialise CNTHP_CTL_EL2. All fields are architecturally UNKNOWN on 1067 * reset. 1068 * 1069 * CNTHP_CTL_EL2:ENABLE: Set to zero to disable the EL2 physical timer 1070 * and prevent timer interrupts. 1071 */ 1072 write_cnthp_ctl_el2(CNTHP_CTL_RESET_VAL & ~(CNTHP_CTL_ENABLE_BIT)); 1073 1074 manage_extensions_nonsecure_el2_unused(); 1075 #endif /* INIT_UNUSED_NS_EL2 */ 1076 } 1077 1078 /******************************************************************************* 1079 * Prepare the CPU system registers for first entry into realm, secure, or 1080 * normal world. 1081 * 1082 * If execution is requested to EL2 or hyp mode, SCTLR_EL2 is initialized 1083 * If execution is requested to non-secure EL1 or svc mode, and the CPU supports 1084 * EL2 then EL2 is disabled by configuring all necessary EL2 registers. 1085 * For all entries, the EL1 registers are initialized from the cpu_context 1086 ******************************************************************************/ 1087 void cm_prepare_el3_exit(uint32_t security_state) 1088 { 1089 u_register_t sctlr_el2, scr_el3; 1090 cpu_context_t *ctx = cm_get_context(security_state); 1091 1092 assert(ctx != NULL); 1093 1094 if (security_state == NON_SECURE) { 1095 uint64_t el2_implemented = el_implemented(2); 1096 1097 scr_el3 = read_ctx_reg(get_el3state_ctx(ctx), 1098 CTX_SCR_EL3); 1099 1100 if (el2_implemented != EL_IMPL_NONE) { 1101 1102 /* 1103 * If context is not being used for EL2, initialize 1104 * HCRX_EL2 with its init value here. 1105 */ 1106 if (is_feat_hcx_supported()) { 1107 write_hcrx_el2(HCRX_EL2_INIT_VAL); 1108 } 1109 1110 /* 1111 * Initialize Fine-grained trap registers introduced 1112 * by FEAT_FGT so all traps are initially disabled when 1113 * switching to EL2 or a lower EL, preventing undesired 1114 * behavior. 1115 */ 1116 if (is_feat_fgt_supported()) { 1117 /* 1118 * Initialize HFG*_EL2 registers with a default 1119 * value so legacy systems unaware of FEAT_FGT 1120 * do not get trapped due to their lack of 1121 * initialization for this feature. 1122 */ 1123 write_hfgitr_el2(HFGITR_EL2_INIT_VAL); 1124 write_hfgrtr_el2(HFGRTR_EL2_INIT_VAL); 1125 write_hfgwtr_el2(HFGWTR_EL2_INIT_VAL); 1126 } 1127 1128 /* Condition to ensure EL2 is being used. */ 1129 if ((scr_el3 & SCR_HCE_BIT) != 0U) { 1130 /* Initialize SCTLR_EL2 register with reset value. */ 1131 sctlr_el2 = SCTLR_EL2_RES1; 1132 1133 /* 1134 * If workaround of errata 764081 for Cortex-A75 1135 * is used then set SCTLR_EL2.IESB to enable 1136 * Implicit Error Synchronization Barrier. 1137 */ 1138 if (errata_a75_764081_applies()) { 1139 sctlr_el2 |= SCTLR_IESB_BIT; 1140 } 1141 1142 write_sctlr_el2(sctlr_el2); 1143 } else { 1144 /* 1145 * (scr_el3 & SCR_HCE_BIT==0) 1146 * EL2 implemented but unused. 1147 */ 1148 init_nonsecure_el2_unused(ctx); 1149 } 1150 } 1151 } 1152 #if (!CTX_INCLUDE_EL2_REGS) 1153 /* Restore EL1 system registers, only when CTX_INCLUDE_EL2_REGS=0 */ 1154 cm_el1_sysregs_context_restore(security_state); 1155 #endif 1156 cm_set_next_eret_context(security_state); 1157 } 1158 1159 #if (CTX_INCLUDE_EL2_REGS && IMAGE_BL31) 1160 1161 static void el2_sysregs_context_save_fgt(el2_sysregs_t *ctx) 1162 { 1163 write_el2_ctx_fgt(ctx, hdfgrtr_el2, read_hdfgrtr_el2()); 1164 if (is_feat_amu_supported()) { 1165 write_el2_ctx_fgt(ctx, hafgrtr_el2, read_hafgrtr_el2()); 1166 } 1167 write_el2_ctx_fgt(ctx, hdfgwtr_el2, read_hdfgwtr_el2()); 1168 write_el2_ctx_fgt(ctx, hfgitr_el2, read_hfgitr_el2()); 1169 write_el2_ctx_fgt(ctx, hfgrtr_el2, read_hfgrtr_el2()); 1170 write_el2_ctx_fgt(ctx, hfgwtr_el2, read_hfgwtr_el2()); 1171 } 1172 1173 static void el2_sysregs_context_restore_fgt(el2_sysregs_t *ctx) 1174 { 1175 write_hdfgrtr_el2(read_el2_ctx_fgt(ctx, hdfgrtr_el2)); 1176 if (is_feat_amu_supported()) { 1177 write_hafgrtr_el2(read_el2_ctx_fgt(ctx, hafgrtr_el2)); 1178 } 1179 write_hdfgwtr_el2(read_el2_ctx_fgt(ctx, hdfgwtr_el2)); 1180 write_hfgitr_el2(read_el2_ctx_fgt(ctx, hfgitr_el2)); 1181 write_hfgrtr_el2(read_el2_ctx_fgt(ctx, hfgrtr_el2)); 1182 write_hfgwtr_el2(read_el2_ctx_fgt(ctx, hfgwtr_el2)); 1183 } 1184 1185 static void el2_sysregs_context_save_fgt2(el2_sysregs_t *ctx) 1186 { 1187 write_el2_ctx_fgt2(ctx, hdfgrtr2_el2, read_hdfgrtr2_el2()); 1188 write_el2_ctx_fgt2(ctx, hdfgwtr2_el2, read_hdfgwtr2_el2()); 1189 write_el2_ctx_fgt2(ctx, hfgitr2_el2, read_hfgitr2_el2()); 1190 write_el2_ctx_fgt2(ctx, hfgrtr2_el2, read_hfgrtr2_el2()); 1191 write_el2_ctx_fgt2(ctx, hfgwtr2_el2, read_hfgwtr2_el2()); 1192 } 1193 1194 static void el2_sysregs_context_restore_fgt2(el2_sysregs_t *ctx) 1195 { 1196 write_hdfgrtr2_el2(read_el2_ctx_fgt2(ctx, hdfgrtr2_el2)); 1197 write_hdfgwtr2_el2(read_el2_ctx_fgt2(ctx, hdfgwtr2_el2)); 1198 write_hfgitr2_el2(read_el2_ctx_fgt2(ctx, hfgitr2_el2)); 1199 write_hfgrtr2_el2(read_el2_ctx_fgt2(ctx, hfgrtr2_el2)); 1200 write_hfgwtr2_el2(read_el2_ctx_fgt2(ctx, hfgwtr2_el2)); 1201 } 1202 1203 static void el2_sysregs_context_save_mpam(el2_sysregs_t *ctx) 1204 { 1205 u_register_t mpam_idr = read_mpamidr_el1(); 1206 1207 write_el2_ctx_mpam(ctx, mpam2_el2, read_mpam2_el2()); 1208 1209 /* 1210 * The context registers that we intend to save would be part of the 1211 * PE's system register frame only if MPAMIDR_EL1.HAS_HCR == 1. 1212 */ 1213 if ((mpam_idr & MPAMIDR_HAS_HCR_BIT) == 0U) { 1214 return; 1215 } 1216 1217 /* 1218 * MPAMHCR_EL2, MPAMVPMV_EL2 and MPAMVPM0_EL2 are always present if 1219 * MPAMIDR_HAS_HCR_BIT == 1. 1220 */ 1221 write_el2_ctx_mpam(ctx, mpamhcr_el2, read_mpamhcr_el2()); 1222 write_el2_ctx_mpam(ctx, mpamvpm0_el2, read_mpamvpm0_el2()); 1223 write_el2_ctx_mpam(ctx, mpamvpmv_el2, read_mpamvpmv_el2()); 1224 1225 /* 1226 * The number of MPAMVPM registers is implementation defined, their 1227 * number is stored in the MPAMIDR_EL1 register. 1228 */ 1229 switch ((mpam_idr >> MPAMIDR_EL1_VPMR_MAX_SHIFT) & MPAMIDR_EL1_VPMR_MAX_MASK) { 1230 case 7: 1231 write_el2_ctx_mpam(ctx, mpamvpm7_el2, read_mpamvpm7_el2()); 1232 __fallthrough; 1233 case 6: 1234 write_el2_ctx_mpam(ctx, mpamvpm6_el2, read_mpamvpm6_el2()); 1235 __fallthrough; 1236 case 5: 1237 write_el2_ctx_mpam(ctx, mpamvpm5_el2, read_mpamvpm5_el2()); 1238 __fallthrough; 1239 case 4: 1240 write_el2_ctx_mpam(ctx, mpamvpm4_el2, read_mpamvpm4_el2()); 1241 __fallthrough; 1242 case 3: 1243 write_el2_ctx_mpam(ctx, mpamvpm3_el2, read_mpamvpm3_el2()); 1244 __fallthrough; 1245 case 2: 1246 write_el2_ctx_mpam(ctx, mpamvpm2_el2, read_mpamvpm2_el2()); 1247 __fallthrough; 1248 case 1: 1249 write_el2_ctx_mpam(ctx, mpamvpm1_el2, read_mpamvpm1_el2()); 1250 break; 1251 } 1252 } 1253 1254 static void el2_sysregs_context_restore_mpam(el2_sysregs_t *ctx) 1255 { 1256 u_register_t mpam_idr = read_mpamidr_el1(); 1257 1258 write_mpam2_el2(read_el2_ctx_mpam(ctx, mpam2_el2)); 1259 1260 if ((mpam_idr & MPAMIDR_HAS_HCR_BIT) == 0U) { 1261 return; 1262 } 1263 1264 write_mpamhcr_el2(read_el2_ctx_mpam(ctx, mpamhcr_el2)); 1265 write_mpamvpm0_el2(read_el2_ctx_mpam(ctx, mpamvpm0_el2)); 1266 write_mpamvpmv_el2(read_el2_ctx_mpam(ctx, mpamvpmv_el2)); 1267 1268 switch ((mpam_idr >> MPAMIDR_EL1_VPMR_MAX_SHIFT) & MPAMIDR_EL1_VPMR_MAX_MASK) { 1269 case 7: 1270 write_mpamvpm7_el2(read_el2_ctx_mpam(ctx, mpamvpm7_el2)); 1271 __fallthrough; 1272 case 6: 1273 write_mpamvpm6_el2(read_el2_ctx_mpam(ctx, mpamvpm6_el2)); 1274 __fallthrough; 1275 case 5: 1276 write_mpamvpm5_el2(read_el2_ctx_mpam(ctx, mpamvpm5_el2)); 1277 __fallthrough; 1278 case 4: 1279 write_mpamvpm4_el2(read_el2_ctx_mpam(ctx, mpamvpm4_el2)); 1280 __fallthrough; 1281 case 3: 1282 write_mpamvpm3_el2(read_el2_ctx_mpam(ctx, mpamvpm3_el2)); 1283 __fallthrough; 1284 case 2: 1285 write_mpamvpm2_el2(read_el2_ctx_mpam(ctx, mpamvpm2_el2)); 1286 __fallthrough; 1287 case 1: 1288 write_mpamvpm1_el2(read_el2_ctx_mpam(ctx, mpamvpm1_el2)); 1289 break; 1290 } 1291 } 1292 1293 /* --------------------------------------------------------------------------- 1294 * The following registers are not added: 1295 * ICH_AP0R<n>_EL2 1296 * ICH_AP1R<n>_EL2 1297 * ICH_LR<n>_EL2 1298 * 1299 * NOTE: For a system with S-EL2 present but not enabled, accessing 1300 * ICC_SRE_EL2 is undefined from EL3. To workaround this change the 1301 * SCR_EL3.NS = 1 before accessing this register. 1302 * --------------------------------------------------------------------------- 1303 */ 1304 static void el2_sysregs_context_save_gic(el2_sysregs_t *ctx, uint32_t security_state) 1305 { 1306 u_register_t scr_el3 = read_scr_el3(); 1307 1308 #if defined(SPD_spmd) && SPMD_SPM_AT_SEL2 1309 write_el2_ctx_common(ctx, icc_sre_el2, read_icc_sre_el2()); 1310 #else 1311 write_scr_el3(scr_el3 | SCR_NS_BIT); 1312 isb(); 1313 1314 write_el2_ctx_common(ctx, icc_sre_el2, read_icc_sre_el2()); 1315 1316 write_scr_el3(scr_el3); 1317 isb(); 1318 #endif 1319 write_el2_ctx_common(ctx, ich_hcr_el2, read_ich_hcr_el2()); 1320 1321 if (errata_ich_vmcr_el2_applies()) { 1322 if (security_state == SECURE) { 1323 write_scr_el3(scr_el3 & ~SCR_NS_BIT); 1324 } else { 1325 write_scr_el3(scr_el3 | SCR_NS_BIT); 1326 } 1327 isb(); 1328 } 1329 1330 write_el2_ctx_common(ctx, ich_vmcr_el2, read_ich_vmcr_el2()); 1331 1332 if (errata_ich_vmcr_el2_applies()) { 1333 write_scr_el3(scr_el3); 1334 isb(); 1335 } 1336 } 1337 1338 static void el2_sysregs_context_restore_gic(el2_sysregs_t *ctx, uint32_t security_state) 1339 { 1340 u_register_t scr_el3 = read_scr_el3(); 1341 1342 #if defined(SPD_spmd) && SPMD_SPM_AT_SEL2 1343 write_icc_sre_el2(read_el2_ctx_common(ctx, icc_sre_el2)); 1344 #else 1345 write_scr_el3(scr_el3 | SCR_NS_BIT); 1346 isb(); 1347 1348 write_icc_sre_el2(read_el2_ctx_common(ctx, icc_sre_el2)); 1349 1350 write_scr_el3(scr_el3); 1351 isb(); 1352 #endif 1353 write_ich_hcr_el2(read_el2_ctx_common(ctx, ich_hcr_el2)); 1354 1355 if (errata_ich_vmcr_el2_applies()) { 1356 if (security_state == SECURE) { 1357 write_scr_el3(scr_el3 & ~SCR_NS_BIT); 1358 } else { 1359 write_scr_el3(scr_el3 | SCR_NS_BIT); 1360 } 1361 isb(); 1362 } 1363 1364 write_ich_vmcr_el2(read_el2_ctx_common(ctx, ich_vmcr_el2)); 1365 1366 if (errata_ich_vmcr_el2_applies()) { 1367 write_scr_el3(scr_el3); 1368 isb(); 1369 } 1370 } 1371 1372 /* ----------------------------------------------------- 1373 * The following registers are not added: 1374 * AMEVCNTVOFF0<n>_EL2 1375 * AMEVCNTVOFF1<n>_EL2 1376 * ----------------------------------------------------- 1377 */ 1378 static void el2_sysregs_context_save_common(el2_sysregs_t *ctx) 1379 { 1380 write_el2_ctx_common(ctx, actlr_el2, read_actlr_el2()); 1381 write_el2_ctx_common(ctx, afsr0_el2, read_afsr0_el2()); 1382 write_el2_ctx_common(ctx, afsr1_el2, read_afsr1_el2()); 1383 write_el2_ctx_common(ctx, amair_el2, read_amair_el2()); 1384 write_el2_ctx_common(ctx, cnthctl_el2, read_cnthctl_el2()); 1385 write_el2_ctx_common(ctx, cntvoff_el2, read_cntvoff_el2()); 1386 write_el2_ctx_common(ctx, cptr_el2, read_cptr_el2()); 1387 if (CTX_INCLUDE_AARCH32_REGS) { 1388 write_el2_ctx_common(ctx, dbgvcr32_el2, read_dbgvcr32_el2()); 1389 } 1390 write_el2_ctx_common(ctx, elr_el2, read_elr_el2()); 1391 write_el2_ctx_common(ctx, esr_el2, read_esr_el2()); 1392 write_el2_ctx_common(ctx, far_el2, read_far_el2()); 1393 write_el2_ctx_common(ctx, hacr_el2, read_hacr_el2()); 1394 write_el2_ctx_common(ctx, hcr_el2, read_hcr_el2()); 1395 write_el2_ctx_common(ctx, hpfar_el2, read_hpfar_el2()); 1396 write_el2_ctx_common(ctx, hstr_el2, read_hstr_el2()); 1397 write_el2_ctx_common(ctx, mair_el2, read_mair_el2()); 1398 write_el2_ctx_common(ctx, mdcr_el2, read_mdcr_el2()); 1399 write_el2_ctx_common(ctx, sctlr_el2, read_sctlr_el2()); 1400 write_el2_ctx_common(ctx, spsr_el2, read_spsr_el2()); 1401 write_el2_ctx_common(ctx, sp_el2, read_sp_el2()); 1402 write_el2_ctx_common(ctx, tcr_el2, read_tcr_el2()); 1403 write_el2_ctx_common(ctx, tpidr_el2, read_tpidr_el2()); 1404 write_el2_ctx_common(ctx, vbar_el2, read_vbar_el2()); 1405 write_el2_ctx_common(ctx, vmpidr_el2, read_vmpidr_el2()); 1406 write_el2_ctx_common(ctx, vpidr_el2, read_vpidr_el2()); 1407 write_el2_ctx_common(ctx, vtcr_el2, read_vtcr_el2()); 1408 1409 write_el2_ctx_common_sysreg128(ctx, ttbr0_el2, read_ttbr0_el2()); 1410 write_el2_ctx_common_sysreg128(ctx, vttbr_el2, read_vttbr_el2()); 1411 } 1412 1413 static void el2_sysregs_context_restore_common(el2_sysregs_t *ctx) 1414 { 1415 write_actlr_el2(read_el2_ctx_common(ctx, actlr_el2)); 1416 write_afsr0_el2(read_el2_ctx_common(ctx, afsr0_el2)); 1417 write_afsr1_el2(read_el2_ctx_common(ctx, afsr1_el2)); 1418 write_amair_el2(read_el2_ctx_common(ctx, amair_el2)); 1419 write_cnthctl_el2(read_el2_ctx_common(ctx, cnthctl_el2)); 1420 write_cntvoff_el2(read_el2_ctx_common(ctx, cntvoff_el2)); 1421 write_cptr_el2(read_el2_ctx_common(ctx, cptr_el2)); 1422 if (CTX_INCLUDE_AARCH32_REGS) { 1423 write_dbgvcr32_el2(read_el2_ctx_common(ctx, dbgvcr32_el2)); 1424 } 1425 write_elr_el2(read_el2_ctx_common(ctx, elr_el2)); 1426 write_esr_el2(read_el2_ctx_common(ctx, esr_el2)); 1427 write_far_el2(read_el2_ctx_common(ctx, far_el2)); 1428 write_hacr_el2(read_el2_ctx_common(ctx, hacr_el2)); 1429 write_hcr_el2(read_el2_ctx_common(ctx, hcr_el2)); 1430 write_hpfar_el2(read_el2_ctx_common(ctx, hpfar_el2)); 1431 write_hstr_el2(read_el2_ctx_common(ctx, hstr_el2)); 1432 write_mair_el2(read_el2_ctx_common(ctx, mair_el2)); 1433 write_mdcr_el2(read_el2_ctx_common(ctx, mdcr_el2)); 1434 write_sctlr_el2(read_el2_ctx_common(ctx, sctlr_el2)); 1435 write_spsr_el2(read_el2_ctx_common(ctx, spsr_el2)); 1436 write_sp_el2(read_el2_ctx_common(ctx, sp_el2)); 1437 write_tcr_el2(read_el2_ctx_common(ctx, tcr_el2)); 1438 write_tpidr_el2(read_el2_ctx_common(ctx, tpidr_el2)); 1439 write_ttbr0_el2(read_el2_ctx_common(ctx, ttbr0_el2)); 1440 write_vbar_el2(read_el2_ctx_common(ctx, vbar_el2)); 1441 write_vmpidr_el2(read_el2_ctx_common(ctx, vmpidr_el2)); 1442 write_vpidr_el2(read_el2_ctx_common(ctx, vpidr_el2)); 1443 write_vtcr_el2(read_el2_ctx_common(ctx, vtcr_el2)); 1444 write_vttbr_el2(read_el2_ctx_common(ctx, vttbr_el2)); 1445 } 1446 1447 /******************************************************************************* 1448 * Save EL2 sysreg context 1449 ******************************************************************************/ 1450 void cm_el2_sysregs_context_save(uint32_t security_state) 1451 { 1452 cpu_context_t *ctx; 1453 el2_sysregs_t *el2_sysregs_ctx; 1454 1455 ctx = cm_get_context(security_state); 1456 assert(ctx != NULL); 1457 1458 el2_sysregs_ctx = get_el2_sysregs_ctx(ctx); 1459 1460 el2_sysregs_context_save_common(el2_sysregs_ctx); 1461 el2_sysregs_context_save_gic(el2_sysregs_ctx, security_state); 1462 1463 if (is_feat_mte2_supported()) { 1464 write_el2_ctx_mte2(el2_sysregs_ctx, tfsr_el2, read_tfsr_el2()); 1465 } 1466 1467 if (is_feat_mpam_supported()) { 1468 el2_sysregs_context_save_mpam(el2_sysregs_ctx); 1469 } 1470 1471 if (is_feat_fgt_supported()) { 1472 el2_sysregs_context_save_fgt(el2_sysregs_ctx); 1473 } 1474 1475 if (is_feat_fgt2_supported()) { 1476 el2_sysregs_context_save_fgt2(el2_sysregs_ctx); 1477 } 1478 1479 if (is_feat_ecv_v2_supported()) { 1480 write_el2_ctx_ecv(el2_sysregs_ctx, cntpoff_el2, read_cntpoff_el2()); 1481 } 1482 1483 if (is_feat_vhe_supported()) { 1484 write_el2_ctx_vhe(el2_sysregs_ctx, contextidr_el2, 1485 read_contextidr_el2()); 1486 write_el2_ctx_vhe_sysreg128(el2_sysregs_ctx, ttbr1_el2, read_ttbr1_el2()); 1487 } 1488 1489 if (is_feat_ras_supported()) { 1490 write_el2_ctx_ras(el2_sysregs_ctx, vdisr_el2, read_vdisr_el2()); 1491 write_el2_ctx_ras(el2_sysregs_ctx, vsesr_el2, read_vsesr_el2()); 1492 } 1493 1494 if (is_feat_nv2_supported()) { 1495 write_el2_ctx_neve(el2_sysregs_ctx, vncr_el2, read_vncr_el2()); 1496 } 1497 1498 if (is_feat_trf_supported()) { 1499 write_el2_ctx_trf(el2_sysregs_ctx, trfcr_el2, read_trfcr_el2()); 1500 } 1501 1502 if (is_feat_csv2_2_supported()) { 1503 write_el2_ctx_csv2_2(el2_sysregs_ctx, scxtnum_el2, 1504 read_scxtnum_el2()); 1505 } 1506 1507 if (is_feat_hcx_supported()) { 1508 write_el2_ctx_hcx(el2_sysregs_ctx, hcrx_el2, read_hcrx_el2()); 1509 } 1510 1511 if (is_feat_tcr2_supported()) { 1512 write_el2_ctx_tcr2(el2_sysregs_ctx, tcr2_el2, read_tcr2_el2()); 1513 } 1514 1515 if (is_feat_sxpie_supported()) { 1516 write_el2_ctx_sxpie(el2_sysregs_ctx, pire0_el2, read_pire0_el2()); 1517 write_el2_ctx_sxpie(el2_sysregs_ctx, pir_el2, read_pir_el2()); 1518 } 1519 1520 if (is_feat_sxpoe_supported()) { 1521 write_el2_ctx_sxpoe(el2_sysregs_ctx, por_el2, read_por_el2()); 1522 } 1523 1524 if (is_feat_s2pie_supported()) { 1525 write_el2_ctx_s2pie(el2_sysregs_ctx, s2pir_el2, read_s2pir_el2()); 1526 } 1527 1528 if (is_feat_gcs_supported()) { 1529 write_el2_ctx_gcs(el2_sysregs_ctx, gcscr_el2, read_gcscr_el2()); 1530 write_el2_ctx_gcs(el2_sysregs_ctx, gcspr_el2, read_gcspr_el2()); 1531 } 1532 1533 if (is_feat_sctlr2_supported()) { 1534 write_el2_ctx_sctlr2(el2_sysregs_ctx, sctlr2_el2, read_sctlr2_el2()); 1535 } 1536 } 1537 1538 /******************************************************************************* 1539 * Restore EL2 sysreg context 1540 ******************************************************************************/ 1541 void cm_el2_sysregs_context_restore(uint32_t security_state) 1542 { 1543 cpu_context_t *ctx; 1544 el2_sysregs_t *el2_sysregs_ctx; 1545 1546 ctx = cm_get_context(security_state); 1547 assert(ctx != NULL); 1548 1549 el2_sysregs_ctx = get_el2_sysregs_ctx(ctx); 1550 1551 el2_sysregs_context_restore_common(el2_sysregs_ctx); 1552 el2_sysregs_context_restore_gic(el2_sysregs_ctx, security_state); 1553 1554 if (is_feat_mte2_supported()) { 1555 write_tfsr_el2(read_el2_ctx_mte2(el2_sysregs_ctx, tfsr_el2)); 1556 } 1557 1558 if (is_feat_mpam_supported()) { 1559 el2_sysregs_context_restore_mpam(el2_sysregs_ctx); 1560 } 1561 1562 if (is_feat_fgt_supported()) { 1563 el2_sysregs_context_restore_fgt(el2_sysregs_ctx); 1564 } 1565 1566 if (is_feat_fgt2_supported()) { 1567 el2_sysregs_context_restore_fgt2(el2_sysregs_ctx); 1568 } 1569 1570 if (is_feat_ecv_v2_supported()) { 1571 write_cntpoff_el2(read_el2_ctx_ecv(el2_sysregs_ctx, cntpoff_el2)); 1572 } 1573 1574 if (is_feat_vhe_supported()) { 1575 write_contextidr_el2(read_el2_ctx_vhe(el2_sysregs_ctx, 1576 contextidr_el2)); 1577 write_ttbr1_el2(read_el2_ctx_vhe(el2_sysregs_ctx, ttbr1_el2)); 1578 } 1579 1580 if (is_feat_ras_supported()) { 1581 write_vdisr_el2(read_el2_ctx_ras(el2_sysregs_ctx, vdisr_el2)); 1582 write_vsesr_el2(read_el2_ctx_ras(el2_sysregs_ctx, vsesr_el2)); 1583 } 1584 1585 if (is_feat_nv2_supported()) { 1586 write_vncr_el2(read_el2_ctx_neve(el2_sysregs_ctx, vncr_el2)); 1587 } 1588 1589 if (is_feat_trf_supported()) { 1590 write_trfcr_el2(read_el2_ctx_trf(el2_sysregs_ctx, trfcr_el2)); 1591 } 1592 1593 if (is_feat_csv2_2_supported()) { 1594 write_scxtnum_el2(read_el2_ctx_csv2_2(el2_sysregs_ctx, 1595 scxtnum_el2)); 1596 } 1597 1598 if (is_feat_hcx_supported()) { 1599 write_hcrx_el2(read_el2_ctx_hcx(el2_sysregs_ctx, hcrx_el2)); 1600 } 1601 1602 if (is_feat_tcr2_supported()) { 1603 write_tcr2_el2(read_el2_ctx_tcr2(el2_sysregs_ctx, tcr2_el2)); 1604 } 1605 1606 if (is_feat_sxpie_supported()) { 1607 write_pire0_el2(read_el2_ctx_sxpie(el2_sysregs_ctx, pire0_el2)); 1608 write_pir_el2(read_el2_ctx_sxpie(el2_sysregs_ctx, pir_el2)); 1609 } 1610 1611 if (is_feat_sxpoe_supported()) { 1612 write_por_el2(read_el2_ctx_sxpoe(el2_sysregs_ctx, por_el2)); 1613 } 1614 1615 if (is_feat_s2pie_supported()) { 1616 write_s2pir_el2(read_el2_ctx_s2pie(el2_sysregs_ctx, s2pir_el2)); 1617 } 1618 1619 if (is_feat_gcs_supported()) { 1620 write_gcscr_el2(read_el2_ctx_gcs(el2_sysregs_ctx, gcscr_el2)); 1621 write_gcspr_el2(read_el2_ctx_gcs(el2_sysregs_ctx, gcspr_el2)); 1622 } 1623 1624 if (is_feat_sctlr2_supported()) { 1625 write_sctlr2_el2(read_el2_ctx_sctlr2(el2_sysregs_ctx, sctlr2_el2)); 1626 } 1627 } 1628 #endif /* (CTX_INCLUDE_EL2_REGS && IMAGE_BL31) */ 1629 1630 #if IMAGE_BL31 1631 /********************************************************************************* 1632 * This function allows Architecture features asymmetry among cores. 1633 * TF-A assumes that all the cores in the platform has architecture feature parity 1634 * and hence the context is setup on different core (e.g. primary sets up the 1635 * context for secondary cores).This assumption may not be true for systems where 1636 * cores are not conforming to same Arch version or there is CPU Erratum which 1637 * requires certain feature to be be disabled only on a given core. 1638 * 1639 * This function is called on secondary cores to override any disparity in context 1640 * setup by primary, this would be called during warmboot path. 1641 *********************************************************************************/ 1642 void cm_handle_asymmetric_features(void) 1643 { 1644 cpu_context_t *ctx __maybe_unused = cm_get_context(NON_SECURE); 1645 1646 assert(ctx != NULL); 1647 1648 #if ENABLE_SPE_FOR_NS == FEAT_STATE_CHECK_ASYMMETRIC 1649 if (is_feat_spe_supported()) { 1650 spe_enable(ctx); 1651 } else { 1652 spe_disable(ctx); 1653 } 1654 #endif 1655 1656 #if ERRATA_A520_2938996 || ERRATA_X4_2726228 1657 if (check_if_affected_core() == ERRATA_APPLIES) { 1658 if (is_feat_trbe_supported()) { 1659 trbe_disable(ctx); 1660 } 1661 } 1662 #endif 1663 1664 #if ENABLE_FEAT_TCR2 == FEAT_STATE_CHECK_ASYMMETRIC 1665 el3_state_t *el3_state = get_el3state_ctx(ctx); 1666 u_register_t spsr = read_ctx_reg(el3_state, CTX_SPSR_EL3); 1667 1668 if (is_feat_tcr2_supported() && (GET_RW(spsr) == MODE_RW_64)) { 1669 tcr2_enable(ctx); 1670 } else { 1671 tcr2_disable(ctx); 1672 } 1673 #endif 1674 1675 } 1676 #endif 1677 1678 /******************************************************************************* 1679 * This function is used to exit to Non-secure world. If CTX_INCLUDE_EL2_REGS 1680 * is enabled, it restores EL1 and EL2 sysreg contexts instead of directly 1681 * updating EL1 and EL2 registers. Otherwise, it calls the generic 1682 * cm_prepare_el3_exit function. 1683 ******************************************************************************/ 1684 void cm_prepare_el3_exit_ns(void) 1685 { 1686 #if IMAGE_BL31 1687 /* 1688 * Check and handle Architecture feature asymmetry among cores. 1689 * 1690 * In warmboot path secondary cores context is initialized on core which 1691 * did CPU_ON SMC call, if there is feature asymmetry in these cores handle 1692 * it in this function call. 1693 * For Symmetric cores this is an empty function. 1694 */ 1695 cm_handle_asymmetric_features(); 1696 #endif 1697 1698 #if (CTX_INCLUDE_EL2_REGS && IMAGE_BL31) 1699 #if ENABLE_ASSERTIONS 1700 cpu_context_t *ctx = cm_get_context(NON_SECURE); 1701 assert(ctx != NULL); 1702 1703 /* Assert that EL2 is used. */ 1704 u_register_t scr_el3 = read_ctx_reg(get_el3state_ctx(ctx), CTX_SCR_EL3); 1705 assert(((scr_el3 & SCR_HCE_BIT) != 0UL) && 1706 (el_implemented(2U) != EL_IMPL_NONE)); 1707 #endif /* ENABLE_ASSERTIONS */ 1708 1709 /* Restore EL2 sysreg contexts */ 1710 cm_el2_sysregs_context_restore(NON_SECURE); 1711 cm_set_next_eret_context(NON_SECURE); 1712 #else 1713 cm_prepare_el3_exit(NON_SECURE); 1714 #endif /* (CTX_INCLUDE_EL2_REGS && IMAGE_BL31) */ 1715 } 1716 1717 #if ((IMAGE_BL1) || (IMAGE_BL31 && (!CTX_INCLUDE_EL2_REGS))) 1718 /******************************************************************************* 1719 * The next set of six functions are used by runtime services to save and restore 1720 * EL1 context on the 'cpu_context' structure for the specified security state. 1721 ******************************************************************************/ 1722 static void el1_sysregs_context_save(el1_sysregs_t *ctx) 1723 { 1724 write_el1_ctx_common(ctx, spsr_el1, read_spsr_el1()); 1725 write_el1_ctx_common(ctx, elr_el1, read_elr_el1()); 1726 1727 #if (!ERRATA_SPECULATIVE_AT) 1728 write_el1_ctx_common(ctx, sctlr_el1, read_sctlr_el1()); 1729 write_el1_ctx_common(ctx, tcr_el1, read_tcr_el1()); 1730 #endif /* (!ERRATA_SPECULATIVE_AT) */ 1731 1732 write_el1_ctx_common(ctx, cpacr_el1, read_cpacr_el1()); 1733 write_el1_ctx_common(ctx, csselr_el1, read_csselr_el1()); 1734 write_el1_ctx_common(ctx, sp_el1, read_sp_el1()); 1735 write_el1_ctx_common(ctx, esr_el1, read_esr_el1()); 1736 write_el1_ctx_common(ctx, mair_el1, read_mair_el1()); 1737 write_el1_ctx_common(ctx, amair_el1, read_amair_el1()); 1738 write_el1_ctx_common(ctx, actlr_el1, read_actlr_el1()); 1739 write_el1_ctx_common(ctx, tpidr_el1, read_tpidr_el1()); 1740 write_el1_ctx_common(ctx, tpidr_el0, read_tpidr_el0()); 1741 write_el1_ctx_common(ctx, tpidrro_el0, read_tpidrro_el0()); 1742 write_el1_ctx_common(ctx, far_el1, read_far_el1()); 1743 write_el1_ctx_common(ctx, afsr0_el1, read_afsr0_el1()); 1744 write_el1_ctx_common(ctx, afsr1_el1, read_afsr1_el1()); 1745 write_el1_ctx_common(ctx, contextidr_el1, read_contextidr_el1()); 1746 write_el1_ctx_common(ctx, vbar_el1, read_vbar_el1()); 1747 write_el1_ctx_common(ctx, mdccint_el1, read_mdccint_el1()); 1748 write_el1_ctx_common(ctx, mdscr_el1, read_mdscr_el1()); 1749 1750 write_el1_ctx_common_sysreg128(ctx, par_el1, read_par_el1()); 1751 write_el1_ctx_common_sysreg128(ctx, ttbr0_el1, read_ttbr0_el1()); 1752 write_el1_ctx_common_sysreg128(ctx, ttbr1_el1, read_ttbr1_el1()); 1753 1754 if (CTX_INCLUDE_AARCH32_REGS) { 1755 /* Save Aarch32 registers */ 1756 write_el1_ctx_aarch32(ctx, spsr_abt, read_spsr_abt()); 1757 write_el1_ctx_aarch32(ctx, spsr_und, read_spsr_und()); 1758 write_el1_ctx_aarch32(ctx, spsr_irq, read_spsr_irq()); 1759 write_el1_ctx_aarch32(ctx, spsr_fiq, read_spsr_fiq()); 1760 write_el1_ctx_aarch32(ctx, dacr32_el2, read_dacr32_el2()); 1761 write_el1_ctx_aarch32(ctx, ifsr32_el2, read_ifsr32_el2()); 1762 } 1763 1764 if (NS_TIMER_SWITCH) { 1765 /* Save NS Timer registers */ 1766 write_el1_ctx_arch_timer(ctx, cntp_ctl_el0, read_cntp_ctl_el0()); 1767 write_el1_ctx_arch_timer(ctx, cntp_cval_el0, read_cntp_cval_el0()); 1768 write_el1_ctx_arch_timer(ctx, cntv_ctl_el0, read_cntv_ctl_el0()); 1769 write_el1_ctx_arch_timer(ctx, cntv_cval_el0, read_cntv_cval_el0()); 1770 write_el1_ctx_arch_timer(ctx, cntkctl_el1, read_cntkctl_el1()); 1771 } 1772 1773 if (is_feat_mte2_supported()) { 1774 write_el1_ctx_mte2(ctx, tfsre0_el1, read_tfsre0_el1()); 1775 write_el1_ctx_mte2(ctx, tfsr_el1, read_tfsr_el1()); 1776 write_el1_ctx_mte2(ctx, rgsr_el1, read_rgsr_el1()); 1777 write_el1_ctx_mte2(ctx, gcr_el1, read_gcr_el1()); 1778 } 1779 1780 if (is_feat_ras_supported()) { 1781 write_el1_ctx_ras(ctx, disr_el1, read_disr_el1()); 1782 } 1783 1784 if (is_feat_s1pie_supported()) { 1785 write_el1_ctx_s1pie(ctx, pire0_el1, read_pire0_el1()); 1786 write_el1_ctx_s1pie(ctx, pir_el1, read_pir_el1()); 1787 } 1788 1789 if (is_feat_s1poe_supported()) { 1790 write_el1_ctx_s1poe(ctx, por_el1, read_por_el1()); 1791 } 1792 1793 if (is_feat_s2poe_supported()) { 1794 write_el1_ctx_s2poe(ctx, s2por_el1, read_s2por_el1()); 1795 } 1796 1797 if (is_feat_tcr2_supported()) { 1798 write_el1_ctx_tcr2(ctx, tcr2_el1, read_tcr2_el1()); 1799 } 1800 1801 if (is_feat_trf_supported()) { 1802 write_el1_ctx_trf(ctx, trfcr_el1, read_trfcr_el1()); 1803 } 1804 1805 if (is_feat_csv2_2_supported()) { 1806 write_el1_ctx_csv2_2(ctx, scxtnum_el0, read_scxtnum_el0()); 1807 write_el1_ctx_csv2_2(ctx, scxtnum_el1, read_scxtnum_el1()); 1808 } 1809 1810 if (is_feat_gcs_supported()) { 1811 write_el1_ctx_gcs(ctx, gcscr_el1, read_gcscr_el1()); 1812 write_el1_ctx_gcs(ctx, gcscre0_el1, read_gcscre0_el1()); 1813 write_el1_ctx_gcs(ctx, gcspr_el1, read_gcspr_el1()); 1814 write_el1_ctx_gcs(ctx, gcspr_el0, read_gcspr_el0()); 1815 } 1816 1817 if (is_feat_the_supported()) { 1818 write_el1_ctx_the_sysreg128(ctx, rcwmask_el1, read_rcwmask_el1()); 1819 write_el1_ctx_the_sysreg128(ctx, rcwsmask_el1, read_rcwsmask_el1()); 1820 } 1821 1822 if (is_feat_sctlr2_supported()) { 1823 write_el1_ctx_sctlr2(ctx, sctlr2_el1, read_sctlr2_el1()); 1824 } 1825 1826 if (is_feat_ls64_accdata_supported()) { 1827 write_el1_ctx_ls64(ctx, accdata_el1, read_accdata_el1()); 1828 } 1829 } 1830 1831 static void el1_sysregs_context_restore(el1_sysregs_t *ctx) 1832 { 1833 write_spsr_el1(read_el1_ctx_common(ctx, spsr_el1)); 1834 write_elr_el1(read_el1_ctx_common(ctx, elr_el1)); 1835 1836 #if (!ERRATA_SPECULATIVE_AT) 1837 write_sctlr_el1(read_el1_ctx_common(ctx, sctlr_el1)); 1838 write_tcr_el1(read_el1_ctx_common(ctx, tcr_el1)); 1839 #endif /* (!ERRATA_SPECULATIVE_AT) */ 1840 1841 write_cpacr_el1(read_el1_ctx_common(ctx, cpacr_el1)); 1842 write_csselr_el1(read_el1_ctx_common(ctx, csselr_el1)); 1843 write_sp_el1(read_el1_ctx_common(ctx, sp_el1)); 1844 write_esr_el1(read_el1_ctx_common(ctx, esr_el1)); 1845 write_ttbr0_el1(read_el1_ctx_common(ctx, ttbr0_el1)); 1846 write_ttbr1_el1(read_el1_ctx_common(ctx, ttbr1_el1)); 1847 write_mair_el1(read_el1_ctx_common(ctx, mair_el1)); 1848 write_amair_el1(read_el1_ctx_common(ctx, amair_el1)); 1849 write_actlr_el1(read_el1_ctx_common(ctx, actlr_el1)); 1850 write_tpidr_el1(read_el1_ctx_common(ctx, tpidr_el1)); 1851 write_tpidr_el0(read_el1_ctx_common(ctx, tpidr_el0)); 1852 write_tpidrro_el0(read_el1_ctx_common(ctx, tpidrro_el0)); 1853 write_par_el1(read_el1_ctx_common(ctx, par_el1)); 1854 write_far_el1(read_el1_ctx_common(ctx, far_el1)); 1855 write_afsr0_el1(read_el1_ctx_common(ctx, afsr0_el1)); 1856 write_afsr1_el1(read_el1_ctx_common(ctx, afsr1_el1)); 1857 write_contextidr_el1(read_el1_ctx_common(ctx, contextidr_el1)); 1858 write_vbar_el1(read_el1_ctx_common(ctx, vbar_el1)); 1859 write_mdccint_el1(read_el1_ctx_common(ctx, mdccint_el1)); 1860 write_mdscr_el1(read_el1_ctx_common(ctx, mdscr_el1)); 1861 1862 if (CTX_INCLUDE_AARCH32_REGS) { 1863 /* Restore Aarch32 registers */ 1864 write_spsr_abt(read_el1_ctx_aarch32(ctx, spsr_abt)); 1865 write_spsr_und(read_el1_ctx_aarch32(ctx, spsr_und)); 1866 write_spsr_irq(read_el1_ctx_aarch32(ctx, spsr_irq)); 1867 write_spsr_fiq(read_el1_ctx_aarch32(ctx, spsr_fiq)); 1868 write_dacr32_el2(read_el1_ctx_aarch32(ctx, dacr32_el2)); 1869 write_ifsr32_el2(read_el1_ctx_aarch32(ctx, ifsr32_el2)); 1870 } 1871 1872 if (NS_TIMER_SWITCH) { 1873 /* Restore NS Timer registers */ 1874 write_cntp_ctl_el0(read_el1_ctx_arch_timer(ctx, cntp_ctl_el0)); 1875 write_cntp_cval_el0(read_el1_ctx_arch_timer(ctx, cntp_cval_el0)); 1876 write_cntv_ctl_el0(read_el1_ctx_arch_timer(ctx, cntv_ctl_el0)); 1877 write_cntv_cval_el0(read_el1_ctx_arch_timer(ctx, cntv_cval_el0)); 1878 write_cntkctl_el1(read_el1_ctx_arch_timer(ctx, cntkctl_el1)); 1879 } 1880 1881 if (is_feat_mte2_supported()) { 1882 write_tfsre0_el1(read_el1_ctx_mte2(ctx, tfsre0_el1)); 1883 write_tfsr_el1(read_el1_ctx_mte2(ctx, tfsr_el1)); 1884 write_rgsr_el1(read_el1_ctx_mte2(ctx, rgsr_el1)); 1885 write_gcr_el1(read_el1_ctx_mte2(ctx, gcr_el1)); 1886 } 1887 1888 if (is_feat_ras_supported()) { 1889 write_disr_el1(read_el1_ctx_ras(ctx, disr_el1)); 1890 } 1891 1892 if (is_feat_s1pie_supported()) { 1893 write_pire0_el1(read_el1_ctx_s1pie(ctx, pire0_el1)); 1894 write_pir_el1(read_el1_ctx_s1pie(ctx, pir_el1)); 1895 } 1896 1897 if (is_feat_s1poe_supported()) { 1898 write_por_el1(read_el1_ctx_s1poe(ctx, por_el1)); 1899 } 1900 1901 if (is_feat_s2poe_supported()) { 1902 write_s2por_el1(read_el1_ctx_s2poe(ctx, s2por_el1)); 1903 } 1904 1905 if (is_feat_tcr2_supported()) { 1906 write_tcr2_el1(read_el1_ctx_tcr2(ctx, tcr2_el1)); 1907 } 1908 1909 if (is_feat_trf_supported()) { 1910 write_trfcr_el1(read_el1_ctx_trf(ctx, trfcr_el1)); 1911 } 1912 1913 if (is_feat_csv2_2_supported()) { 1914 write_scxtnum_el0(read_el1_ctx_csv2_2(ctx, scxtnum_el0)); 1915 write_scxtnum_el1(read_el1_ctx_csv2_2(ctx, scxtnum_el1)); 1916 } 1917 1918 if (is_feat_gcs_supported()) { 1919 write_gcscr_el1(read_el1_ctx_gcs(ctx, gcscr_el1)); 1920 write_gcscre0_el1(read_el1_ctx_gcs(ctx, gcscre0_el1)); 1921 write_gcspr_el1(read_el1_ctx_gcs(ctx, gcspr_el1)); 1922 write_gcspr_el0(read_el1_ctx_gcs(ctx, gcspr_el0)); 1923 } 1924 1925 if (is_feat_the_supported()) { 1926 write_rcwmask_el1(read_el1_ctx_the(ctx, rcwmask_el1)); 1927 write_rcwsmask_el1(read_el1_ctx_the(ctx, rcwsmask_el1)); 1928 } 1929 1930 if (is_feat_sctlr2_supported()) { 1931 write_sctlr2_el1(read_el1_ctx_sctlr2(ctx, sctlr2_el1)); 1932 } 1933 1934 if (is_feat_ls64_accdata_supported()) { 1935 write_accdata_el1(read_el1_ctx_ls64(ctx, accdata_el1)); 1936 } 1937 } 1938 1939 /******************************************************************************* 1940 * The next couple of functions are used by runtime services to save and restore 1941 * EL1 context on the 'cpu_context' structure for the specified security state. 1942 ******************************************************************************/ 1943 void cm_el1_sysregs_context_save(uint32_t security_state) 1944 { 1945 cpu_context_t *ctx; 1946 1947 ctx = cm_get_context(security_state); 1948 assert(ctx != NULL); 1949 1950 el1_sysregs_context_save(get_el1_sysregs_ctx(ctx)); 1951 1952 #if IMAGE_BL31 1953 if (security_state == SECURE) 1954 PUBLISH_EVENT(cm_exited_secure_world); 1955 else 1956 PUBLISH_EVENT(cm_exited_normal_world); 1957 #endif 1958 } 1959 1960 void cm_el1_sysregs_context_restore(uint32_t security_state) 1961 { 1962 cpu_context_t *ctx; 1963 1964 ctx = cm_get_context(security_state); 1965 assert(ctx != NULL); 1966 1967 el1_sysregs_context_restore(get_el1_sysregs_ctx(ctx)); 1968 1969 #if IMAGE_BL31 1970 if (security_state == SECURE) 1971 PUBLISH_EVENT(cm_entering_secure_world); 1972 else 1973 PUBLISH_EVENT(cm_entering_normal_world); 1974 #endif 1975 } 1976 1977 #endif /* ((IMAGE_BL1) || (IMAGE_BL31 && (!CTX_INCLUDE_EL2_REGS))) */ 1978 1979 /******************************************************************************* 1980 * This function populates ELR_EL3 member of 'cpu_context' pertaining to the 1981 * given security state with the given entrypoint 1982 ******************************************************************************/ 1983 void cm_set_elr_el3(uint32_t security_state, uintptr_t entrypoint) 1984 { 1985 cpu_context_t *ctx; 1986 el3_state_t *state; 1987 1988 ctx = cm_get_context(security_state); 1989 assert(ctx != NULL); 1990 1991 /* Populate EL3 state so that ERET jumps to the correct entry */ 1992 state = get_el3state_ctx(ctx); 1993 write_ctx_reg(state, CTX_ELR_EL3, entrypoint); 1994 } 1995 1996 /******************************************************************************* 1997 * This function populates ELR_EL3 and SPSR_EL3 members of 'cpu_context' 1998 * pertaining to the given security state 1999 ******************************************************************************/ 2000 void cm_set_elr_spsr_el3(uint32_t security_state, 2001 uintptr_t entrypoint, uint32_t spsr) 2002 { 2003 cpu_context_t *ctx; 2004 el3_state_t *state; 2005 2006 ctx = cm_get_context(security_state); 2007 assert(ctx != NULL); 2008 2009 /* Populate EL3 state so that ERET jumps to the correct entry */ 2010 state = get_el3state_ctx(ctx); 2011 write_ctx_reg(state, CTX_ELR_EL3, entrypoint); 2012 write_ctx_reg(state, CTX_SPSR_EL3, spsr); 2013 } 2014 2015 /******************************************************************************* 2016 * This function updates a single bit in the SCR_EL3 member of the 'cpu_context' 2017 * pertaining to the given security state using the value and bit position 2018 * specified in the parameters. It preserves all other bits. 2019 ******************************************************************************/ 2020 void cm_write_scr_el3_bit(uint32_t security_state, 2021 uint32_t bit_pos, 2022 uint32_t value) 2023 { 2024 cpu_context_t *ctx; 2025 el3_state_t *state; 2026 u_register_t scr_el3; 2027 2028 ctx = cm_get_context(security_state); 2029 assert(ctx != NULL); 2030 2031 /* Ensure that the bit position is a valid one */ 2032 assert(((1UL << bit_pos) & SCR_VALID_BIT_MASK) != 0U); 2033 2034 /* Ensure that the 'value' is only a bit wide */ 2035 assert(value <= 1U); 2036 2037 /* 2038 * Get the SCR_EL3 value from the cpu context, clear the desired bit 2039 * and set it to its new value. 2040 */ 2041 state = get_el3state_ctx(ctx); 2042 scr_el3 = read_ctx_reg(state, CTX_SCR_EL3); 2043 scr_el3 &= ~(1UL << bit_pos); 2044 scr_el3 |= (u_register_t)value << bit_pos; 2045 write_ctx_reg(state, CTX_SCR_EL3, scr_el3); 2046 } 2047 2048 /******************************************************************************* 2049 * This function retrieves SCR_EL3 member of 'cpu_context' pertaining to the 2050 * given security state. 2051 ******************************************************************************/ 2052 u_register_t cm_get_scr_el3(uint32_t security_state) 2053 { 2054 cpu_context_t *ctx; 2055 el3_state_t *state; 2056 2057 ctx = cm_get_context(security_state); 2058 assert(ctx != NULL); 2059 2060 /* Populate EL3 state so that ERET jumps to the correct entry */ 2061 state = get_el3state_ctx(ctx); 2062 return read_ctx_reg(state, CTX_SCR_EL3); 2063 } 2064 2065 /******************************************************************************* 2066 * This function is used to program the context that's used for exception 2067 * return. This initializes the SP_EL3 to a pointer to a 'cpu_context' set for 2068 * the required security state 2069 ******************************************************************************/ 2070 void cm_set_next_eret_context(uint32_t security_state) 2071 { 2072 cpu_context_t *ctx; 2073 2074 ctx = cm_get_context(security_state); 2075 assert(ctx != NULL); 2076 2077 cm_set_next_context(ctx); 2078 } 2079