1/* 2 * Copyright (c) 2024-2025, Arm Limited. All rights reserved. 3 * 4 * SPDX-License-Identifier: BSD-3-Clause 5 */ 6 7#include <arch.h> 8#include <asm_macros.S> 9#include <common/bl_common.h> 10#include <cortex_a320.h> 11#include <cpu_macros.S> 12#include <plat_macros.S> 13 14/* Hardware handled coherency */ 15#if HW_ASSISTED_COHERENCY == 0 16#error "Cortex-A320 must be compiled with HW_ASSISTED_COHERENCY enabled" 17#endif 18 19/* 64-bit only core */ 20#if CTX_INCLUDE_AARCH32_REGS == 1 21#error "Cortex-A320 supports only AArch64. Compile with CTX_INCLUDE_AARCH32_REGS=0" 22#endif 23 24cpu_reset_prologue cortex_a320 25 26cpu_reset_func_start cortex_a320 27 /* Disable speculative loads */ 28 msr SSBS, xzr 29 enable_mpmm 30cpu_reset_func_end cortex_a320 31 32 /* ---------------------------------------------------- 33 * HW will do the cache maintenance while powering down 34 * ---------------------------------------------------- 35 */ 36func cortex_a320_core_pwr_dwn 37 /* --------------------------------------------------- 38 * Enable CPU power down bit in power control register 39 * --------------------------------------------------- 40 */ 41 sysreg_bit_set CORTEX_A320_CPUPWRCTLR_EL1, CORTEX_A320_CPUPWRCTLR_EL1_CORE_PWRDN_BIT 42 isb 43 ret 44endfunc cortex_a320_core_pwr_dwn 45 46 /* --------------------------------------------- 47 * This function provides Cortex-A320 specific 48 * register information for crash reporting. 49 * It needs to return with x6 pointing to 50 * a list of register names in ascii and 51 * x8 - x15 having values of registers to be 52 * reported. 53 * --------------------------------------------- 54 */ 55.section .rodata.cortex_a320_regs, "aS" 56cortex_a320_regs: /* The ascii list of register names to be reported */ 57 .asciz "cpuectlr_el1", "" 58 59func cortex_a320_cpu_reg_dump 60 adr x6, cortex_a320_regs 61 mrs x8, CORTEX_A320_CPUECTLR_EL1 62 ret 63endfunc cortex_a320_cpu_reg_dump 64 65declare_cpu_ops cortex_a320, CORTEX_A320_MIDR, \ 66 cortex_a320_reset_func, \ 67 cortex_a320_core_pwr_dwn 68