1/* 2 * Copyright (c) 2017-2025, Arm Limited and Contributors. All rights reserved. 3 * 4 * SPDX-License-Identifier: BSD-3-Clause 5 */ 6 7#include <arch.h> 8#include <asm_macros.S> 9#include <cpuamu.h> 10#include <cpu_macros.S> 11#include <dsu_macros.S> 12#include <neoverse_n1.h> 13#include "wa_cve_2022_23960_bhb_vector.S" 14 15/* Hardware handled coherency */ 16#if HW_ASSISTED_COHERENCY == 0 17#error "Neoverse N1 must be compiled with HW_ASSISTED_COHERENCY enabled" 18#endif 19 20/* 64-bit only core */ 21#if CTX_INCLUDE_AARCH32_REGS == 1 22#error "Neoverse-N1 supports only AArch64. Compile with CTX_INCLUDE_AARCH32_REGS=0" 23#endif 24 25 .global neoverse_n1_errata_ic_trap_handler 26 27#if WORKAROUND_CVE_2022_23960 28 wa_cve_2022_23960_bhb_vector_table NEOVERSE_N1_BHB_LOOP_COUNT, neoverse_n1 29#endif /* WORKAROUND_CVE_2022_23960 */ 30 31workaround_reset_start neoverse_n1, ERRATUM(936184), ERRATA_DSU_936184 32 errata_dsu_936184_wa_impl 33workaround_reset_end neoverse_n1, ERRATUM(936184) 34 35check_erratum_custom_start neoverse_n1, ERRATUM(936184) 36 branch_if_scu_not_present 2f /* label 1 is used in the macro */ 37 check_errata_dsu_936184_impl 38 2: 39 ret 40check_erratum_custom_end neoverse_n1, ERRATUM(936184) 41 42workaround_reset_start neoverse_n1, ERRATUM(1043202), ERRATA_N1_1043202 43 /* Apply instruction patching sequence */ 44 ldr x0, =0x0 45 msr CPUPSELR_EL3, x0 46 ldr x0, =0xF3BF8F2F 47 msr CPUPOR_EL3, x0 48 ldr x0, =0xFFFFFFFF 49 msr CPUPMR_EL3, x0 50 ldr x0, =0x800200071 51 msr CPUPCR_EL3, x0 52workaround_reset_end neoverse_n1, ERRATUM(1043202) 53 54check_erratum_ls neoverse_n1, ERRATUM(1043202), CPU_REV(1, 0) 55 56workaround_reset_start neoverse_n1, ERRATUM(1073348), ERRATA_N1_1073348 57 sysreg_bit_set NEOVERSE_N1_CPUACTLR_EL1, NEOVERSE_N1_CPUACTLR_EL1_BIT_6 58workaround_reset_end neoverse_n1, ERRATUM(1073348) 59 60check_erratum_ls neoverse_n1, ERRATUM(1073348), CPU_REV(1, 0) 61 62workaround_reset_start neoverse_n1, ERRATUM(1130799), ERRATA_N1_1130799 63 sysreg_bit_set NEOVERSE_N1_CPUACTLR2_EL1, NEOVERSE_N1_CPUACTLR2_EL1_BIT_59 64workaround_reset_end neoverse_n1, ERRATUM(1130799) 65 66check_erratum_ls neoverse_n1, ERRATUM(1130799), CPU_REV(2, 0) 67 68workaround_reset_start neoverse_n1, ERRATUM(1165347), ERRATA_N1_1165347 69 sysreg_bit_set NEOVERSE_N1_CPUACTLR2_EL1, NEOVERSE_N1_CPUACTLR2_EL1_BIT_0 70 sysreg_bit_set NEOVERSE_N1_CPUACTLR2_EL1, NEOVERSE_N1_CPUACTLR2_EL1_BIT_15 71workaround_reset_end neoverse_n1, ERRATUM(1165347) 72 73check_erratum_ls neoverse_n1, ERRATUM(1165347), CPU_REV(2, 0) 74 75workaround_reset_start neoverse_n1, ERRATUM(1207823), ERRATA_N1_1207823 76 sysreg_bit_set NEOVERSE_N1_CPUACTLR2_EL1, NEOVERSE_N1_CPUACTLR2_EL1_BIT_11 77workaround_reset_end neoverse_n1, ERRATUM(1207823) 78 79check_erratum_ls neoverse_n1, ERRATUM(1207823), CPU_REV(2, 0) 80 81workaround_reset_start neoverse_n1, ERRATUM(1220197), ERRATA_N1_1220197 82 sysreg_bit_set NEOVERSE_N1_CPUECTLR_EL1, NEOVERSE_N1_WS_THR_L2_MASK 83workaround_reset_end neoverse_n1, ERRATUM(1220197) 84 85check_erratum_ls neoverse_n1, ERRATUM(1220197), CPU_REV(2, 0) 86 87workaround_reset_start neoverse_n1, ERRATUM(1257314), ERRATA_N1_1257314 88 sysreg_bit_set NEOVERSE_N1_CPUACTLR3_EL1, NEOVERSE_N1_CPUACTLR3_EL1_BIT_10 89workaround_reset_end neoverse_n1, ERRATUM(1257314) 90 91check_erratum_ls neoverse_n1, ERRATUM(1257314), CPU_REV(3, 0) 92 93workaround_reset_start neoverse_n1, ERRATUM(1262606), ERRATA_N1_1262606 94 sysreg_bit_set NEOVERSE_N1_CPUACTLR_EL1, NEOVERSE_N1_CPUACTLR_EL1_BIT_13 95workaround_reset_end neoverse_n1, ERRATUM(1262606) 96 97check_erratum_ls neoverse_n1, ERRATUM(1262606), CPU_REV(3, 0) 98 99workaround_reset_start neoverse_n1, ERRATUM(1262888), ERRATA_N1_1262888 100 sysreg_bit_set NEOVERSE_N1_CPUECTLR_EL1, NEOVERSE_N1_CPUECTLR_EL1_MM_TLBPF_DIS_BIT 101workaround_reset_end neoverse_n1, ERRATUM(1262888) 102 103check_erratum_ls neoverse_n1, ERRATUM(1262888), CPU_REV(3, 0) 104 105workaround_reset_start neoverse_n1, ERRATUM(1275112), ERRATA_N1_1275112 106 sysreg_bit_set NEOVERSE_N1_CPUACTLR_EL1, NEOVERSE_N1_CPUACTLR_EL1_BIT_13 107workaround_reset_end neoverse_n1, ERRATUM(1275112) 108 109check_erratum_ls neoverse_n1, ERRATUM(1275112), CPU_REV(3, 0) 110 111workaround_reset_start neoverse_n1, ERRATUM(1315703), ERRATA_N1_1315703 112 sysreg_bit_set NEOVERSE_N1_CPUACTLR2_EL1, NEOVERSE_N1_CPUACTLR2_EL1_BIT_16 113workaround_reset_end neoverse_n1, ERRATUM(1315703) 114 115check_erratum_ls neoverse_n1, ERRATUM(1315703), CPU_REV(3, 0) 116 117workaround_reset_start neoverse_n1, ERRATUM(1542419), ERRATA_N1_1542419 118 /* Apply instruction patching sequence */ 119 ldr x0, =0x0 120 msr CPUPSELR_EL3, x0 121 ldr x0, =0xEE670D35 122 msr CPUPOR_EL3, x0 123 ldr x0, =0xFFFF0FFF 124 msr CPUPMR_EL3, x0 125 ldr x0, =0x08000020007D 126 msr CPUPCR_EL3, x0 127 isb 128workaround_reset_end neoverse_n1, ERRATUM(1542419) 129 130check_erratum_range neoverse_n1, ERRATUM(1542419), CPU_REV(3, 0), CPU_REV(4, 0) 131 132workaround_reset_start neoverse_n1, ERRATUM(1868343), ERRATA_N1_1868343 133 sysreg_bit_set NEOVERSE_N1_CPUACTLR_EL1, NEOVERSE_N1_CPUACTLR_EL1_BIT_13 134workaround_reset_end neoverse_n1, ERRATUM(1868343) 135 136check_erratum_ls neoverse_n1, ERRATUM(1868343), CPU_REV(4, 0) 137 138workaround_reset_start neoverse_n1, ERRATUM(1946160), ERRATA_N1_1946160 139 mov x0, #3 140 msr S3_6_C15_C8_0, x0 141 ldr x0, =0x10E3900002 142 msr S3_6_C15_C8_2, x0 143 ldr x0, =0x10FFF00083 144 msr S3_6_C15_C8_3, x0 145 ldr x0, =0x2001003FF 146 msr S3_6_C15_C8_1, x0 147 mov x0, #4 148 msr S3_6_C15_C8_0, x0 149 ldr x0, =0x10E3800082 150 msr S3_6_C15_C8_2, x0 151 ldr x0, =0x10FFF00083 152 msr S3_6_C15_C8_3, x0 153 ldr x0, =0x2001003FF 154 msr S3_6_C15_C8_1, x0 155 mov x0, #5 156 msr S3_6_C15_C8_0, x0 157 ldr x0, =0x10E3800200 158 msr S3_6_C15_C8_2, x0 159 ldr x0, =0x10FFF003E0 160 msr S3_6_C15_C8_3, x0 161 ldr x0, =0x2001003FF 162 msr S3_6_C15_C8_1, x0 163 isb 164workaround_reset_end neoverse_n1, ERRATUM(1946160) 165 166check_erratum_range neoverse_n1, ERRATUM(1946160), CPU_REV(3, 0), CPU_REV(4, 1) 167 168workaround_runtime_start neoverse_n1, ERRATUM(2743102), ERRATA_N1_2743102 169 /* dsb before isb of power down sequence */ 170 dsb sy 171workaround_runtime_end neoverse_n1, ERRATUM(2743102) 172 173check_erratum_ls neoverse_n1, ERRATUM(2743102), CPU_REV(4, 1) 174 175workaround_reset_start neoverse_n1, CVE(2022, 23960), WORKAROUND_CVE_2022_23960 176#if IMAGE_BL31 177 /* 178 * The Neoverse-N1 generic vectors are overridden to apply errata 179 * mitigation on exception entry from lower ELs. 180 */ 181 override_vector_table wa_cve_vbar_neoverse_n1 182#endif /* IMAGE_BL31 */ 183workaround_reset_end neoverse_n1, CVE(2022, 23960) 184 185check_erratum_chosen neoverse_n1, CVE(2022, 23960), WORKAROUND_CVE_2022_23960 186 187/* -------------------------------------------------- 188 * Disable speculative loads if Neoverse N1 supports 189 * SSBS. 190 * 191 * Shall clobber: x0. 192 * -------------------------------------------------- 193 */ 194func neoverse_n1_disable_speculative_loads 195 /* Check if the PE implements SSBS */ 196 mrs x0, id_aa64pfr1_el1 197 tst x0, #(ID_AA64PFR1_EL1_SSBS_MASK << ID_AA64PFR1_EL1_SSBS_SHIFT) 198 b.eq 1f 199 200 /* Disable speculative loads */ 201 msr SSBS, xzr 202 2031: 204 ret 205endfunc neoverse_n1_disable_speculative_loads 206 207cpu_reset_func_start neoverse_n1 208 bl neoverse_n1_disable_speculative_loads 209 210 /* Forces all cacheable atomic instructions to be near */ 211 sysreg_bit_set NEOVERSE_N1_CPUACTLR2_EL1, NEOVERSE_N1_CPUACTLR2_EL1_BIT_2 212 isb 213 214#if ENABLE_FEAT_AMU 215 /* Make sure accesses from EL0/EL1 and EL2 are not trapped to EL3 */ 216 sysreg_bit_set actlr_el3, NEOVERSE_N1_ACTLR_AMEN_BIT 217 /* Make sure accesses from EL0/EL1 are not trapped to EL2 */ 218 sysreg_bit_set actlr_el2, NEOVERSE_N1_ACTLR_AMEN_BIT 219 /* Enable group0 counters */ 220 mov x0, #NEOVERSE_N1_AMU_GROUP0_MASK 221 msr CPUAMCNTENSET_EL0, x0 222#endif 223 224#if NEOVERSE_Nx_EXTERNAL_LLC 225 /* Some system may have External LLC, core needs to be made aware */ 226 sysreg_bit_set NEOVERSE_N1_CPUECTLR_EL1, NEOVERSE_N1_CPUECTLR_EL1_EXTLLC_BIT 227#endif 228cpu_reset_func_end neoverse_n1 229 230 /* --------------------------------------------- 231 * HW will do the cache maintenance while powering down 232 * --------------------------------------------- 233 */ 234func neoverse_n1_core_pwr_dwn 235 /* --------------------------------------------- 236 * Enable CPU power down bit in power control register 237 * --------------------------------------------- 238 */ 239 sysreg_bit_set NEOVERSE_N1_CPUPWRCTLR_EL1, NEOVERSE_N1_CORE_PWRDN_EN_MASK 240 241 apply_erratum neoverse_n1, ERRATUM(2743102), ERRATA_N1_2743102, NO_GET_CPU_REV 242 243 isb 244 ret 245endfunc neoverse_n1_core_pwr_dwn 246 247/* 248 * Handle trap of EL0 IC IVAU instructions to EL3 by executing a TLB 249 * inner-shareable invalidation to an arbitrary address followed by a DSB. 250 * 251 * x1: Exception Syndrome 252 */ 253func neoverse_n1_errata_ic_trap_handler 254 cmp x1, #NEOVERSE_N1_EC_IC_TRAP 255 b.ne 1f 256 tlbi vae3is, xzr 257 dsb sy 258 259 # Skip the IC instruction itself 260 mrs x3, elr_el3 261 add x3, x3, #4 262 msr elr_el3, x3 263 264 ldp x0, x1, [sp, #CTX_GPREGS_OFFSET + CTX_GPREG_X0] 265 ldp x2, x3, [sp, #CTX_GPREGS_OFFSET + CTX_GPREG_X2] 266 ldp x4, x5, [sp, #CTX_GPREGS_OFFSET + CTX_GPREG_X4] 267 ldr x30, [sp, #CTX_GPREGS_OFFSET + CTX_GPREG_LR] 268 269 /* 270 * Issue Error Synchronization Barrier to synchronize SErrors before 271 * exiting EL3. We're running with EAs unmasked, so any synchronized 272 * errors would be taken immediately; therefore no need to inspect 273 * DISR_EL1 register. 274 */ 275 esb 276 exception_return 2771: 278 ret 279endfunc neoverse_n1_errata_ic_trap_handler 280 281 /* --------------------------------------------- 282 * This function provides neoverse_n1 specific 283 * register information for crash reporting. 284 * It needs to return with x6 pointing to 285 * a list of register names in ascii and 286 * x8 - x15 having values of registers to be 287 * reported. 288 * --------------------------------------------- 289 */ 290.section .rodata.neoverse_n1_regs, "aS" 291neoverse_n1_regs: /* The ascii list of register names to be reported */ 292 .asciz "cpuectlr_el1", "" 293 294func neoverse_n1_cpu_reg_dump 295 adr x6, neoverse_n1_regs 296 mrs x8, NEOVERSE_N1_CPUECTLR_EL1 297 ret 298endfunc neoverse_n1_cpu_reg_dump 299 300declare_cpu_ops_eh neoverse_n1, NEOVERSE_N1_MIDR, \ 301 neoverse_n1_reset_func, \ 302 neoverse_n1_errata_ic_trap_handler, \ 303 neoverse_n1_core_pwr_dwn 304