1# Copyright (c) 2018-2022, Arm Limited and Contributors. All rights reserved. 2# Copyright (c) 2021-2022, Xilinx, Inc. All rights reserved. 3# Copyright (c) 2022-2025, Advanced Micro Devices, Inc. All rights reserved. 4# 5# SPDX-License-Identifier: BSD-3-Clause 6 7PLAT_PATH := plat/amd/versal2 8 9override NEED_BL1 := no 10override NEED_BL2 := no 11 12# A78 Erratum for SoC 13ERRATA_A78_AE_1941500 := 1 14ERRATA_A78_AE_1951502 := 1 15ERRATA_A78_AE_2376748 := 1 16ERRATA_A78_AE_2395408 := 1 17ERRATA_ABI_SUPPORT := 1 18 19# Platform Supports Armv8.2 extensions 20ARM_ARCH_MAJOR := 8 21ARM_ARCH_MINOR := 2 22 23override PROGRAMMABLE_RESET_ADDRESS := 1 24PSCI_EXTENDED_STATE_ID := 1 25SEPARATE_CODE_AND_RODATA := 1 26override RESET_TO_BL31 := 1 27PL011_GENERIC_UART := 1 28IPI_CRC_CHECK := 0 29GIC_ENABLE_V4_EXTN := 0 30GICV3_SUPPORT_GIC600 := 1 31 32override CTX_INCLUDE_AARCH32_REGS := 0 33 34# Platform to support Dynamic XLAT Table by default 35override PLAT_XLAT_TABLES_DYNAMIC := 1 36$(eval $(call add_define,PLAT_XLAT_TABLES_DYNAMIC)) 37 38ifdef MEM_BASE 39 $(eval $(call add_define,MEM_BASE)) 40 41 ifndef MEM_SIZE 42 $(error "MEM_BASE defined without MEM_SIZE") 43 endif 44 $(eval $(call add_define,MEM_SIZE)) 45 46 ifdef MEM_PROGBITS_SIZE 47 $(eval $(call add_define,MEM_PROGBITS_SIZE)) 48 endif 49endif 50 51ifdef BL32_MEM_BASE 52 $(eval $(call add_define,BL32_MEM_BASE)) 53 54 ifndef BL32_MEM_SIZE 55 $(error "BL32_MEM_BASE defined without BL32_MEM_SIZE") 56 endif 57 $(eval $(call add_define,BL32_MEM_SIZE)) 58endif 59 60ifdef IPI_CRC_CHECK 61 $(eval $(call add_define,IPI_CRC_CHECK)) 62endif 63 64USE_COHERENT_MEM := 0 65HW_ASSISTED_COHERENCY := 1 66 67VERSAL2_CONSOLE ?= pl011 68ifeq (${VERSAL2_CONSOLE}, $(filter ${VERSAL2_CONSOLE},pl011 pl011_0 pl011_1 dcc dtb none)) 69 else 70 $(error "Please define VERSAL2_CONSOLE") 71 endif 72 73$(eval $(call add_define_val,VERSAL2_CONSOLE,VERSAL2_CONSOLE_ID_${VERSAL2_CONSOLE})) 74 75# Runtime console in default console in DEBUG build 76ifeq ($(DEBUG), 1) 77CONSOLE_RUNTIME ?= pl011 78endif 79 80# Runtime console 81ifdef CONSOLE_RUNTIME 82ifeq (${CONSOLE_RUNTIME}, $(filter ${CONSOLE_RUNTIME},pl011 pl011_0 pl011_1 dcc dtb)) 83$(eval $(call add_define_val,CONSOLE_RUNTIME,RT_CONSOLE_ID_${CONSOLE_RUNTIME})) 84else 85 $(error "Please define CONSOLE_RUNTIME") 86endif 87endif 88 89ifeq (${TRANSFER_LIST},0) 90XILINX_OF_BOARD_DTB_ADDR ?= 0x1000000 91$(eval $(call add_define,XILINX_OF_BOARD_DTB_ADDR)) 92endif 93 94PLAT_INCLUDES := -Iinclude/plat/arm/common/ \ 95 -Iplat/xilinx/common/include/ \ 96 -Iplat/amd/common/include/ \ 97 -Iplat/xilinx/common/ipi_mailbox_service/ \ 98 -I${PLAT_PATH}/include/ \ 99 -Iplat/xilinx/versal/pm_service/ 100 101# Include GICv3 driver files 102include drivers/arm/gic/v3/gicv3.mk 103include lib/xlat_tables_v2/xlat_tables.mk 104include lib/libfdt/libfdt.mk 105 106PLAT_BL_COMMON_SOURCES := \ 107 drivers/arm/dcc/dcc_console.c \ 108 drivers/delay_timer/delay_timer.c \ 109 drivers/delay_timer/generic_delay_timer.c \ 110 ${GICV3_SOURCES} \ 111 drivers/arm/pl011/aarch64/pl011_console.S \ 112 plat/common/aarch64/crash_console_helpers.S \ 113 plat/arm/common/arm_common.c \ 114 plat/common/plat_gicv3.c \ 115 ${PLAT_PATH}/aarch64/helpers.S \ 116 ${PLAT_PATH}/aarch64/common.c \ 117 ${PLAT_PATH}/plat_topology.c \ 118 ${XLAT_TABLES_LIB_SRCS} 119 120BL31_SOURCES += drivers/arm/cci/cci.c \ 121 lib/cpus/aarch64/cortex_a78_ae.S \ 122 lib/cpus/aarch64/cortex_a78.S \ 123 plat/common/plat_psci_common.c \ 124 drivers/scmi-msg/base.c \ 125 drivers/scmi-msg/entry.c \ 126 drivers/scmi-msg/smt.c \ 127 drivers/scmi-msg/clock.c \ 128 drivers/scmi-msg/power_domain.c \ 129 drivers/scmi-msg/reset_domain.c \ 130 ${PLAT_PATH}/scmi.c 131 132BL31_SOURCES += ${PLAT_PATH}/plat_psci.c \ 133 common/fdt_wrappers.c \ 134 plat/xilinx/common/plat_console.c \ 135 plat/xilinx/common/plat_startup.c \ 136 plat/xilinx/common/ipi.c \ 137 plat/xilinx/common/ipi_mailbox_service/ipi_mailbox_svc.c \ 138 ${PLAT_PATH}/soc_ipi.c \ 139 plat/xilinx/common/versal.c \ 140 ${PLAT_PATH}/bl31_setup.c \ 141 common/fdt_fixup.c \ 142 common/fdt_wrappers.c \ 143 ${LIBFDT_SRCS} \ 144 ${PLAT_PATH}/sip_svc_setup.c \ 145 ${PLAT_PATH}/gicv3.c 146 147ifeq (${ERRATA_ABI_SUPPORT}, 1) 148# enable the cpu macros for errata abi interface 149CORTEX_A78_AE_H_INC := 1 150$(eval $(call add_define, CORTEX_A78_AE_H_INC)) 151endif 152 153# Enable Handoff protocol using transfer lists 154TRANSFER_LIST ?= 0 155 156ifeq (${TRANSFER_LIST},1) 157include lib/transfer_list/transfer_list.mk 158BL31_SOURCES += plat/amd/common/plat_fdt.c 159BL31_SOURCES += plat/amd/common/plat_xfer_list.c 160else 161BL31_SOURCES += plat/xilinx/common/plat_fdt.c 162endif 163 164XLNX_DT_CFG ?= 1 165ifeq (${TRANSFER_LIST},0) 166ifndef XILINX_OF_BOARD_DTB_ADDR 167XLNX_DT_CFG := 0 168endif 169endif 170$(eval $(call add_define,XLNX_DT_CFG)) 171