1 /* 2 * Copyright (c) 2013-2025, Arm Limited and Contributors. All rights reserved. 3 * 4 * SPDX-License-Identifier: BSD-3-Clause 5 */ 6 7 #include <assert.h> 8 9 #include <common/debug.h> 10 #include <common/desc_image_load.h> 11 #include <drivers/arm/sp804_delay_timer.h> 12 #include <fvp_pas_def.h> 13 #include <lib/fconf/fconf.h> 14 #include <lib/fconf/fconf_dyn_cfg_getter.h> 15 #include <lib/transfer_list.h> 16 17 #include <plat/arm/common/plat_arm.h> 18 #include <plat/common/platform.h> 19 #include <platform_def.h> 20 21 #include "fvp_private.h" 22 23 #if ENABLE_RME 24 /* 25 * The GPT library might modify the gpt regions structure to optimize 26 * the layout, so the array cannot be constant. 27 */ 28 static pas_region_t pas_regions[] = { 29 ARM_PAS_KERNEL, 30 ARM_PAS_SECURE, 31 ARM_PAS_REALM, 32 ARM_PAS_EL3_DRAM, 33 #ifdef ARM_PAS_GPTS 34 ARM_PAS_GPTS, 35 #endif 36 ARM_PAS_KERNEL_1, 37 ARM_PAS_PCI_MEM_1, 38 ARM_PAS_PCI_MEM_2 39 }; 40 41 static const arm_gpt_info_t arm_gpt_info = { 42 .pas_region_base = pas_regions, 43 .pas_region_count = (unsigned int)ARRAY_SIZE(pas_regions), 44 .l0_base = ARM_L0_GPT_BASE, 45 .l1_base = ARM_L1_GPT_BASE, 46 .l0_size = ARM_L0_GPT_SIZE, 47 .l1_size = ARM_L1_GPT_SIZE, 48 .pps = GPCCR_PPS_1TB, 49 .pgs = GPCCR_PGS_4K 50 }; 51 #endif /* ENABLE_RME */ 52 53 void bl2_early_platform_setup2(u_register_t arg0, u_register_t arg1, u_register_t arg2, u_register_t arg3) 54 { 55 arm_bl2_early_platform_setup(arg0, arg1, arg2, arg3); 56 57 /* Initialize the platform config for future decision making */ 58 fvp_config_setup(); 59 } 60 61 void bl2_platform_setup(void) 62 { 63 arm_bl2_platform_setup(); 64 65 /* Initialize System level generic or SP804 timer */ 66 fvp_timer_init(); 67 } 68 69 #if ENABLE_RME 70 const arm_gpt_info_t *plat_arm_get_gpt_info(void) 71 { 72 return &arm_gpt_info; 73 } 74 #endif /* ENABLE_RME */ 75 76 /******************************************************************************* 77 * This function returns the list of executable images 78 ******************************************************************************/ 79 struct bl_params *plat_get_next_bl_params(void) 80 { 81 struct bl_params *arm_bl_params; 82 bl_mem_params_node_t *param_node __unused; 83 const struct dyn_cfg_dtb_info_t *fw_config_info __unused; 84 const struct dyn_cfg_dtb_info_t *hw_config_info __unused; 85 entry_point_info_t *ep __unused; 86 uint32_t next_exe_img_id __unused; 87 uintptr_t fw_config_base __unused; 88 89 arm_bl_params = arm_get_next_bl_params(); 90 91 #if __aarch64__ 92 /* Get BL31 image node */ 93 param_node = get_bl_mem_params_node(BL31_IMAGE_ID); 94 #else /* aarch32 */ 95 /* Get SP_MIN image node */ 96 param_node = get_bl_mem_params_node(BL32_IMAGE_ID); 97 #endif /* __aarch64__ */ 98 assert(param_node != NULL); 99 100 #if TRANSFER_LIST 101 arm_bl_params->head = ¶m_node->params_node_mem; 102 arm_bl_params->head->ep_info = ¶m_node->ep_info; 103 arm_bl_params->head->image_id = param_node->image_id; 104 105 arm_bl2_setup_next_ep_info(param_node); 106 #elif !RESET_TO_BL2 && !EL3_PAYLOAD_BASE 107 fw_config_base = 0UL; 108 109 /* Update the next image's ep info with the FW config address */ 110 fw_config_info = FCONF_GET_PROPERTY(dyn_cfg, dtb, FW_CONFIG_ID); 111 assert(fw_config_info != NULL); 112 113 fw_config_base = fw_config_info->config_addr; 114 assert(fw_config_base != 0UL); 115 116 param_node->ep_info.args.arg1 = (uint32_t)fw_config_base; 117 118 /* Update BL33's ep info with the NS HW config address */ 119 param_node = get_bl_mem_params_node(BL33_IMAGE_ID); 120 assert(param_node != NULL); 121 122 hw_config_info = FCONF_GET_PROPERTY(dyn_cfg, dtb, HW_CONFIG_ID); 123 assert(hw_config_info != NULL); 124 125 param_node->ep_info.args.arg1 = hw_config_info->secondary_config_addr; 126 #endif /* TRANSFER_LIST */ 127 128 return arm_bl_params; 129 } 130 131 int bl2_plat_handle_post_image_load(unsigned int image_id) 132 { 133 #if !RESET_TO_BL2 && !EL3_PAYLOAD_BASE && !TRANSFER_LIST 134 if (image_id == HW_CONFIG_ID) { 135 const struct dyn_cfg_dtb_info_t *hw_config_info __unused; 136 struct transfer_list_entry *te __unused; 137 bl_mem_params_node_t *param_node __unused; 138 139 param_node = get_bl_mem_params_node(image_id); 140 assert(param_node != NULL); 141 142 hw_config_info = FCONF_GET_PROPERTY(dyn_cfg, dtb, HW_CONFIG_ID); 143 assert(hw_config_info != NULL); 144 145 memcpy((void *)hw_config_info->secondary_config_addr, 146 (void *)hw_config_info->config_addr, 147 (size_t)param_node->image_info.image_size); 148 149 /* 150 * Ensure HW-config device tree is committed to memory, as the HW-Config 151 * might be used without cache and MMU enabled at BL33. 152 */ 153 flush_dcache_range(hw_config_info->secondary_config_addr, 154 param_node->image_info.image_size); 155 } 156 #endif /* !RESET_TO_BL2 && !EL3_PAYLOAD_BASE && !TRANSFER_LIST*/ 157 158 return arm_bl2_plat_handle_post_image_load(image_id); 159 } 160