1/* 2 * Copyright (c) 2023-2025, Arm Limited. All rights reserved. 3 * 4 * SPDX-License-Identifier: BSD-3-Clause 5 */ 6 7#include <arch.h> 8#include <asm_macros.S> 9#include <common/bl_common.h> 10#include <cortex_a725.h> 11#include <cpu_macros.S> 12#include <plat_macros.S> 13 14/* Hardware handled coherency */ 15#if HW_ASSISTED_COHERENCY == 0 16#error "Cortex-A725 must be compiled with HW_ASSISTED_COHERENCY enabled" 17#endif 18 19/* 64-bit only core */ 20#if CTX_INCLUDE_AARCH32_REGS == 1 21#error "Cortex-A725 supports only AArch64. Compile with CTX_INCLUDE_AARCH32_REGS=0" 22#endif 23 24.global check_erratum_cortex_a725_3699564 25 26add_erratum_entry cortex_a725, ERRATUM(3699564), ERRATA_A725_3699564, NO_APPLY_AT_RESET 27 28check_erratum_ls cortex_a725, ERRATUM(3699564), CPU_REV(0, 1) 29 30cpu_reset_func_start cortex_a725 31 /* Disable speculative loads */ 32 msr SSBS, xzr 33cpu_reset_func_end cortex_a725 34 35 /* ---------------------------------------------------- 36 * HW will do the cache maintenance while powering down 37 * ---------------------------------------------------- 38 */ 39func cortex_a725_core_pwr_dwn 40 /* --------------------------------------------------- 41 * Enable CPU power down bit in power control register 42 * --------------------------------------------------- 43 */ 44 sysreg_bit_set CORTEX_A725_CPUPWRCTLR_EL1, CORTEX_A725_CPUPWRCTLR_EL1_CORE_PWRDN_BIT 45 isb 46 ret 47endfunc cortex_a725_core_pwr_dwn 48 49 /* --------------------------------------------- 50 * This function provides Cortex-A725 specific 51 * register information for crash reporting. 52 * It needs to return with x6 pointing to 53 * a list of register names in ascii and 54 * x8 - x15 having values of registers to be 55 * reported. 56 * --------------------------------------------- 57 */ 58.section .rodata.cortex_a725_regs, "aS" 59cortex_a725_regs: /* The ascii list of register names to be reported */ 60 .asciz "cpuectlr_el1", "" 61 62func cortex_a725_cpu_reg_dump 63 adr x6, cortex_a725_regs 64 mrs x8, CORTEX_A725_CPUECTLR_EL1 65 ret 66endfunc cortex_a725_cpu_reg_dump 67 68declare_cpu_ops cortex_a725, CORTEX_A725_MIDR, \ 69 cortex_a725_reset_func, \ 70 cortex_a725_core_pwr_dwn 71