1/* 2 * Copyright (c) 2015-2025, Arm Limited and Contributors. All rights reserved. 3 * 4 * SPDX-License-Identifier: BSD-3-Clause 5 */ 6 7#ifndef EL3_COMMON_MACROS_S 8#define EL3_COMMON_MACROS_S 9 10#include <arch.h> 11#include <asm_macros.S> 12#include <assert_macros.S> 13#include <context.h> 14#include <lib/xlat_tables/xlat_tables_defs.h> 15 16 /* 17 * Helper macro to initialise EL3 registers we care about. 18 */ 19 .macro el3_arch_init_common 20 /* --------------------------------------------------------------------- 21 * SCTLR_EL3 has already been initialised - read current value before 22 * modifying. 23 * 24 * SCTLR_EL3.I: Enable the instruction cache. 25 * 26 * SCTLR_EL3.SA: Enable Stack Alignment check. A SP alignment fault 27 * exception is generated if a load or store instruction executed at 28 * EL3 uses the SP as the base address and the SP is not aligned to a 29 * 16-byte boundary. 30 * 31 * SCTLR_EL3.A: Enable Alignment fault checking. All instructions that 32 * load or store one or more registers have an alignment check that the 33 * address being accessed is aligned to the size of the data element(s) 34 * being accessed. 35 * --------------------------------------------------------------------- 36 */ 37 mov x1, #(SCTLR_I_BIT | SCTLR_A_BIT | SCTLR_SA_BIT) 38 mrs x0, sctlr_el3 39 orr x0, x0, x1 40 msr sctlr_el3, x0 41 isb 42 43#ifdef IMAGE_BL31 44 /* --------------------------------------------------------------------- 45 * Initialise the per-cpu cache pointer to the CPU. 46 * This is done early to enable crash reporting to have access to crash 47 * stack. Since crash reporting depends on cpu_data to report the 48 * unhandled exception, not doing so can lead to recursive exceptions 49 * due to a NULL TPIDR_EL3. 50 * --------------------------------------------------------------------- 51 */ 52 bl plat_my_core_pos 53 bl _cpu_data_by_index 54 msr tpidr_el3, x0 55#endif /* IMAGE_BL31 */ 56 57 /* --------------------------------------------------------------------- 58 * Initialise SCR_EL3, setting all fields rather than relying on hw. 59 * All fields are architecturally UNKNOWN on reset. The following fields 60 * do not change during the TF lifetime. The remaining fields are set to 61 * zero here but are updated ahead of transitioning to a lower EL in the 62 * function cm_init_context_common(). 63 * 64 * SCR_EL3.EEL2: Set to one if S-EL2 is present and enabled. 65 * 66 * NOTE: Modifying EEL2 bit along with EA bit ensures that we mitigate 67 * against ERRATA_V2_3099206. 68 * --------------------------------------------------------------------- 69 */ 70 mov_imm x0, SCR_RESET_VAL 71#if IMAGE_BL31 && defined(SPD_spmd) && SPMD_SPM_AT_SEL2 72 mrs x1, id_aa64pfr0_el1 73 and x1, x1, #(ID_AA64PFR0_SEL2_MASK << ID_AA64PFR0_SEL2_SHIFT) 74 cbz x1, 1f 75 orr x0, x0, #SCR_EEL2_BIT 76#endif 771: 78 msr scr_el3, x0 79 80 /* --------------------------------------------------------------------- 81 * Initialise MDCR_EL3, setting all fields rather than relying on hw. 82 * Some fields are architecturally UNKNOWN on reset. 83 */ 84 mov_imm x0, MDCR_EL3_RESET_VAL 85 msr mdcr_el3, x0 86 87 /* --------------------------------------------------------------------- 88 * Initialise CPTR_EL3, setting all fields rather than relying on hw. 89 * All fields are architecturally UNKNOWN on reset. 90 * --------------------------------------------------------------------- 91 */ 92 mov_imm x0, CPTR_EL3_RESET_VAL 93 msr cptr_el3, x0 94 95 .endm 96 97/* ----------------------------------------------------------------------------- 98 * This is the super set of actions that need to be performed during a cold boot 99 * or a warm boot in EL3. This code is shared by BL1 and BL31. 100 * 101 * This macro will always perform reset handling, architectural initialisations 102 * and stack setup. The rest of the actions are optional because they might not 103 * be needed, depending on the context in which this macro is called. This is 104 * why this macro is parameterised ; each parameter allows to enable/disable 105 * some actions. 106 * 107 * _init_sctlr: 108 * Whether the macro needs to initialise SCTLR_EL3, including configuring 109 * the endianness of data accesses. 110 * 111 * _warm_boot_mailbox: 112 * Whether the macro needs to detect the type of boot (cold/warm). The 113 * detection is based on the platform entrypoint address : if it is zero 114 * then it is a cold boot, otherwise it is a warm boot. In the latter case, 115 * this macro jumps on the platform entrypoint address. 116 * 117 * _secondary_cold_boot: 118 * Whether the macro needs to identify the CPU that is calling it: primary 119 * CPU or secondary CPU. The primary CPU will be allowed to carry on with 120 * the platform initialisations, while the secondaries will be put in a 121 * platform-specific state in the meantime. 122 * 123 * If the caller knows this macro will only be called by the primary CPU 124 * then this parameter can be defined to 0 to skip this step. 125 * 126 * _init_memory: 127 * Whether the macro needs to initialise the memory. 128 * 129 * _init_c_runtime: 130 * Whether the macro needs to initialise the C runtime environment. 131 * 132 * _exception_vectors: 133 * Address of the exception vectors to program in the VBAR_EL3 register. 134 * 135 * _pie_fixup_size: 136 * Size of memory region to fixup Global Descriptor Table (GDT). 137 * 138 * A non-zero value is expected when firmware needs GDT to be fixed-up. 139 * 140 * ----------------------------------------------------------------------------- 141 */ 142 .macro el3_entrypoint_common \ 143 _init_sctlr, _warm_boot_mailbox, _secondary_cold_boot, \ 144 _init_memory, _init_c_runtime, _exception_vectors, \ 145 _pie_fixup_size 146 147 .if \_init_sctlr 148 /* ------------------------------------------------------------- 149 * This is the initialisation of SCTLR_EL3 and so must ensure 150 * that all fields are explicitly set rather than relying on hw. 151 * Some fields reset to an IMPLEMENTATION DEFINED value and 152 * others are architecturally UNKNOWN on reset. 153 * 154 * SCTLR.EE: Set the CPU endianness before doing anything that 155 * might involve memory reads or writes. Set to zero to select 156 * Little Endian. 157 * 158 * SCTLR_EL3.WXN: For the EL3 translation regime, this field can 159 * force all memory regions that are writeable to be treated as 160 * XN (Execute-never). Set to zero so that this control has no 161 * effect on memory access permissions. 162 * 163 * SCTLR_EL3.SA: Set to zero to disable Stack Alignment check. 164 * 165 * SCTLR_EL3.A: Set to zero to disable Alignment fault checking. 166 * 167 * SCTLR.DSSBS: Set to zero to disable speculation store bypass 168 * safe behaviour upon exception entry to EL3. 169 * ------------------------------------------------------------- 170 */ 171 mov_imm x0, (SCTLR_RESET_VAL & ~(SCTLR_EE_BIT | SCTLR_WXN_BIT \ 172 | SCTLR_SA_BIT | SCTLR_A_BIT | SCTLR_DSSBS_BIT)) 173#if ENABLE_FEAT_RAS 174 /* If FEAT_RAS is present assume FEAT_IESB is also present */ 175 orr x0, x0, #SCTLR_IESB_BIT 176#endif 177 msr sctlr_el3, x0 178 isb 179 .endif /* _init_sctlr */ 180 181 .if \_warm_boot_mailbox 182 /* ------------------------------------------------------------- 183 * This code will be executed for both warm and cold resets. 184 * Now is the time to distinguish between the two. 185 * Query the platform entrypoint address and if it is not zero 186 * then it means it is a warm boot so jump to this address. 187 * ------------------------------------------------------------- 188 */ 189 bl plat_get_my_entrypoint 190 cbz x0, do_cold_boot 191 br x0 192 193 do_cold_boot: 194 .endif /* _warm_boot_mailbox */ 195 196 .if \_pie_fixup_size 197#if ENABLE_PIE 198 /* 199 * ------------------------------------------------------------ 200 * If PIE is enabled fixup the Global descriptor Table only 201 * once during primary core cold boot path. 202 * 203 * Compile time base address, required for fixup, is calculated 204 * using "pie_fixup" label present within first page. 205 * ------------------------------------------------------------ 206 */ 207 pie_fixup: 208 ldr x0, =pie_fixup 209 and x0, x0, #~(PAGE_SIZE_MASK) 210 mov_imm x1, \_pie_fixup_size 211 add x1, x1, x0 212 bl fixup_gdt_reloc 213#endif /* ENABLE_PIE */ 214 .endif /* _pie_fixup_size */ 215 216 /* --------------------------------------------------------------------- 217 * Set the exception vectors. 218 * --------------------------------------------------------------------- 219 */ 220 adr x0, \_exception_vectors 221 msr vbar_el3, x0 222 isb 223 224 call_reset_handler 225 226 el3_arch_init_common 227 228 /* --------------------------------------------------------------------- 229 * Set the el3 execution context(i.e. root_context). 230 * --------------------------------------------------------------------- 231 */ 232 setup_el3_execution_context 233 234 .if \_secondary_cold_boot 235 /* ------------------------------------------------------------- 236 * Check if this is a primary or secondary CPU cold boot. 237 * The primary CPU will set up the platform while the 238 * secondaries are placed in a platform-specific state until the 239 * primary CPU performs the necessary actions to bring them out 240 * of that state and allows entry into the OS. 241 * ------------------------------------------------------------- 242 */ 243 bl plat_is_my_cpu_primary 244 cbnz w0, do_primary_cold_boot 245 246 /* This is a cold boot on a secondary CPU */ 247 bl plat_secondary_cold_boot_setup 248 /* plat_secondary_cold_boot_setup() is not supposed to return */ 249 bl el3_panic 250 251 do_primary_cold_boot: 252 .endif /* _secondary_cold_boot */ 253 254 /* --------------------------------------------------------------------- 255 * Initialize memory now. Secondary CPU initialization won't get to this 256 * point. 257 * --------------------------------------------------------------------- 258 */ 259 260 .if \_init_memory 261 bl platform_mem_init 262 .endif /* _init_memory */ 263 264 /* --------------------------------------------------------------------- 265 * Init C runtime environment: 266 * - Zero-initialise the NOBITS sections. There are 2 of them: 267 * - the .bss section; 268 * - the coherent memory section (if any). 269 * - Relocate the data section from ROM to RAM, if required. 270 * --------------------------------------------------------------------- 271 */ 272 .if \_init_c_runtime 273#if defined(IMAGE_BL31) || (defined(IMAGE_BL2) && \ 274 ((RESET_TO_BL2 && BL2_INV_DCACHE) || ENABLE_RME)) 275 /* ------------------------------------------------------------- 276 * Invalidate the RW memory used by the BL31 image. This 277 * includes the data and NOBITS sections. This is done to 278 * safeguard against possible corruption of this memory by 279 * dirty cache lines in a system cache as a result of use by 280 * an earlier boot loader stage. If PIE is enabled however, 281 * RO sections including the GOT may be modified during 282 * pie fixup. Therefore, to be on the safe side, invalidate 283 * the entire image region if PIE is enabled. 284 * ------------------------------------------------------------- 285 */ 286#if ENABLE_PIE 287#if SEPARATE_CODE_AND_RODATA 288 adrp x0, __TEXT_START__ 289 add x0, x0, :lo12:__TEXT_START__ 290#else 291 adrp x0, __RO_START__ 292 add x0, x0, :lo12:__RO_START__ 293#endif /* SEPARATE_CODE_AND_RODATA */ 294#else 295 adrp x0, __RW_START__ 296 add x0, x0, :lo12:__RW_START__ 297#endif /* ENABLE_PIE */ 298 adrp x1, __RW_END__ 299 add x1, x1, :lo12:__RW_END__ 300 sub x1, x1, x0 301 bl inv_dcache_range 302#if defined(IMAGE_BL31) && SEPARATE_NOBITS_REGION 303 adrp x0, __NOBITS_START__ 304 add x0, x0, :lo12:__NOBITS_START__ 305 adrp x1, __NOBITS_END__ 306 add x1, x1, :lo12:__NOBITS_END__ 307 sub x1, x1, x0 308 bl inv_dcache_range 309#endif 310#if defined(IMAGE_BL2) && SEPARATE_BL2_NOLOAD_REGION 311 adrp x0, __BL2_NOLOAD_START__ 312 add x0, x0, :lo12:__BL2_NOLOAD_START__ 313 adrp x1, __BL2_NOLOAD_END__ 314 add x1, x1, :lo12:__BL2_NOLOAD_END__ 315 sub x1, x1, x0 316 bl inv_dcache_range 317#endif 318#endif 319 adrp x0, __BSS_START__ 320 add x0, x0, :lo12:__BSS_START__ 321 322 adrp x1, __BSS_END__ 323 add x1, x1, :lo12:__BSS_END__ 324 sub x1, x1, x0 325 bl zeromem 326 327#if USE_COHERENT_MEM 328 adrp x0, __COHERENT_RAM_START__ 329 add x0, x0, :lo12:__COHERENT_RAM_START__ 330 adrp x1, __COHERENT_RAM_END_UNALIGNED__ 331 add x1, x1, :lo12: __COHERENT_RAM_END_UNALIGNED__ 332 sub x1, x1, x0 333 bl zeromem 334#endif 335 336#if defined(IMAGE_BL1) || \ 337 (defined(IMAGE_BL2) && RESET_TO_BL2 && BL2_IN_XIP_MEM) || \ 338 (defined(IMAGE_BL31) && SEPARATE_RWDATA_REGION) 339 340 adrp x0, __DATA_RAM_START__ 341 add x0, x0, :lo12:__DATA_RAM_START__ 342 adrp x1, __DATA_ROM_START__ 343 add x1, x1, :lo12:__DATA_ROM_START__ 344 adrp x2, __DATA_RAM_END__ 345 add x2, x2, :lo12:__DATA_RAM_END__ 346 sub x2, x2, x0 347 bl memcpy16 348#endif 349 .endif /* _init_c_runtime */ 350 351 /* --------------------------------------------------------------------- 352 * Use SP_EL0 for the C runtime stack. 353 * --------------------------------------------------------------------- 354 */ 355 msr spsel, #0 356 357 /* --------------------------------------------------------------------- 358 * Allocate a stack whose memory will be marked as Normal-IS-WBWA when 359 * the MMU is enabled. There is no risk of reading stale stack memory 360 * after enabling the MMU as only the primary CPU is running at the 361 * moment. 362 * --------------------------------------------------------------------- 363 */ 364 bl plat_set_my_stack 365 366#if STACK_PROTECTOR_ENABLED 367 .if \_init_c_runtime 368 bl update_stack_protector_canary 369 .endif /* _init_c_runtime */ 370#endif 371 .endm 372 373 .macro apply_at_speculative_wa 374#if ERRATA_SPECULATIVE_AT 375 /* 376 * This function expects x30 has been saved. 377 * Also, save x29 which will be used in the called function. 378 */ 379 str x29, [sp, #CTX_GPREGS_OFFSET + CTX_GPREG_X29] 380 bl save_and_update_ptw_el1_sys_regs 381 ldr x29, [sp, #CTX_GPREGS_OFFSET + CTX_GPREG_X29] 382#endif 383 .endm 384 385 .macro restore_ptw_el1_sys_regs 386#if ERRATA_SPECULATIVE_AT 387 /* ----------------------------------------------------------- 388 * In case of ERRATA_SPECULATIVE_AT, must follow below order 389 * to ensure that page table walk is not enabled until 390 * restoration of all EL1 system registers. TCR_EL1 register 391 * should be updated at the end which restores previous page 392 * table walk setting of stage1 i.e.(TCR_EL1.EPDx) bits. ISB 393 * ensures that CPU does below steps in order. 394 * 395 * 1. Ensure all other system registers are written before 396 * updating SCTLR_EL1 using ISB. 397 * 2. Restore SCTLR_EL1 register. 398 * 3. Ensure SCTLR_EL1 written successfully using ISB. 399 * 4. Restore TCR_EL1 register. 400 * ----------------------------------------------------------- 401 */ 402 isb 403 ldp x28, x29, [sp, #CTX_ERRATA_SPEC_AT_OFFSET + CTX_ERRATA_SPEC_AT_SCTLR_EL1] 404 msr sctlr_el1, x28 405 isb 406 msr tcr_el1, x29 407#endif 408 .endm 409 410/* ----------------------------------------------------------------- 411 * The below macro reads SCR_EL3 from the context structure to 412 * determine the security state of the context upon ERET. 413 * ------------------------------------------------------------------ 414 */ 415 .macro get_security_state _ret:req, _scr_reg:req 416 ubfx \_ret, \_scr_reg, #SCR_NSE_SHIFT, #1 417 cmp \_ret, #1 418 beq realm_state 419 bfi \_ret, \_scr_reg, #0, #1 420 b end 421 realm_state: 422 mov \_ret, #2 423 end: 424 .endm 425 426/*----------------------------------------------------------------------------- 427 * Helper macro to configure EL3 registers we care about, while executing 428 * at EL3/Root world. Root world has its own execution environment and 429 * needs to have its settings configured to be independent of other worlds. 430 * ----------------------------------------------------------------------------- 431 */ 432 .macro setup_el3_execution_context 433 434 /* --------------------------------------------------------------------- 435 * The following registers need to be part of separate root context 436 * as their values are of importance during EL3 execution. 437 * Hence these registers are overwritten to their intital values, 438 * irrespective of whichever world they return from to ensure EL3 has a 439 * consistent execution context throughout the lifetime of TF-A. 440 * 441 * DAIF.A: Enable External Aborts and SError Interrupts at EL3. 442 * 443 * MDCR_EL3.SDD: Set to one to disable AArch64 Secure self-hosted debug. 444 * Debug exceptions, other than Breakpoint Instruction exceptions, are 445 * disabled from all ELs in Secure state. 446 * 447 * SCR_EL3.EA: Set to one to enable SError interrupts at EL3. 448 * 449 * SCR_EL3.SIF: Set to one to disable instruction fetches from 450 * Non-secure memory. 451 * 452 * PMCR_EL0.DP: Set to one so that the cycle counter, 453 * PMCCNTR_EL0 does not count when event counting is prohibited. 454 * Necessary on PMUv3 <= p7 where MDCR_EL3.{SCCD,MCCD} are not 455 * available. 456 * 457 * CPTR_EL3.EZ: Set to one so that accesses to ZCR_EL3 do not trap 458 * CPTR_EL3.TFP: Set to zero so that advanced SIMD operations don't trap 459 * CPTR_EL3.ESM: Set to one so that SME related registers don't trap 460 * 461 * PSTATE.DIT: Set to one to enable the Data Independent Timing (DIT) 462 * functionality, if implemented in EL3. 463 * --------------------------------------------------------------------- 464 */ 465 msr daifclr, #DAIF_ABT_BIT 466 467 mrs x15, mdcr_el3 468 orr x15, x15, #MDCR_SDD_BIT 469 msr mdcr_el3, x15 470 471 mrs x15, scr_el3 472 orr x15, x15, #SCR_EA_BIT 473 orr x15, x15, #SCR_SIF_BIT 474 msr scr_el3, x15 475 476 mrs x15, pmcr_el0 477 orr x15, x15, #PMCR_EL0_DP_BIT 478 msr pmcr_el0, x15 479 480 mrs x15, cptr_el3 481 orr x15, x15, #CPTR_EZ_BIT 482 orr x15, x15, #ESM_BIT 483 bic x15, x15, #TFP_BIT 484 msr cptr_el3, x15 485 486#if ENABLE_FEAT_DIT 487#if ENABLE_FEAT_DIT > 1 488 mrs x15, id_aa64pfr0_el1 489 ubfx x15, x15, #ID_AA64PFR0_DIT_SHIFT, #ID_AA64PFR0_DIT_LENGTH 490 cbz x15, 1f 491#endif 492 mov x15, #DIT_BIT 493 msr DIT, x15 494 1: 495#endif 496 497 isb 498 .endm 499 500#endif /* EL3_COMMON_MACROS_S */ 501