1/* 2 * Copyright (c) 2013-2025, Arm Limited and Contributors. All rights reserved. 3 * 4 * SPDX-License-Identifier: BSD-3-Clause 5 */ 6 7#include <arch.h> 8#include <asm_macros.S> 9#include <assert_macros.S> 10#include <context.h> 11#include <el3_common_macros.S> 12#include <platform_def.h> 13 14#if CTX_INCLUDE_FPREGS 15 .global fpregs_context_save 16 .global fpregs_context_restore 17#endif /* CTX_INCLUDE_FPREGS */ 18 19#if CTX_INCLUDE_SVE_REGS 20 .global sve_context_save 21 .global sve_context_restore 22#endif /* CTX_INCLUDE_SVE_REGS */ 23 24#if ERRATA_SPECULATIVE_AT 25 .global save_and_update_ptw_el1_sys_regs 26#endif /* ERRATA_SPECULATIVE_AT */ 27 28 .global prepare_el3_entry 29 .global restore_gp_pmcr_pauth_regs 30 .global el3_exit 31 32/* Following macros will be used if any of CTX_INCLUDE_FPREGS or CTX_INCLUDE_SVE_REGS is enabled */ 33#if CTX_INCLUDE_FPREGS || CTX_INCLUDE_SVE_REGS 34.macro fpregs_state_save base:req hold:req 35 mrs \hold, fpsr 36 str \hold, [\base, #CTX_SIMD_FPSR] 37 38 mrs \hold, fpcr 39 str \hold, [\base, #CTX_SIMD_FPCR] 40 41#if CTX_INCLUDE_AARCH32_REGS && CTX_INCLUDE_FPREGS 42 mrs \hold, fpexc32_el2 43 str \hold, [\base, #CTX_SIMD_FPEXC32] 44#endif 45.endm 46 47.macro fpregs_state_restore base:req hold:req 48 ldr \hold, [\base, #CTX_SIMD_FPSR] 49 msr fpsr, \hold 50 51 ldr \hold, [\base, #CTX_SIMD_FPCR] 52 msr fpcr, \hold 53 54#if CTX_INCLUDE_AARCH32_REGS && CTX_INCLUDE_FPREGS 55 ldr \hold, [\base, #CTX_SIMD_FPEXC32] 56 msr fpexc32_el2, \hold 57#endif 58.endm 59 60#endif /* CTX_INCLUDE_FPREGS || CTX_INCLUDE_SVE_REGS */ 61 62/* ------------------------------------------------------------------ 63 * The following function follows the aapcs_64 strictly to use 64 * x9-x17 (temporary caller-saved registers according to AArch64 PCS) 65 * to save floating point register context. It assumes that 'x0' is 66 * pointing to a 'fp_regs' structure where the register context will 67 * be saved. 68 * 69 * Access to VFP registers will trap if CPTR_EL3.TFP is set. 70 * However currently we don't use VFP registers nor set traps in 71 * Trusted Firmware, and assume it's cleared. 72 * 73 * TODO: Revisit when VFP is used in secure world 74 * ------------------------------------------------------------------ 75 */ 76#if CTX_INCLUDE_FPREGS 77func fpregs_context_save 78 /* Save x0 and pass its original value to fpregs_state_save */ 79 mov x1, x0 80 81 stp q0, q1, [x0], #32 82 stp q2, q3, [x0], #32 83 stp q4, q5, [x0], #32 84 stp q6, q7, [x0], #32 85 stp q8, q9, [x0], #32 86 stp q10, q11, [x0], #32 87 stp q12, q13, [x0], #32 88 stp q14, q15, [x0], #32 89 stp q16, q17, [x0], #32 90 stp q18, q19, [x0], #32 91 stp q20, q21, [x0], #32 92 stp q22, q23, [x0], #32 93 stp q24, q25, [x0], #32 94 stp q26, q27, [x0], #32 95 stp q28, q29, [x0], #32 96 stp q30, q31, [x0], #32 97 98 fpregs_state_save x1, x9 99 100 ret 101endfunc fpregs_context_save 102 103/* ------------------------------------------------------------------ 104 * The following function follows the aapcs_64 strictly to use x9-x17 105 * (temporary caller-saved registers according to AArch64 PCS) to 106 * restore floating point register context. It assumes that 'x0' is 107 * pointing to a 'fp_regs' structure from where the register context 108 * will be restored. 109 * 110 * Access to VFP registers will trap if CPTR_EL3.TFP is set. 111 * However currently we don't use VFP registers nor set traps in 112 * Trusted Firmware, and assume it's cleared. 113 * 114 * TODO: Revisit when VFP is used in secure world 115 * ------------------------------------------------------------------ 116 */ 117func fpregs_context_restore 118 /* Save x0 and pass its original value to fpregs_state_restore */ 119 mov x1, x0 120 121 ldp q0, q1, [x0], #32 122 ldp q2, q3, [x0], #32 123 ldp q4, q5, [x0], #32 124 ldp q6, q7, [x0], #32 125 ldp q8, q9, [x0], #32 126 ldp q10, q11, [x0], #32 127 ldp q12, q13, [x0], #32 128 ldp q14, q15, [x0], #32 129 ldp q16, q17, [x0], #32 130 ldp q18, q19, [x0], #32 131 ldp q20, q21, [x0], #32 132 ldp q22, q23, [x0], #32 133 ldp q24, q25, [x0], #32 134 ldp q26, q27, [x0], #32 135 ldp q28, q29, [x0], #32 136 ldp q30, q31, [x0], #32 137 138 fpregs_state_restore x1, x9 139 140 ret 141endfunc fpregs_context_restore 142#endif /* CTX_INCLUDE_FPREGS */ 143 144#if CTX_INCLUDE_SVE_REGS 145/* 146 * Helper macros for SVE predicates save/restore operations. 147 */ 148.macro sve_predicate_op op:req reg:req 149 \op p0, [\reg, #0, MUL VL] 150 \op p1, [\reg, #1, MUL VL] 151 \op p2, [\reg, #2, MUL VL] 152 \op p3, [\reg, #3, MUL VL] 153 \op p4, [\reg, #4, MUL VL] 154 \op p5, [\reg, #5, MUL VL] 155 \op p6, [\reg, #6, MUL VL] 156 \op p7, [\reg, #7, MUL VL] 157 \op p8, [\reg, #8, MUL VL] 158 \op p9, [\reg, #9, MUL VL] 159 \op p10, [\reg, #10, MUL VL] 160 \op p11, [\reg, #11, MUL VL] 161 \op p12, [\reg, #12, MUL VL] 162 \op p13, [\reg, #13, MUL VL] 163 \op p14, [\reg, #14, MUL VL] 164 \op p15, [\reg, #15, MUL VL] 165.endm 166 167.macro sve_vectors_op op:req reg:req 168 \op z0, [\reg, #0, MUL VL] 169 \op z1, [\reg, #1, MUL VL] 170 \op z2, [\reg, #2, MUL VL] 171 \op z3, [\reg, #3, MUL VL] 172 \op z4, [\reg, #4, MUL VL] 173 \op z5, [\reg, #5, MUL VL] 174 \op z6, [\reg, #6, MUL VL] 175 \op z7, [\reg, #7, MUL VL] 176 \op z8, [\reg, #8, MUL VL] 177 \op z9, [\reg, #9, MUL VL] 178 \op z10, [\reg, #10, MUL VL] 179 \op z11, [\reg, #11, MUL VL] 180 \op z12, [\reg, #12, MUL VL] 181 \op z13, [\reg, #13, MUL VL] 182 \op z14, [\reg, #14, MUL VL] 183 \op z15, [\reg, #15, MUL VL] 184 \op z16, [\reg, #16, MUL VL] 185 \op z17, [\reg, #17, MUL VL] 186 \op z18, [\reg, #18, MUL VL] 187 \op z19, [\reg, #19, MUL VL] 188 \op z20, [\reg, #20, MUL VL] 189 \op z21, [\reg, #21, MUL VL] 190 \op z22, [\reg, #22, MUL VL] 191 \op z23, [\reg, #23, MUL VL] 192 \op z24, [\reg, #24, MUL VL] 193 \op z25, [\reg, #25, MUL VL] 194 \op z26, [\reg, #26, MUL VL] 195 \op z27, [\reg, #27, MUL VL] 196 \op z28, [\reg, #28, MUL VL] 197 \op z29, [\reg, #29, MUL VL] 198 \op z30, [\reg, #30, MUL VL] 199 \op z31, [\reg, #31, MUL VL] 200.endm 201 202/* ------------------------------------------------------------------ 203 * The following function follows the aapcs_64 strictly to use x9-x17 204 * (temporary caller-saved registers according to AArch64 PCS) to 205 * restore SVE register context. It assumes that 'x0' is 206 * pointing to a 'sve_regs_t' structure to which the register context 207 * will be saved. 208 * ------------------------------------------------------------------ 209 */ 210func sve_context_save 211.arch_extension sve 212 /* Predicate registers */ 213 mov x13, #CTX_SIMD_PREDICATES 214 add x9, x0, x13 215 sve_predicate_op str, x9 216 217 /* Save FFR after predicates */ 218 mov x13, #CTX_SIMD_FFR 219 add x9, x0, x13 220 rdffr p0.b 221 str p0, [x9] 222 223 /* Save vector registers */ 224 mov x13, #CTX_SIMD_VECTORS 225 add x9, x0, x13 226 sve_vectors_op str, x9 227.arch_extension nosve 228 229 /* Save FPSR, FPCR and FPEXC32 */ 230 fpregs_state_save x0, x9 231 232 ret 233endfunc sve_context_save 234 235/* ------------------------------------------------------------------ 236 * The following function follows the aapcs_64 strictly to use x9-x17 237 * (temporary caller-saved registers according to AArch64 PCS) to 238 * restore SVE register context. It assumes that 'x0' is pointing to 239 * a 'sve_regs_t' structure from where the register context will be 240 * restored. 241 * ------------------------------------------------------------------ 242 */ 243func sve_context_restore 244.arch_extension sve 245 /* Restore FFR register before predicates */ 246 mov x13, #CTX_SIMD_FFR 247 add x9, x0, x13 248 ldr p0, [x9] 249 wrffr p0.b 250 251 /* Restore predicate registers */ 252 mov x13, #CTX_SIMD_PREDICATES 253 add x9, x0, x13 254 sve_predicate_op ldr, x9 255 256 /* Restore vector registers */ 257 mov x13, #CTX_SIMD_VECTORS 258 add x9, x0, x13 259 sve_vectors_op ldr, x9 260.arch_extension nosve 261 262 /* Restore FPSR, FPCR and FPEXC32 */ 263 fpregs_state_restore x0, x9 264 ret 265endfunc sve_context_restore 266#endif /* CTX_INCLUDE_SVE_REGS */ 267 268 /* 269 * Set SCR_EL3.EA bit to enable SErrors at EL3 270 */ 271 .macro enable_serror_at_el3 272 mrs x8, scr_el3 273 orr x8, x8, #SCR_EA_BIT 274 msr scr_el3, x8 275 .endm 276 277 /* 278 * Set the PSTATE bits not set when the exception was taken as 279 * described in the AArch64.TakeException() pseudocode function 280 * in ARM DDI 0487F.c page J1-7635 to a default value. 281 */ 282 .macro set_unset_pstate_bits 283 /* 284 * If Data Independent Timing (DIT) functionality is implemented, 285 * always enable DIT in EL3 286 */ 287#if ENABLE_FEAT_DIT 288#if ENABLE_FEAT_DIT >= 2 289 mrs x8, id_aa64pfr0_el1 290 and x8, x8, #(ID_AA64PFR0_DIT_MASK << ID_AA64PFR0_DIT_SHIFT) 291 cbz x8, 1f 292#endif 293 mov x8, #DIT_BIT 294 msr DIT, x8 2951: 296#endif /* ENABLE_FEAT_DIT */ 297 .endm /* set_unset_pstate_bits */ 298 299/*------------------------------------------------------------------------- 300 * This macro checks the ENABLE_FEAT_MPAM state, performs ID register 301 * check to see if the platform supports MPAM extension and restores MPAM3 302 * register value if it is FEAT_STATE_ENABLED/FEAT_STATE_CHECKED. 303 * 304 * This is particularly more complicated because we can't check 305 * if the platform supports MPAM by looking for status of a particular bit 306 * in the MDCR_EL3 or CPTR_EL3 register like other extensions. 307 * ------------------------------------------------------------------------ 308 */ 309 310 .macro restore_mpam3_el3 311#if ENABLE_FEAT_MPAM 312#if ENABLE_FEAT_MPAM >= 2 313 mrs x8, id_aa64pfr0_el1 314 lsr x8, x8, #(ID_AA64PFR0_MPAM_SHIFT) 315 and x8, x8, #(ID_AA64PFR0_MPAM_MASK) 316 mrs x7, id_aa64pfr1_el1 317 lsr x7, x7, #(ID_AA64PFR1_MPAM_FRAC_SHIFT) 318 and x7, x7, #(ID_AA64PFR1_MPAM_FRAC_MASK) 319 orr x7, x7, x8 320 cbz x7, no_mpam 321#endif 322 /* ----------------------------------------------------------- 323 * Restore MPAM3_EL3 register as per context state 324 * Currently we only enable MPAM for NS world and trap to EL3 325 * for MPAM access in lower ELs of Secure and Realm world 326 * x9 holds address of the per_world context 327 * ----------------------------------------------------------- 328 */ 329 330 ldr x17, [x9, #CTX_MPAM3_EL3] 331 msr S3_6_C10_C5_0, x17 /* mpam3_el3 */ 332 333no_mpam: 334#endif 335 .endm /* restore_mpam3_el3 */ 336 337/* ------------------------------------------------------------------ 338 * The following macro is used to save and restore all the general 339 * purpose and ARMv8.3-PAuth (if enabled) registers. 340 * It also checks if the Secure Cycle Counter (PMCCNTR_EL0) 341 * is disabled in EL3/Secure (ARMv8.5-PMU), wherein PMCCNTR_EL0 342 * needs not to be saved/restored during world switch. 343 * 344 * Ideally we would only save and restore the callee saved registers 345 * when a world switch occurs but that type of implementation is more 346 * complex. So currently we will always save and restore these 347 * registers on entry and exit of EL3. 348 * clobbers: x18 349 * ------------------------------------------------------------------ 350 */ 351 .macro save_gp_pmcr_pauth_regs 352 stp x0, x1, [sp, #CTX_GPREGS_OFFSET + CTX_GPREG_X0] 353 stp x2, x3, [sp, #CTX_GPREGS_OFFSET + CTX_GPREG_X2] 354 stp x4, x5, [sp, #CTX_GPREGS_OFFSET + CTX_GPREG_X4] 355 stp x6, x7, [sp, #CTX_GPREGS_OFFSET + CTX_GPREG_X6] 356 stp x8, x9, [sp, #CTX_GPREGS_OFFSET + CTX_GPREG_X8] 357 stp x10, x11, [sp, #CTX_GPREGS_OFFSET + CTX_GPREG_X10] 358 stp x12, x13, [sp, #CTX_GPREGS_OFFSET + CTX_GPREG_X12] 359 stp x14, x15, [sp, #CTX_GPREGS_OFFSET + CTX_GPREG_X14] 360 stp x16, x17, [sp, #CTX_GPREGS_OFFSET + CTX_GPREG_X16] 361 stp x18, x19, [sp, #CTX_GPREGS_OFFSET + CTX_GPREG_X18] 362 stp x20, x21, [sp, #CTX_GPREGS_OFFSET + CTX_GPREG_X20] 363 stp x22, x23, [sp, #CTX_GPREGS_OFFSET + CTX_GPREG_X22] 364 stp x24, x25, [sp, #CTX_GPREGS_OFFSET + CTX_GPREG_X24] 365 stp x26, x27, [sp, #CTX_GPREGS_OFFSET + CTX_GPREG_X26] 366 stp x28, x29, [sp, #CTX_GPREGS_OFFSET + CTX_GPREG_X28] 367 mrs x18, sp_el0 368 str x18, [sp, #CTX_GPREGS_OFFSET + CTX_GPREG_SP_EL0] 369 370 /* PMUv3 is presumed to be always present */ 371 mrs x9, pmcr_el0 372 str x9, [sp, #CTX_EL3STATE_OFFSET + CTX_PMCR_EL0] 373#if CTX_INCLUDE_PAUTH_REGS 374 /* ---------------------------------------------------------- 375 * Save the ARMv8.3-PAuth keys as they are not banked 376 * by exception level 377 * ---------------------------------------------------------- 378 */ 379 add x19, sp, #CTX_PAUTH_REGS_OFFSET 380 381 mrs x20, APIAKeyLo_EL1 /* x21:x20 = APIAKey */ 382 mrs x21, APIAKeyHi_EL1 383 mrs x22, APIBKeyLo_EL1 /* x23:x22 = APIBKey */ 384 mrs x23, APIBKeyHi_EL1 385 mrs x24, APDAKeyLo_EL1 /* x25:x24 = APDAKey */ 386 mrs x25, APDAKeyHi_EL1 387 mrs x26, APDBKeyLo_EL1 /* x27:x26 = APDBKey */ 388 mrs x27, APDBKeyHi_EL1 389 mrs x28, APGAKeyLo_EL1 /* x29:x28 = APGAKey */ 390 mrs x29, APGAKeyHi_EL1 391 392 stp x20, x21, [x19, #CTX_PACIAKEY_LO] 393 stp x22, x23, [x19, #CTX_PACIBKEY_LO] 394 stp x24, x25, [x19, #CTX_PACDAKEY_LO] 395 stp x26, x27, [x19, #CTX_PACDBKEY_LO] 396 stp x28, x29, [x19, #CTX_PACGAKEY_LO] 397#endif /* CTX_INCLUDE_PAUTH_REGS */ 398 .endm /* save_gp_pmcr_pauth_regs */ 399 400/* ----------------------------------------------------------------- 401 * This function saves the context and sets the PSTATE to a known 402 * state, preparing entry to el3. 403 * Save all the general purpose and ARMv8.3-PAuth (if enabled) 404 * registers. 405 * Then set any of the PSTATE bits that are not set by hardware 406 * according to the Aarch64.TakeException pseudocode in the Arm 407 * Architecture Reference Manual to a default value for EL3. 408 * clobbers: x17 409 * ----------------------------------------------------------------- 410 */ 411func prepare_el3_entry 412 /* 413 * context is about to mutate, so make sure we don't affect any still 414 * in-flight profiling operations. We don't care that they actually 415 * finish, that can still be later. NOP if not present 416 */ 417#if ENABLE_SPE_FOR_NS 418 psb_csync 419#endif 420#if ENABLE_TRBE_FOR_NS 421 tsb_csync 422#endif 423 isb 424 save_gp_pmcr_pauth_regs 425 setup_el3_execution_context 426 ret 427endfunc prepare_el3_entry 428 429/* ------------------------------------------------------------------ 430 * This function restores ARMv8.3-PAuth (if enabled) and all general 431 * purpose registers except x30 from the CPU context. 432 * x30 register must be explicitly restored by the caller. 433 * ------------------------------------------------------------------ 434 */ 435func restore_gp_pmcr_pauth_regs 436#if CTX_INCLUDE_PAUTH_REGS 437 /* Restore the ARMv8.3 PAuth keys */ 438 add x10, sp, #CTX_PAUTH_REGS_OFFSET 439 440 ldp x0, x1, [x10, #CTX_PACIAKEY_LO] /* x1:x0 = APIAKey */ 441 ldp x2, x3, [x10, #CTX_PACIBKEY_LO] /* x3:x2 = APIBKey */ 442 ldp x4, x5, [x10, #CTX_PACDAKEY_LO] /* x5:x4 = APDAKey */ 443 ldp x6, x7, [x10, #CTX_PACDBKEY_LO] /* x7:x6 = APDBKey */ 444 ldp x8, x9, [x10, #CTX_PACGAKEY_LO] /* x9:x8 = APGAKey */ 445 446 msr APIAKeyLo_EL1, x0 447 msr APIAKeyHi_EL1, x1 448 msr APIBKeyLo_EL1, x2 449 msr APIBKeyHi_EL1, x3 450 msr APDAKeyLo_EL1, x4 451 msr APDAKeyHi_EL1, x5 452 msr APDBKeyLo_EL1, x6 453 msr APDBKeyHi_EL1, x7 454 msr APGAKeyLo_EL1, x8 455 msr APGAKeyHi_EL1, x9 456#endif /* CTX_INCLUDE_PAUTH_REGS */ 457 458 /* PMUv3 is presumed to be always present */ 459 ldr x0, [sp, #CTX_EL3STATE_OFFSET + CTX_PMCR_EL0] 460 msr pmcr_el0, x0 461 ldp x0, x1, [sp, #CTX_GPREGS_OFFSET + CTX_GPREG_X0] 462 ldp x2, x3, [sp, #CTX_GPREGS_OFFSET + CTX_GPREG_X2] 463 ldp x4, x5, [sp, #CTX_GPREGS_OFFSET + CTX_GPREG_X4] 464 ldp x6, x7, [sp, #CTX_GPREGS_OFFSET + CTX_GPREG_X6] 465 ldp x8, x9, [sp, #CTX_GPREGS_OFFSET + CTX_GPREG_X8] 466 ldp x10, x11, [sp, #CTX_GPREGS_OFFSET + CTX_GPREG_X10] 467 ldp x12, x13, [sp, #CTX_GPREGS_OFFSET + CTX_GPREG_X12] 468 ldp x14, x15, [sp, #CTX_GPREGS_OFFSET + CTX_GPREG_X14] 469 ldp x16, x17, [sp, #CTX_GPREGS_OFFSET + CTX_GPREG_X16] 470 ldp x18, x19, [sp, #CTX_GPREGS_OFFSET + CTX_GPREG_X18] 471 ldp x20, x21, [sp, #CTX_GPREGS_OFFSET + CTX_GPREG_X20] 472 ldp x22, x23, [sp, #CTX_GPREGS_OFFSET + CTX_GPREG_X22] 473 ldp x24, x25, [sp, #CTX_GPREGS_OFFSET + CTX_GPREG_X24] 474 ldp x26, x27, [sp, #CTX_GPREGS_OFFSET + CTX_GPREG_X26] 475 ldr x28, [sp, #CTX_GPREGS_OFFSET + CTX_GPREG_SP_EL0] 476 msr sp_el0, x28 477 ldp x28, x29, [sp, #CTX_GPREGS_OFFSET + CTX_GPREG_X28] 478 ret 479endfunc restore_gp_pmcr_pauth_regs 480 481#if ERRATA_SPECULATIVE_AT 482/* -------------------------------------------------------------------- 483 * In case of ERRATA_SPECULATIVE_AT, save SCTLR_EL1 and TCR_EL1 484 * registers and update EL1 registers to disable stage1 and stage2 485 * page table walk. 486 * -------------------------------------------------------------------- 487 */ 488func save_and_update_ptw_el1_sys_regs 489 /* ---------------------------------------------------------- 490 * Save only sctlr_el1 and tcr_el1 registers 491 * ---------------------------------------------------------- 492 */ 493 mrs x29, sctlr_el1 494 str x29, [sp, #(CTX_ERRATA_SPEC_AT_OFFSET + CTX_ERRATA_SPEC_AT_SCTLR_EL1)] 495 mrs x29, tcr_el1 496 str x29, [sp, #(CTX_ERRATA_SPEC_AT_OFFSET + CTX_ERRATA_SPEC_AT_TCR_EL1)] 497 498 /* ------------------------------------------------------------ 499 * Must follow below order in order to disable page table 500 * walk for lower ELs (EL1 and EL0). First step ensures that 501 * page table walk is disabled for stage1 and second step 502 * ensures that page table walker should use TCR_EL1.EPDx 503 * bits to perform address translation. ISB ensures that CPU 504 * does these 2 steps in order. 505 * 506 * 1. Update TCR_EL1.EPDx bits to disable page table walk by 507 * stage1. 508 * 2. Enable MMU bit to avoid identity mapping via stage2 509 * and force TCR_EL1.EPDx to be used by the page table 510 * walker. 511 * ------------------------------------------------------------ 512 */ 513 orr x29, x29, #(TCR_EPD0_BIT) 514 orr x29, x29, #(TCR_EPD1_BIT) 515 msr tcr_el1, x29 516 isb 517 mrs x29, sctlr_el1 518 orr x29, x29, #SCTLR_M_BIT 519 msr sctlr_el1, x29 520 isb 521 ret 522endfunc save_and_update_ptw_el1_sys_regs 523 524#endif /* ERRATA_SPECULATIVE_AT */ 525 526/* ----------------------------------------------------------------- 527* The below macro returns the address of the per_world context for 528* the security state, retrieved through "get_security_state" macro. 529* The per_world context address is returned in the register argument. 530* Clobbers: x9, x10 531* ------------------------------------------------------------------ 532*/ 533 534.macro get_per_world_context _reg:req 535 ldr x10, [sp, #CTX_EL3STATE_OFFSET + CTX_SCR_EL3] 536 get_security_state x9, x10 537 mov_imm x10, (CTX_PERWORLD_EL3STATE_END - CTX_CPTR_EL3) 538 mul x9, x9, x10 539 adrp x10, per_world_context 540 add x10, x10, :lo12:per_world_context 541 add x9, x9, x10 542 mov \_reg, x9 543.endm 544 545/* ------------------------------------------------------------------ 546 * This routine assumes that the SP_EL3 is pointing to a valid 547 * context structure from where the gp regs and other special 548 * registers can be retrieved. 549 * ------------------------------------------------------------------ 550 */ 551func el3_exit 552#if ENABLE_ASSERTIONS 553 /* el3_exit assumes SP_EL0 on entry */ 554 mrs x17, spsel 555 cmp x17, #MODE_SP_EL0 556 ASM_ASSERT(eq) 557#endif /* ENABLE_ASSERTIONS */ 558 559 /* ---------------------------------------------------------- 560 * Save the current SP_EL0 i.e. the EL3 runtime stack which 561 * will be used for handling the next SMC. 562 * Then switch to SP_EL3. 563 * ---------------------------------------------------------- 564 */ 565 mov x17, sp 566 msr spsel, #MODE_SP_ELX 567 str x17, [sp, #CTX_EL3STATE_OFFSET + CTX_RUNTIME_SP] 568 569 /* ---------------------------------------------------------- 570 * Restore CPTR_EL3. 571 * ---------------------------------------------------------- */ 572 573 /* The address of the per_world context is stored in x9 */ 574 get_per_world_context x9 575 576 ldp x19, x20, [x9, #CTX_CPTR_EL3] 577 msr cptr_el3, x19 578 579#if IMAGE_BL31 580 restore_mpam3_el3 581 582#endif /* IMAGE_BL31 */ 583 584#if IMAGE_BL31 && DYNAMIC_WORKAROUND_CVE_2018_3639 585 /* ---------------------------------------------------------- 586 * Restore mitigation state as it was on entry to EL3 587 * ---------------------------------------------------------- 588 */ 589 ldr x17, [sp, #CTX_CVE_2018_3639_OFFSET + CTX_CVE_2018_3639_DISABLE] 590 cbz x17, 1f 591 blr x17 5921: 593#endif /* IMAGE_BL31 && DYNAMIC_WORKAROUND_CVE_2018_3639 */ 594 595#if IMAGE_BL31 596 synchronize_errors 597#endif /* IMAGE_BL31 */ 598 599 /* -------------------------------------------------------------- 600 * Restore MDCR_EL3, SPSR_EL3, ELR_EL3 and SCR_EL3 prior to ERET 601 * -------------------------------------------------------------- 602 */ 603 ldp x16, x17, [sp, #CTX_EL3STATE_OFFSET + CTX_SPSR_EL3] 604 ldr x18, [sp, #CTX_EL3STATE_OFFSET + CTX_SCR_EL3] 605 ldr x19, [sp, #CTX_EL3STATE_OFFSET + CTX_MDCR_EL3] 606 msr spsr_el3, x16 607 msr elr_el3, x17 608 msr scr_el3, x18 609 msr mdcr_el3, x19 610 611 restore_ptw_el1_sys_regs 612 613 /* ---------------------------------------------------------- 614 * Restore general purpose (including x30), PMCR_EL0 and 615 * ARMv8.3-PAuth registers. 616 * Exit EL3 via ERET to a lower exception level. 617 * ---------------------------------------------------------- 618 */ 619 bl restore_gp_pmcr_pauth_regs 620 ldr x30, [sp, #CTX_GPREGS_OFFSET + CTX_GPREG_LR] 621 622#ifdef IMAGE_BL31 623 /* Clear the EL3 flag as we are exiting el3 */ 624 str xzr, [sp, #CTX_EL3STATE_OFFSET + CTX_NESTED_EA_FLAG] 625#endif /* IMAGE_BL31 */ 626 627 exception_return 628 629endfunc el3_exit 630