1 /* 2 * Copyright (c) 2019-2023, Intel Corporation. All rights reserved. 3 * Copyright (c) 2024-2025, Altera Corporation. All rights reserved. 4 * 5 * SPDX-License-Identifier: BSD-3-Clause 6 */ 7 8 #ifndef SOCFPGA_MBOX_H 9 #define SOCFPGA_MBOX_H 10 11 #include <lib/utils_def.h> 12 13 #if PLATFORM_MODEL == PLAT_SOCFPGA_AGILEX5 14 #define MBOX_OFFSET 0x10a30000 15 #else 16 #define MBOX_OFFSET 0xffa30000 17 #endif 18 19 #define MBOX_ATF_CLIENT_ID 0x1U 20 #define MBOX_MAX_JOB_ID 0xFU 21 #define MBOX_MAX_IND_JOB_ID (MBOX_MAX_JOB_ID - 1U) 22 #define MBOX_JOB_ID MBOX_MAX_JOB_ID 23 #define MBOX_TEST_BIT BIT(31) 24 25 /* Mailbox Shared Memory Register Map */ 26 #define MBOX_CIN 0x00 /* Command valid offset, to SDM */ 27 #define MBOX_ROUT 0x04 /* Response output offset, to SDM */ 28 #define MBOX_URG 0x08 /* Urgent command, to SDM */ 29 #define MBOX_INT 0x0C /* Interrupt enables, to SDM */ 30 /* 0x10 - 0x1F, Reserved */ 31 32 #define MBOX_COUT 0x20 /* Command free offset, from SDM */ 33 #define MBOX_RIN 0x24 /* Response valid offset, from SDM */ 34 #define MBOX_STATUS 0x2C /* Mailbox status from SDM to client */ 35 /* 0x30 - 0x3F, Reserved */ 36 37 #define MBOX_CMD_BUFFER 0x40 /* Circular buffer, cmds to SDM */ 38 #define MBOX_RESP_BUFFER 0xC0 /* Circular buffer, resp from SDM */ 39 40 #define MBOX_DOORBELL_TO_SDM 0x400 /* Doorbell from HPS to SDM */ 41 #define MBOX_DOORBELL_FROM_SDM 0x480 /* Doorbell from SDM to HPS */ 42 43 /* Mailbox commands */ 44 45 #define MBOX_CMD_NOOP 0x00 46 #define MBOX_CMD_SYNC 0x01 47 #define MBOX_CMD_RESTART 0x02 48 #define MBOX_CMD_CANCEL 0x03 49 #define MBOX_CMD_VAB_SRC_CERT 0x0B 50 #define MBOX_CMD_GET_IDCODE 0x10 51 #define MBOX_CMD_GET_USERCODE 0x13 52 #define MBOX_CMD_GET_CHIPID 0x12 53 #define MBOX_CMD_FPGA_CONFIG_COMP 0x45 54 #define MBOX_CMD_REBOOT_HPS 0x47 55 56 /* Reconfiguration Commands */ 57 #define MBOX_CONFIG_STATUS 0x04 58 #define MBOX_RECONFIG 0x06 59 #define MBOX_RECONFIG_DATA 0x08 60 #define MBOX_RECONFIG_STATUS 0x09 61 62 /* HWMON Commands */ 63 #define MBOX_HWMON_READVOLT 0x18 64 #define MBOX_HWMON_READTEMP 0x19 65 66 /* QSPI Commands */ 67 #define MBOX_CMD_QSPI_OPEN 0x32 68 #define MBOX_CMD_QSPI_CLOSE 0x33 69 #define MBOX_CMD_QSPI_SET_CS 0x34 70 #define MBOX_CMD_QSPI_ERASE 0x38 71 #define MBOX_CMD_QSPI_WRITE 0x39 72 #define MBOX_CMD_QSPI_READ 0x3A 73 #define MBOX_CMD_QSPI_DIRECT 0x3B 74 #define MBOX_CMD_QSPI_GET_DEV_INFO 0x74 75 76 /* SEU Commands */ 77 #define MBOX_CMD_SEU_ERR_READ 0x3C 78 #define MBOX_CMD_SAFE_INJECT_SEU_ERR 0x41 79 80 /* RSU Commands */ 81 #define MBOX_GET_SUBPARTITION_TABLE 0x5A 82 #define MBOX_RSU_STATUS 0x5B 83 #define MBOX_RSU_UPDATE 0x5C 84 #define MBOX_HPS_STAGE_NOTIFY 0x5D 85 #define MBOX_RSU_GET_DEVICE_INFO 0x74 86 87 /* FCS Command */ 88 #define MBOX_FCS_GET_PROVISION 0x7B 89 #define MBOX_FCS_CNTR_SET_PREAUTH 0x7C 90 #define MBOX_FCS_ENCRYPT_REQ 0x7E 91 #define MBOX_FCS_DECRYPT_REQ 0x7F 92 #define MBOX_FCS_RANDOM_GEN 0x80 93 #define MBOX_FCS_AES_CRYPT_REQ 0x81 94 #define MBOX_FCS_GET_DIGEST_REQ 0x82 95 #define MBOX_FCS_MAC_VERIFY_REQ 0x83 96 #define MBOX_FCS_ECDSA_HASH_SIGN_REQ 0x84 97 #define MBOX_FCS_ECDSA_SHA2_DATA_SIGN_REQ 0x85 98 #define MBOX_FCS_ECDSA_HASH_SIG_VERIFY 0x86 99 #define MBOX_FCS_ECDSA_SHA2_DATA_SIGN_VERIFY 0x87 100 #define MBOX_FCS_ECDSA_GET_PUBKEY 0x88 101 #define MBOX_FCS_ECDH_REQUEST 0x89 102 #define MBOX_FCS_HKDF_REQUEST 0x8B 103 #define MBOX_FCS_OPEN_CS_SESSION 0xA0 104 #define MBOX_FCS_CLOSE_CS_SESSION 0xA1 105 #define MBOX_FCS_IMPORT_CS_KEY 0xA5 106 #define MBOX_FCS_EXPORT_CS_KEY 0xA6 107 #define MBOX_FCS_REMOVE_CS_KEY 0xA7 108 #define MBOX_FCS_GET_CS_KEY_INFO 0xA8 109 #define MBOX_FCS_CREATE_CS_KEY 0xA9 110 111 /* PSG SIGMA Commands */ 112 #define MBOX_PSG_SIGMA_TEARDOWN 0xD5 113 114 /* Attestation Commands */ 115 #define MBOX_CREATE_CERT_ON_RELOAD 0x180 116 #define MBOX_GET_ATTESTATION_CERT 0x181 117 #define MBOX_ATTESTATION_SUBKEY 0x182 118 #define MBOX_GET_MEASUREMENT 0x183 119 120 /* Miscellaneous commands */ 121 #define MBOX_CMD_MCTP_MSG 0x194 122 #define MBOX_GET_ROM_PATCH_SHA384 0x1B0 123 #define MBOX_CMD_GET_DEVICEID 0x500 124 125 /* Mailbox Definitions */ 126 127 #define CMD_DIRECT 0 128 #define CMD_INDIRECT 1 129 #define CMD_CASUAL 0 130 #define CMD_URGENT 1 131 132 /* Mailbox command flags and related macros */ 133 #define MBOX_CMD_FLAG_DIRECT BIT(0) 134 #define MBOX_CMD_FLAG_INDIRECT BIT(1) 135 #define MBOX_CMD_FLAG_CASUAL BIT(2) 136 #define MBOX_CMD_FLAG_URGENT BIT(3) 137 138 #define MBOX_CMD_FLAG_CASUAL_INDIRECT (MBOX_CMD_FLAG_CASUAL | \ 139 MBOX_CMD_FLAG_INDIRECT) 140 141 #define IS_CMD_SET(cmd, _type) ((((cmd) & MBOX_CMD_FLAG_##_type) != 0) ? \ 142 1 : 0) 143 144 #define MBOX_WORD_BYTE 4U 145 #define MBOX_RESP_BUFFER_SIZE 16 146 #define MBOX_CMD_BUFFER_SIZE 32 147 #define MBOX_INC_HEADER_MAX_WORD_SIZE 1024U 148 149 /* Execution states for HPS_STAGE_NOTIFY */ 150 #define HPS_EXECUTION_STATE_FSBL 0 151 #define HPS_EXECUTION_STATE_SSBL 1 152 #define HPS_EXECUTION_STATE_OS 2 153 154 /* Status Response */ 155 #define MBOX_RET_OK 0 156 #define MBOX_RET_ERROR -1 157 #define MBOX_NO_RESPONSE -2 158 #define MBOX_WRONG_ID -3 159 #define MBOX_BUFFER_FULL -4 160 #define MBOX_BUSY -5 161 #define MBOX_TIMEOUT -2047 162 163 /* Key Status */ 164 #define MBOX_RET_SDOS_DECRYPTION_ERROR_102 -258 165 #define MBOX_RET_SDOS_DECRYPTION_ERROR_103 -259 166 167 /* Reconfig Status Response */ 168 #define RECONFIG_STATUS_STATE 0 169 #define RECONFIG_STATUS_PIN_STATUS 2 170 #define RECONFIG_STATUS_SOFTFUNC_STATUS 3 171 #define PIN_STATUS_NSTATUS (U(1) << 31) 172 #define SOFTFUNC_STATUS_SEU_ERROR (1 << 3) 173 #define SOFTFUNC_STATUS_INIT_DONE (1 << 1) 174 #define SOFTFUNC_STATUS_CONF_DONE (1 << 0) 175 #define MBOX_CFGSTAT_STATE_IDLE 0x00000000 176 #define MBOX_CFGSTAT_STATE_CONFIG 0x10000000 177 #define MBOX_CFGSTAT_VAB_BS_PREAUTH 0x20000000 178 #define MBOX_CFGSTAT_STATE_FAILACK 0x08000000 179 #define MBOX_CFGSTAT_STATE_ERROR_INVALID 0xf0000001 180 #define MBOX_CFGSTAT_STATE_ERROR_CORRUPT 0xf0000002 181 #define MBOX_CFGSTAT_STATE_ERROR_AUTH 0xf0000003 182 #define MBOX_CFGSTAT_STATE_ERROR_CORE_IO 0xf0000004 183 #define MBOX_CFGSTAT_STATE_ERROR_HARDWARE 0xf0000005 184 #define MBOX_CFGSTAT_STATE_ERROR_FAKE 0xf0000006 185 #define MBOX_CFGSTAT_STATE_ERROR_BOOT_INFO 0xf0000007 186 #define MBOX_CFGSTAT_STATE_ERROR_QSPI_ERROR 0xf0000008 187 188 189 /* Mailbox Macros */ 190 191 #define MBOX_ENTRY_TO_ADDR(_buf, ptr) (MBOX_OFFSET + (MBOX_##_buf##_BUFFER) \ 192 + MBOX_WORD_BYTE * (ptr)) 193 194 /* Mailbox interrupt flags and masks */ 195 #define MBOX_INT_FLAG_COE BIT(0) /* COUT update interrupt enable */ 196 #define MBOX_INT_FLAG_RIE BIT(1) /* RIN update interrupt enable */ 197 #define MBOX_INT_FLAG_UAE BIT(8) /* Urgent ACK interrupt enable */ 198 199 #define MBOX_COE_BIT(INTERRUPT) ((INTERRUPT) & MBOX_INT_FLAG_COE) 200 #define MBOX_RIE_BIT(INTERRUPT) ((INTERRUPT) & MBOX_INT_FLAG_RIE) 201 #define MBOX_UAE_BIT(INTERRUPT) ((INTERRUPT) & MBOX_INT_FLAG_UAE) 202 203 /* Mailbox response and status */ 204 #define MBOX_RESP_ERR(BUFFER) ((BUFFER) & 0x000007ff) 205 #define MBOX_RESP_LEN(BUFFER) (((BUFFER) & 0x007ff000) >> 12) 206 #define MBOX_RESP_CLIENT_ID(BUFFER) (((BUFFER) & 0xf0000000) >> 28) 207 #define MBOX_RESP_JOB_ID(BUFFER) (((BUFFER) & 0x0f000000) >> 24) 208 #define MBOX_RESP_TRANSACTION_ID(BUFFER) (((BUFFER) & 0xff000000) >> 24) 209 #define MBOX_STATUS_UA_MASK (1<<8) 210 211 /* Mailbox command and response */ 212 #define MBOX_CLIENT_ID_CMD(CLIENT_ID) ((CLIENT_ID) << 28) 213 #define MBOX_JOB_ID_CMD(JOB_ID) (JOB_ID << 24) 214 #define MBOX_CMD_LEN_CMD(CMD_LEN) ((CMD_LEN) << 12) 215 #define MBOX_INDIRECT(val) ((val) << 11) 216 #define MBOX_CMD_MASK(header) ((header) & 0x7ff) 217 218 /* Mailbox payload */ 219 #define MBOX_DATA_MAX_LEN 0x3ff 220 #define MBOX_PAYLOAD_FLAG_BUSY BIT(0) 221 222 /* RSU Macros */ 223 #define RSU_VERSION_ACMF BIT(8) 224 #define RSU_VERSION_ACMF_MASK 0xff00 225 226 /* Config Status Macros */ 227 #define CONFIG_STATUS_WORD_SIZE 16U 228 #define CONFIG_STATUS_FW_VER_OFFSET 1 229 #define CONFIG_STATUS_FW_VER_MASK 0x00FFFFFF 230 231 /* QSPI mailbox command macros */ 232 #define MBOX_QSPI_SET_CS_OFFSET (28) 233 #define MBOX_QSPI_SET_CS_MODE_OFFSET (27) 234 #define MBOX_QSPI_SET_CS_CA_OFFSET (26) 235 #define MBOX_QSPI_ERASE_SIZE_GRAN (0x400) 236 237 #define MBOX_4K_ALIGNED_MASK (0xFFF) 238 #define MBOX_IS_4K_ALIGNED(x) ((x) & MBOX_4K_ALIGNED_MASK) 239 #define MBOX_IS_WORD_ALIGNED(x) (!((x) & 0x3)) 240 #define MBOX_QSPI_RW_MAX_WORDS (0x1000) 241 242 /* Data structure */ 243 244 typedef struct mailbox_payload { 245 uint32_t header; 246 uint32_t data[MBOX_DATA_MAX_LEN]; 247 } mailbox_payload_t; 248 249 typedef struct mailbox_container { 250 uint32_t flag; 251 uint32_t index; 252 mailbox_payload_t *payload; 253 } mailbox_container_t; 254 255 /* Mailbox Function Definitions */ 256 257 void mailbox_set_int(uint32_t interrupt_input); 258 int mailbox_init(void); 259 void mailbox_set_qspi_close(void); 260 void mailbox_hps_qspi_enable(void); 261 262 int mailbox_send_cmd(uint32_t job_id, uint32_t cmd, uint32_t *args, 263 unsigned int len, uint32_t urgent, uint32_t *response, 264 unsigned int *resp_len); 265 int mailbox_send_cmd_async(uint32_t *job_id, uint32_t cmd, uint32_t *args, 266 unsigned int len, unsigned int indirect); 267 int mailbox_send_cmd_async_ext(uint32_t header_cmd, uint32_t *args, 268 unsigned int len); 269 int mailbox_read_response(uint32_t *job_id, uint32_t *response, 270 unsigned int *resp_len); 271 int mailbox_read_response_async(uint32_t *job_id, uint32_t *header, 272 uint32_t *response, unsigned int *resp_len, 273 uint8_t ignore_client_id); 274 int iterate_resp(uint32_t mbox_resp_len, uint32_t *resp_buf, 275 unsigned int *resp_len); 276 277 void mailbox_reset_cold(void); 278 void mailbox_reset_warm(uint32_t reset_type); 279 void mailbox_clear_response(void); 280 281 int intel_mailbox_get_config_status(uint32_t cmd, bool init_done, 282 uint32_t *err_states); 283 int intel_mailbox_is_fpga_not_ready(void); 284 285 #if PLATFORM_MODEL == PLAT_SOCFPGA_AGILEX5 286 void intel_smmu_hps_remapper_init(uint64_t *mem); 287 int intel_smmu_hps_remapper_config(uint32_t remapper_bypass); 288 #endif 289 290 int mailbox_rsu_get_spt_offset(uint32_t *resp_buf, uint32_t resp_buf_len); 291 int mailbox_rsu_status(uint32_t *resp_buf, uint32_t resp_buf_len); 292 int mailbox_rsu_get_device_info(uint32_t *resp_buf, uint32_t resp_buf_len); 293 int mailbox_rsu_update(uint32_t *flash_offset); 294 int mailbox_hps_stage_notify(uint32_t execution_stage); 295 int mailbox_hwmon_readtemp(uint32_t chan, uint32_t *resp_buf); 296 int mailbox_hwmon_readvolt(uint32_t chan, uint32_t *resp_buf); 297 int mailbox_seu_err_status(uint32_t *resp_buf, uint32_t resp_buf_len); 298 int mailbox_safe_inject_seu_err(uint32_t *arg, unsigned int len); 299 300 int mailbox_send_fpga_config_comp(void); 301 302 #if SIP_SVC_V3 303 #define MBOX_CLIENT_ID_SHIFT (28) 304 #define MBOX_JOB_ID_SHIFT (24) 305 #define MBOX_CMD_LEN_SHIFT (12) 306 #define MBOX_INDIRECT_SHIFT (11) 307 308 #define MBOX_FRAME_CMD_HEADER(client_id, job_id, args_len, indirect, cmd)\ 309 ((client_id << MBOX_CLIENT_ID_SHIFT) | \ 310 (job_id << MBOX_JOB_ID_SHIFT) | \ 311 (args_len << MBOX_CMD_LEN_SHIFT) | \ 312 (indirect << MBOX_CMD_LEN_SHIFT) | \ 313 cmd) 314 315 #define FLAG_SDM_RESPONSE_IS_VALID BIT(0) 316 #define FLAG_SDM_RESPONSE_IS_USED BIT(1) 317 #define FLAG_SDM_RESPONSE_IS_IN_PROGRESS BIT(2) 318 #define FLAG_SDM_RESPONSE_IS_POLL_ON_INTR BIT(3) 319 320 /* 321 * TODO: Re-visit this queue size based on the system load. 322 * 4 bits for client ID and 4 bits for job ID, total 8 bits and we can have up to 323 * 256 transactions. We can tune this based on our system load at any given time 324 */ 325 #define MBOX_SVC_CMD_QUEUE_SIZE (32) 326 #define MBOX_SVC_RESP_QUEUE_SIZE (32) 327 #define MBOX_SVC_MAX_JOB_ID (16) 328 #define MBOX_SVC_CMD_ARG_SIZE (2) 329 #define MBOX_SVC_CMD_IS_USED BIT(0) 330 #define MBOX_SVC_CMD_CB_ARGS_SIZE (4) 331 #define MBOX_SVC_MAX_CLIENTS (16) 332 #define MBOX_SVC_MAX_RESP_DATA_SIZE (32) 333 #define MBOX_SVC_SMC_RET_MAX_SIZE (8) 334 335 /* Client ID(4bits) + Job ID(4bits) = Transcation ID(TID - 8bits, 256 combinations) */ 336 #define MBOX_MAX_TIDS (256) 337 /* Each transcation ID bitmap holds 64bits */ 338 #define MBOX_TID_BITMAP_SIZE (sizeof(uint64_t) * 8) 339 /* Number of transcation ID bitmaps required to hold 256 combinations */ 340 #define MBOX_MAX_TIDS_BITMAP (MBOX_MAX_TIDS / MBOX_TID_BITMAP_SIZE) 341 342 /* SDM Response State (SRS) enums */ 343 typedef enum sdm_resp_state { 344 SRS_WAIT_FOR_RESP = 0x00U, 345 SRS_WAIT_FOR_HEADER, 346 SRS_WAIT_FOR_ARGUMENTS, 347 SRS_SYNC_ERROR 348 } sdm_resp_state_t; 349 350 /* SDM response data structure */ 351 typedef struct sdm_response { 352 bool is_poll_intr; 353 uint8_t client_id; 354 uint8_t job_id; 355 uint16_t resp_len; 356 uint16_t err_code; 357 uint32_t flags; 358 uint32_t header; 359 uint16_t rcvd_resp_len; 360 uint32_t resp_data[MBOX_SVC_MAX_RESP_DATA_SIZE]; 361 } sdm_response_t; 362 363 /* SDM client callback template */ 364 typedef uint8_t (*sdm_command_callback)(void *resp, void *cmd, 365 uint32_t *ret_args); 366 367 /* SDM command data structure */ 368 typedef struct sdm_command { 369 uint8_t client_id; 370 uint8_t job_id; 371 uint32_t flags; 372 sdm_command_callback cb; 373 uint32_t *cb_args; 374 uint8_t cb_args_len; 375 } sdm_command_t; 376 377 /* Get the transcation ID from client ID and job ID. */ 378 #define MBOX_GET_TRANS_ID(cid, jib) (((cid) << 4) | (jib)) 379 380 /* Mailbox service data structure */ 381 typedef struct mailbox_service { 382 sdm_resp_state_t resp_state; 383 sdm_resp_state_t next_resp_state; 384 uint32_t flags; 385 int curr_di; 386 uint64_t received_bitmap[MBOX_MAX_TIDS_BITMAP]; 387 uint64_t interrupt_bitmap[MBOX_MAX_TIDS_BITMAP]; 388 sdm_command_t cmd_queue[MBOX_SVC_CMD_QUEUE_SIZE]; 389 sdm_response_t resp_queue[MBOX_SVC_RESP_QUEUE_SIZE]; 390 } mailbox_service_t; 391 392 int mailbox_send_cmd_async_v3(uint8_t client_id, uint8_t job_id, uint32_t cmd, 393 uint32_t *args, uint32_t args_len, uint8_t cmd_flag, 394 sdm_command_callback cb, uint32_t *cb_args, 395 uint32_t cb_args_len); 396 397 int mailbox_response_poll_v3(uint8_t client_id, uint8_t job_id, uint32_t *ret_args, 398 uint32_t *ret_args_size); 399 400 int mailbox_response_poll_on_intr_v3(uint8_t *client_id, uint8_t *job_id, 401 uint64_t *bitmap); 402 403 #endif /* #if SIP_SVC_V3 */ 404 405 #endif /* SOCFPGA_MBOX_H */ 406