1/* 2 * Copyright (c) 2017-2025, Arm Limited and Contributors. All rights reserved. 3 * 4 * SPDX-License-Identifier: BSD-3-Clause 5 */ 6 7#include <arch.h> 8#include <asm_macros.S> 9#include <cortex_a75.h> 10#include <cpuamu.h> 11#include <cpu_macros.S> 12#include <dsu_macros.S> 13 14.global check_erratum_cortex_a75_764081 15 16/* Hardware handled coherency */ 17#if HW_ASSISTED_COHERENCY == 0 18#error "Cortex-A75 must be compiled with HW_ASSISTED_COHERENCY enabled" 19#endif 20 21cpu_reset_prologue cortex_a75 22 23workaround_reset_start cortex_a75, ERRATUM(764081), ERRATA_A75_764081 24 sysreg_bit_set sctlr_el3, SCTLR_IESB_BIT 25workaround_reset_end cortex_a75, ERRATUM(764081) 26 27check_erratum_ls cortex_a75, ERRATUM(764081), CPU_REV(0, 0) 28 29workaround_reset_start cortex_a75, ERRATUM(790748), ERRATA_A75_790748 30 sysreg_bit_set CORTEX_A75_CPUACTLR_EL1, (1 << 13) 31workaround_reset_end cortex_a75, ERRATUM(790748) 32 33check_erratum_ls cortex_a75, ERRATUM(790748), CPU_REV(0, 0) 34 35workaround_reset_start cortex_a75, ERRATUM(798953), ERRATA_DSU_798953 36 errata_dsu_798953_wa_impl 37workaround_reset_end cortex_a75, ERRATUM(798953) 38 39check_erratum_custom_start cortex_a75, ERRATUM(798953) 40 check_errata_dsu_798953_impl 41 ret 42check_erratum_custom_end cortex_a75, ERRATUM(798953) 43 44workaround_reset_start cortex_a75, ERRATUM(936184), ERRATA_DSU_936184 45 errata_dsu_936184_wa_impl 46workaround_reset_end cortex_a75, ERRATUM(936184) 47 48check_erratum_custom_start cortex_a75, ERRATUM(936184) 49 check_errata_dsu_936184_impl 50 ret 51check_erratum_custom_end cortex_a75, ERRATUM(936184) 52 53workaround_reset_start cortex_a75, CVE(2017, 5715), WORKAROUND_CVE_2017_5715 54#if IMAGE_BL31 55 override_vector_table wa_cve_2017_5715_bpiall_vbar 56#endif /* IMAGE_BL31 */ 57workaround_reset_end cortex_a75, CVE(2017, 5715) 58 59check_erratum_custom_start cortex_a75, CVE(2017, 5715) 60 cpu_check_csv2 x0, 1f 61#if WORKAROUND_CVE_2017_5715 62 mov x0, #ERRATA_APPLIES 63#else 64 mov x0, #ERRATA_MISSING 65#endif 66 ret 671: 68 mov x0, #ERRATA_NOT_APPLIES 69 ret 70check_erratum_custom_end cortex_a75, CVE(2017, 5715) 71 72workaround_reset_start cortex_a75, CVE(2018, 3639), WORKAROUND_CVE_2018_3639 73 sysreg_bit_set CORTEX_A75_CPUACTLR_EL1, CORTEX_A75_CPUACTLR_EL1_DISABLE_LOAD_PASS_STORE 74workaround_reset_end cortex_a75, CVE(2018, 3639) 75 76check_erratum_chosen cortex_a75, CVE(2018, 3639), WORKAROUND_CVE_2018_3639 77 78workaround_reset_start cortex_a75, CVE(2022, 23960), WORKAROUND_CVE_2022_23960 79#if IMAGE_BL31 80 /* Skip installing vector table again if already done for CVE(2017, 5715) */ 81 adr x0, wa_cve_2017_5715_bpiall_vbar 82 mrs x1, vbar_el3 83 cmp x0, x1 84 b.eq 1f 85 msr vbar_el3, x0 861: 87#endif /* IMAGE_BL31 */ 88workaround_reset_end cortex_a75, CVE(2022, 23960) 89 90check_erratum_custom_start cortex_a75, CVE(2022, 23960) 91#if WORKAROUND_CVE_2017_5715 || WORKAROUND_CVE_2022_23960 92 cpu_check_csv2 x0, 1f 93 mov x0, #ERRATA_APPLIES 94 ret 951: 96# if WORKAROUND_CVE_2022_23960 97 mov x0, #ERRATA_APPLIES 98# else 99 mov x0, #ERRATA_MISSING 100# endif /* WORKAROUND_CVE_2022_23960 */ 101 ret 102#endif /* WORKAROUND_CVE_2017_5715 || WORKAROUND_CVE_2022_23960 */ 103 mov x0, #ERRATA_MISSING 104 ret 105check_erratum_custom_end cortex_a75, CVE(2022, 23960) 106 107 /* ------------------------------------------------- 108 * The CPU Ops reset function for Cortex-A75. 109 * ------------------------------------------------- 110 */ 111 112cpu_reset_func_start cortex_a75 113#if ENABLE_FEAT_AMU 114 /* Make sure accesses from EL0/EL1 and EL2 are not trapped to EL3 */ 115 sysreg_bit_set actlr_el3, CORTEX_A75_ACTLR_AMEN_BIT 116 isb 117 118 /* Make sure accesses from EL0/EL1 are not trapped to EL2 */ 119 sysreg_bit_set actlr_el2, CORTEX_A75_ACTLR_AMEN_BIT 120 isb 121 122 /* Enable group0 counters */ 123 mov x0, #CORTEX_A75_AMU_GROUP0_MASK 124 msr CPUAMCNTENSET_EL0, x0 125 isb 126 127 /* Enable group1 counters */ 128 mov x0, #CORTEX_A75_AMU_GROUP1_MASK 129 msr CPUAMCNTENSET_EL0, x0 130 /* isb included in cpu_reset_func_end macro */ 131#endif 132cpu_reset_func_end cortex_a75 133 134func check_smccc_arch_workaround_3 135 mov x0, #ERRATA_APPLIES 136 ret 137endfunc check_smccc_arch_workaround_3 138 139 /* --------------------------------------------- 140 * HW will do the cache maintenance while powering down 141 * --------------------------------------------- 142 */ 143func cortex_a75_core_pwr_dwn 144 /* --------------------------------------------- 145 * Enable CPU power down bit in power control register 146 * --------------------------------------------- 147 */ 148 sysreg_bit_set CORTEX_A75_CPUPWRCTLR_EL1, \ 149 CORTEX_A75_CORE_PWRDN_EN_MASK 150 isb 151 ret 152endfunc cortex_a75_core_pwr_dwn 153 154 /* --------------------------------------------- 155 * This function provides cortex_a75 specific 156 * register information for crash reporting. 157 * It needs to return with x6 pointing to 158 * a list of register names in ascii and 159 * x8 - x15 having values of registers to be 160 * reported. 161 * --------------------------------------------- 162 */ 163.section .rodata.cortex_a75_regs, "aS" 164cortex_a75_regs: /* The ascii list of register names to be reported */ 165 .asciz "cpuectlr_el1", "" 166 167func cortex_a75_cpu_reg_dump 168 adr x6, cortex_a75_regs 169 mrs x8, CORTEX_A75_CPUECTLR_EL1 170 ret 171endfunc cortex_a75_cpu_reg_dump 172 173declare_cpu_ops_wa cortex_a75, CORTEX_A75_MIDR, \ 174 cortex_a75_reset_func, \ 175 check_erratum_cortex_a75_5715, \ 176 CPU_NO_EXTRA2_FUNC, \ 177 check_smccc_arch_workaround_3, \ 178 cortex_a75_core_pwr_dwn 179