1 /* 2 * Copyright (c) 2015-2024, Arm Limited and Contributors. All rights reserved. 3 * 4 * SPDX-License-Identifier: BSD-3-Clause 5 */ 6 7 #include <assert.h> 8 #include <errno.h> 9 10 #include <arch_helpers.h> 11 #include <bl32/sp_min/platform_sp_min.h> 12 #include <common/debug.h> 13 #include <drivers/arm/gic_common.h> 14 #include <drivers/arm/gicv2.h> 15 #include <drivers/clk.h> 16 #include <drivers/st/stm32mp_reset.h> 17 #include <dt-bindings/clock/stm32mp1-clks.h> 18 #include <lib/mmio.h> 19 #include <lib/psci/psci.h> 20 #include <plat/common/platform.h> 21 22 #include <platform_def.h> 23 24 static uintptr_t stm32_sec_entrypoint; 25 static uint32_t cntfrq_core0; 26 27 /******************************************************************************* 28 * STM32MP1 handler called when a CPU is about to enter standby. 29 * call by core 1 to enter in wfi 30 ******************************************************************************/ 31 static void stm32_cpu_standby(plat_local_state_t cpu_state) 32 { 33 uint32_t interrupt = GIC_SPURIOUS_INTERRUPT; 34 35 assert(cpu_state == ARM_LOCAL_STATE_RET); 36 37 /* 38 * Enter standby state 39 * dsb is good practice before using wfi to enter low power states 40 */ 41 isb(); 42 dsb(); 43 while (interrupt == GIC_SPURIOUS_INTERRUPT) { 44 wfi(); 45 46 /* Acknowledge IT */ 47 interrupt = gicv2_acknowledge_interrupt(); 48 /* If Interrupt == 1022 it will be acknowledged by non secure */ 49 if ((interrupt != PENDING_G1_INTID) && 50 (interrupt != GIC_SPURIOUS_INTERRUPT)) { 51 gicv2_end_of_interrupt(interrupt); 52 } 53 } 54 } 55 56 /******************************************************************************* 57 * STM32MP1 handler called when a power domain is about to be turned on. The 58 * mpidr determines the CPU to be turned on. 59 * call by core 0 to activate core 1 60 ******************************************************************************/ 61 static int stm32_pwr_domain_on(u_register_t mpidr) 62 { 63 unsigned long current_cpu_mpidr = read_mpidr_el1(); 64 uintptr_t bkpr_core1_addr = 65 tamp_bkpr(BOOT_API_CORE1_BRANCH_ADDRESS_TAMP_BCK_REG_IDX); 66 uintptr_t bkpr_core1_magic = 67 tamp_bkpr(BOOT_API_CORE1_MAGIC_NUMBER_TAMP_BCK_REG_IDX); 68 69 if (mpidr == current_cpu_mpidr) { 70 return PSCI_E_INVALID_PARAMS; 71 } 72 73 /* Only one valid entry point */ 74 if (stm32_sec_entrypoint != (uintptr_t)&sp_min_warm_entrypoint) { 75 return PSCI_E_INVALID_ADDRESS; 76 } 77 78 clk_enable(RTCAPB); 79 80 cntfrq_core0 = read_cntfrq_el0(); 81 82 /* Write entrypoint in backup RAM register */ 83 mmio_write_32(bkpr_core1_addr, stm32_sec_entrypoint); 84 85 /* Write magic number in backup register */ 86 mmio_write_32(bkpr_core1_magic, BOOT_API_A7_CORE1_MAGIC_NUMBER); 87 88 clk_disable(RTCAPB); 89 90 /* Generate an IT to core 1 */ 91 gicv2_raise_sgi(ARM_IRQ_SEC_SGI_0, false, STM32MP_SECONDARY_CPU); 92 93 return PSCI_E_SUCCESS; 94 } 95 96 /******************************************************************************* 97 * STM32MP1 handler called when a power domain is about to be turned off. The 98 * target_state encodes the power state that each level should transition to. 99 ******************************************************************************/ 100 static void stm32_pwr_domain_off(const psci_power_state_t *target_state) 101 { 102 /* Nothing to do */ 103 } 104 105 /******************************************************************************* 106 * STM32MP1 handler called when a power domain is about to be suspended. The 107 * target_state encodes the power state that each level should transition to. 108 ******************************************************************************/ 109 static void stm32_pwr_domain_suspend(const psci_power_state_t *target_state) 110 { 111 /* Nothing to do, power domain is not disabled */ 112 } 113 114 /******************************************************************************* 115 * STM32MP1 handler called when a power domain has just been powered on after 116 * being turned off earlier. The target_state encodes the low power state that 117 * each level has woken up from. 118 * call by core 1 just after wake up 119 ******************************************************************************/ 120 static void stm32_pwr_domain_on_finish(const psci_power_state_t *target_state) 121 { 122 stm32mp_gic_pcpu_init(); 123 124 write_cntfrq_el0(cntfrq_core0); 125 } 126 127 /******************************************************************************* 128 * STM32MP1 handler called when a power domain has just been powered on after 129 * having been suspended earlier. The target_state encodes the low power state 130 * that each level has woken up from. 131 ******************************************************************************/ 132 static void stm32_pwr_domain_suspend_finish(const psci_power_state_t 133 *target_state) 134 { 135 /* Nothing to do, power domain is not disabled */ 136 } 137 138 static void __dead2 stm32_pwr_domain_pwr_down_wfi(const psci_power_state_t 139 *target_state) 140 { 141 ERROR("stm32mpu1 Power Down WFI: operation not handled.\n"); 142 panic(); 143 } 144 145 static void __dead2 stm32_system_off(void) 146 { 147 ERROR("stm32mpu1 System Off: operation not handled.\n"); 148 panic(); 149 } 150 151 static void __dead2 stm32_system_reset(void) 152 { 153 stm32mp_system_reset(); 154 } 155 156 static int stm32_validate_power_state(unsigned int power_state, 157 psci_power_state_t *req_state) 158 { 159 if (psci_get_pstate_type(power_state) != 0U) { 160 return PSCI_E_INVALID_PARAMS; 161 } 162 163 if (psci_get_pstate_pwrlvl(power_state) != 0U) { 164 return PSCI_E_INVALID_PARAMS; 165 } 166 167 if (psci_get_pstate_id(power_state) != 0U) { 168 return PSCI_E_INVALID_PARAMS; 169 } 170 171 req_state->pwr_domain_state[0] = ARM_LOCAL_STATE_RET; 172 req_state->pwr_domain_state[1] = ARM_LOCAL_STATE_RUN; 173 174 return PSCI_E_SUCCESS; 175 } 176 177 static int stm32_validate_ns_entrypoint(uintptr_t entrypoint) 178 { 179 /* The non-secure entry point must be in DDR */ 180 if (entrypoint < STM32MP_DDR_BASE) { 181 return PSCI_E_INVALID_ADDRESS; 182 } 183 184 return PSCI_E_SUCCESS; 185 } 186 187 static int stm32_node_hw_state(u_register_t target_cpu, 188 unsigned int power_level) 189 { 190 /* 191 * The format of 'power_level' is implementation-defined, but 0 must 192 * mean a CPU. Only allow level 0. 193 */ 194 if (power_level != MPIDR_AFFLVL0) { 195 return PSCI_E_INVALID_PARAMS; 196 } 197 198 /* 199 * From psci view the CPU 0 is always ON, 200 * CPU 1 can be SUSPEND or RUNNING. 201 * Therefore do not manage POWER OFF state and always return HW_ON. 202 */ 203 204 return (int)HW_ON; 205 } 206 207 /******************************************************************************* 208 * Export the platform handlers. The ARM Standard platform layer will take care 209 * of registering the handlers with PSCI. 210 ******************************************************************************/ 211 static const plat_psci_ops_t stm32_psci_ops = { 212 .cpu_standby = stm32_cpu_standby, 213 .pwr_domain_on = stm32_pwr_domain_on, 214 .pwr_domain_off = stm32_pwr_domain_off, 215 .pwr_domain_suspend = stm32_pwr_domain_suspend, 216 .pwr_domain_on_finish = stm32_pwr_domain_on_finish, 217 .pwr_domain_suspend_finish = stm32_pwr_domain_suspend_finish, 218 .pwr_domain_pwr_down = stm32_pwr_domain_pwr_down_wfi, 219 .system_off = stm32_system_off, 220 .system_reset = stm32_system_reset, 221 .validate_power_state = stm32_validate_power_state, 222 .validate_ns_entrypoint = stm32_validate_ns_entrypoint, 223 .get_node_hw_state = stm32_node_hw_state 224 }; 225 226 /******************************************************************************* 227 * Export the platform specific power ops. 228 ******************************************************************************/ 229 int plat_setup_psci_ops(uintptr_t sec_entrypoint, 230 const plat_psci_ops_t **psci_ops) 231 { 232 stm32_sec_entrypoint = sec_entrypoint; 233 *psci_ops = &stm32_psci_ops; 234 235 return 0; 236 } 237