1/* 2 * Copyright (c) 2014-2025, Arm Limited and Contributors. All rights reserved. 3 * 4 * SPDX-License-Identifier: BSD-3-Clause 5 */ 6#include <arch.h> 7#include <asm_macros.S> 8#include <common/bl_common.h> 9#include <common/debug.h> 10#include <cortex_a53.h> 11#include <cpu_macros.S> 12#include <plat_macros.S> 13#include <lib/cpus/errata.h> 14 15cpu_reset_prologue cortex_a53 16 17 /* --------------------------------------------- 18 * Disable L1 data cache and unified L2 cache 19 * --------------------------------------------- 20 */ 21func cortex_a53_disable_dcache 22 sysreg_bit_clear sctlr_el3, SCTLR_C_BIT 23 isb 24 ret 25endfunc cortex_a53_disable_dcache 26 27 /* --------------------------------------------- 28 * Disable intra-cluster coherency 29 * --------------------------------------------- 30 */ 31func cortex_a53_disable_smp 32 sysreg_bit_clear CORTEX_A53_ECTLR_EL1, CORTEX_A53_ECTLR_SMP_BIT 33 isb 34 dsb sy 35 ret 36endfunc cortex_a53_disable_smp 37 38/* Due to the nature of the errata it is applied unconditionally when chosen */ 39check_erratum_ls cortex_a53, ERRATUM(819472), CPU_REV(0, 1) 40/* erratum workaround is interleaved with generic code */ 41add_erratum_entry cortex_a53, ERRATUM(819472), ERRATUM_ALWAYS_CHOSEN 42 43/* Due to the nature of the errata it is applied unconditionally when chosen */ 44check_erratum_ls cortex_a53, ERRATUM(824069), CPU_REV(0, 2) 45/* erratum workaround is interleaved with generic code */ 46add_erratum_entry cortex_a53, ERRATUM(824069), ERRATUM_ALWAYS_CHOSEN 47 48workaround_reset_start cortex_a53, ERRATUM(826319), ERRATA_A53_826319 49 mrs x1, CORTEX_A53_L2ACTLR_EL1 50 bic x1, x1, #CORTEX_A53_L2ACTLR_ENABLE_UNIQUECLEAN 51 orr x1, x1, #CORTEX_A53_L2ACTLR_DISABLE_CLEAN_PUSH 52 msr CORTEX_A53_L2ACTLR_EL1, x1 53workaround_reset_end cortex_a53, ERRATUM(826319) 54 55check_erratum_ls cortex_a53, ERRATUM(826319), CPU_REV(0, 2) 56 57/* Due to the nature of the errata it is applied unconditionally when chosen */ 58check_erratum_ls cortex_a53, ERRATUM(827319), CPU_REV(0, 2) 59/* erratum workaround is interleaved with generic code */ 60add_erratum_entry cortex_a53, ERRATUM(827319), ERRATUM_ALWAYS_CHOSEN 61 62check_erratum_custom_start cortex_a53, ERRATUM(835769) 63 cmp x0, CPU_REV(0, 4) 64 b.hi errata_not_applies 65 /* 66 * Fix potentially available for revisions r0p2, r0p3 and r0p4. 67 * If r0p2, r0p3 or r0p4; check for fix in REVIDR, else exit. 68 */ 69 cmp x0, #0x01 70 mov x0, #ERRATA_APPLIES 71 b.ls exit_check_errata_835769 72 /* Load REVIDR. */ 73 mrs x1, revidr_el1 74 /* If REVIDR[7] is set (fix exists) set ERRATA_NOT_APPLIES, else exit. */ 75 tbz x1, #7, exit_check_errata_835769 76errata_not_applies: 77 mov x0, #ERRATA_NOT_APPLIES 78exit_check_errata_835769: 79 ret 80check_erratum_custom_end cortex_a53, ERRATUM(835769) 81 82/* workaround at build time */ 83add_erratum_entry cortex_a53, ERRATUM(835769), ERRATA_A53_835769 84 85 /* 86 * Disable the cache non-temporal hint. 87 * 88 * This ignores the Transient allocation hint in the MAIR and treats 89 * allocations the same as non-transient allocation types. As a result, 90 * the LDNP and STNP instructions in AArch64 behave the same as the 91 * equivalent LDP and STP instructions. 92 */ 93workaround_reset_start cortex_a53, ERRATUM(836870), ERRATA_A53_836870 | A53_DISABLE_NON_TEMPORAL_HINT 94 sysreg_bit_set CORTEX_A53_CPUACTLR_EL1, CORTEX_A53_CPUACTLR_EL1_DTAH 95workaround_reset_end cortex_a53, ERRATUM(836870) 96 97check_erratum_ls cortex_a53, ERRATUM(836870), CPU_REV(0, 3) 98 99check_erratum_custom_start cortex_a53, ERRATUM(843419) 100 mov x1, #ERRATA_APPLIES 101 mov x2, #ERRATA_NOT_APPLIES 102 cmp x0, CPU_REV(0, 4) 103 csel x0, x1, x2, ls 104 /* 105 * Fix potentially available for revision r0p4. 106 * If r0p4 check for fix in REVIDR, else exit. 107 */ 108 b.ne exit_check_errata_843419 109 /* Load REVIDR. */ 110 mrs x3, revidr_el1 111 /* If REVIDR[8] is set (fix exists) set ERRATA_NOT_APPLIES, else exit. */ 112 tbz x3, #8, exit_check_errata_843419 113 mov x0, x2 114exit_check_errata_843419: 115 ret 116check_erratum_custom_end cortex_a53, ERRATUM(843419) 117 118/* workaround at build time */ 119add_erratum_entry cortex_a53, ERRATUM(843419), ERRATA_A53_843419 120 121 /* 122 * Earlier revisions of the core are affected as well, but don't 123 * have the chicken bit in the CPUACTLR register. It is expected that 124 * the rich OS takes care of that, especially as the workaround is 125 * shared with other erratas in those revisions of the CPU. 126 */ 127workaround_reset_start cortex_a53, ERRATUM(855873), ERRATA_A53_855873 128 sysreg_bit_set CORTEX_A53_CPUACTLR_EL1, CORTEX_A53_CPUACTLR_EL1_ENDCCASCI 129workaround_reset_end cortex_a53, ERRATUM(855873) 130 131check_erratum_hs cortex_a53, ERRATUM(855873), CPU_REV(0, 3) 132 133check_erratum_chosen cortex_a53, ERRATUM(1530924), ERRATA_A53_1530924 134 135/* erratum has no workaround in the cpu. Generic code must take care */ 136add_erratum_entry cortex_a53, ERRATUM(1530924), ERRATA_A53_1530924 137 138cpu_reset_func_start cortex_a53 139 /* Enable the SMP bit. */ 140 sysreg_bit_set CORTEX_A53_ECTLR_EL1, CORTEX_A53_ECTLR_SMP_BIT 141cpu_reset_func_end cortex_a53 142 143func cortex_a53_core_pwr_dwn 144 mov x18, x30 145 146 /* --------------------------------------------- 147 * Turn off caches. 148 * --------------------------------------------- 149 */ 150 bl cortex_a53_disable_dcache 151 152 /* --------------------------------------------- 153 * Flush L1 caches. 154 * --------------------------------------------- 155 */ 156 mov x0, #DCCISW 157 bl dcsw_op_level1 158 159 /* --------------------------------------------- 160 * Come out of intra cluster coherency 161 * --------------------------------------------- 162 */ 163 mov x30, x18 164 b cortex_a53_disable_smp 165endfunc cortex_a53_core_pwr_dwn 166 167func cortex_a53_cluster_pwr_dwn 168 mov x18, x30 169 170 /* --------------------------------------------- 171 * Turn off caches. 172 * --------------------------------------------- 173 */ 174 bl cortex_a53_disable_dcache 175 176 /* --------------------------------------------- 177 * Flush L1 caches. 178 * --------------------------------------------- 179 */ 180 mov x0, #DCCISW 181 bl dcsw_op_level1 182 183 /* --------------------------------------------- 184 * Disable the optional ACP. 185 * --------------------------------------------- 186 */ 187 bl plat_disable_acp 188 189 /* --------------------------------------------- 190 * Flush L2 caches. 191 * --------------------------------------------- 192 */ 193 mov x0, #DCCISW 194 bl dcsw_op_level2 195 196 /* --------------------------------------------- 197 * Come out of intra cluster coherency 198 * --------------------------------------------- 199 */ 200 mov x30, x18 201 b cortex_a53_disable_smp 202endfunc cortex_a53_cluster_pwr_dwn 203 204 /* --------------------------------------------- 205 * This function provides cortex_a53 specific 206 * register information for crash reporting. 207 * It needs to return with x6 pointing to 208 * a list of register names in ascii and 209 * x8 - x15 having values of registers to be 210 * reported. 211 * --------------------------------------------- 212 */ 213.section .rodata.cortex_a53_regs, "aS" 214cortex_a53_regs: /* The ascii list of register names to be reported */ 215 .asciz "cpuectlr_el1", "cpumerrsr_el1", "l2merrsr_el1", \ 216 "cpuactlr_el1", "" 217 218func cortex_a53_cpu_reg_dump 219 adr x6, cortex_a53_regs 220 mrs x8, CORTEX_A53_ECTLR_EL1 221 mrs x9, CORTEX_A53_MERRSR_EL1 222 mrs x10, CORTEX_A53_L2MERRSR_EL1 223 mrs x11, CORTEX_A53_CPUACTLR_EL1 224 ret 225endfunc cortex_a53_cpu_reg_dump 226 227declare_cpu_ops cortex_a53, CORTEX_A53_MIDR, \ 228 cortex_a53_reset_func, \ 229 cortex_a53_core_pwr_dwn, \ 230 cortex_a53_cluster_pwr_dwn 231