1/* 2 * Copyright (c) 2023-2025, Arm Limited. All rights reserved. 3 * 4 * SPDX-License-Identifier: BSD-3-Clause 5 */ 6 7#include <arch.h> 8#include <asm_macros.S> 9#include <common/bl_common.h> 10#include <cortex_a725.h> 11#include <cpu_macros.S> 12#include <plat_macros.S> 13 14/* Hardware handled coherency */ 15#if HW_ASSISTED_COHERENCY == 0 16#error "Cortex-A725 must be compiled with HW_ASSISTED_COHERENCY enabled" 17#endif 18 19/* 64-bit only core */ 20#if CTX_INCLUDE_AARCH32_REGS == 1 21#error "Cortex-A725 supports only AArch64. Compile with CTX_INCLUDE_AARCH32_REGS=0" 22#endif 23 24cpu_reset_prologue cortex_a725 25 26.global check_erratum_cortex_a725_3699564 27 28add_erratum_entry cortex_a725, ERRATUM(3699564), ERRATA_A725_3699564 29 30check_erratum_ls cortex_a725, ERRATUM(3699564), CPU_REV(0, 1) 31 32cpu_reset_func_start cortex_a725 33 /* Disable speculative loads */ 34 msr SSBS, xzr 35 enable_mpmm 36cpu_reset_func_end cortex_a725 37 38 /* ---------------------------------------------------- 39 * HW will do the cache maintenance while powering down 40 * ---------------------------------------------------- 41 */ 42func cortex_a725_core_pwr_dwn 43 /* --------------------------------------------------- 44 * Enable CPU power down bit in power control register 45 * --------------------------------------------------- 46 */ 47 sysreg_bit_set CORTEX_A725_CPUPWRCTLR_EL1, CORTEX_A725_CPUPWRCTLR_EL1_CORE_PWRDN_BIT 48 isb 49 ret 50endfunc cortex_a725_core_pwr_dwn 51 52 /* --------------------------------------------- 53 * This function provides Cortex-A725 specific 54 * register information for crash reporting. 55 * It needs to return with x6 pointing to 56 * a list of register names in ascii and 57 * x8 - x15 having values of registers to be 58 * reported. 59 * --------------------------------------------- 60 */ 61.section .rodata.cortex_a725_regs, "aS" 62cortex_a725_regs: /* The ascii list of register names to be reported */ 63 .asciz "cpuectlr_el1", "" 64 65func cortex_a725_cpu_reg_dump 66 adr x6, cortex_a725_regs 67 mrs x8, CORTEX_A725_CPUECTLR_EL1 68 ret 69endfunc cortex_a725_cpu_reg_dump 70 71declare_cpu_ops cortex_a725, CORTEX_A725_MIDR, \ 72 cortex_a725_reset_func, \ 73 cortex_a725_core_pwr_dwn 74