1 /* 2 * Copyright (c) 2013-2025, Arm Limited and Contributors. All rights reserved. 3 * Copyright (c) 2022, NVIDIA Corporation. All rights reserved. 4 * 5 * SPDX-License-Identifier: BSD-3-Clause 6 */ 7 8 #include <assert.h> 9 #include <stdbool.h> 10 #include <string.h> 11 12 #include <platform_def.h> 13 14 #include <arch.h> 15 #include <arch_helpers.h> 16 #include <arch_features.h> 17 #include <bl31/interrupt_mgmt.h> 18 #include <common/bl_common.h> 19 #include <common/debug.h> 20 #include <context.h> 21 #include <drivers/arm/gicv3.h> 22 #include <lib/cpus/cpu_ops.h> 23 #include <lib/cpus/errata.h> 24 #include <lib/el3_runtime/context_mgmt.h> 25 #include <lib/el3_runtime/cpu_data.h> 26 #include <lib/el3_runtime/pubsub_events.h> 27 #include <lib/extensions/amu.h> 28 #include <lib/extensions/brbe.h> 29 #include <lib/extensions/debug_v8p9.h> 30 #include <lib/extensions/fgt2.h> 31 #include <lib/extensions/fpmr.h> 32 #include <lib/extensions/mpam.h> 33 #include <lib/extensions/pauth.h> 34 #include <lib/extensions/pmuv3.h> 35 #include <lib/extensions/sme.h> 36 #include <lib/extensions/spe.h> 37 #include <lib/extensions/sve.h> 38 #include <lib/extensions/sysreg128.h> 39 #include <lib/extensions/sys_reg_trace.h> 40 #include <lib/extensions/tcr2.h> 41 #include <lib/extensions/trbe.h> 42 #include <lib/extensions/trf.h> 43 #include <lib/utils.h> 44 45 #if ENABLE_FEAT_TWED 46 /* Make sure delay value fits within the range(0-15) */ 47 CASSERT(((TWED_DELAY & ~SCR_TWEDEL_MASK) == 0U), assert_twed_delay_value_check); 48 #endif /* ENABLE_FEAT_TWED */ 49 50 per_world_context_t per_world_context[CPU_DATA_CONTEXT_NUM]; 51 static bool has_secure_perworld_init; 52 53 static void manage_extensions_nonsecure(cpu_context_t *ctx); 54 static void manage_extensions_secure(cpu_context_t *ctx); 55 static void manage_extensions_secure_per_world(void); 56 57 #if ((IMAGE_BL1) || (IMAGE_BL31 && (!CTX_INCLUDE_EL2_REGS))) 58 static void setup_el1_context(cpu_context_t *ctx, const struct entry_point_info *ep) 59 { 60 u_register_t sctlr_elx, actlr_elx; 61 62 /* 63 * Initialise SCTLR_EL1 to the reset value corresponding to the target 64 * execution state setting all fields rather than relying on the hw. 65 * Some fields have architecturally UNKNOWN reset values and these are 66 * set to zero. 67 * 68 * SCTLR.EE: Endianness is taken from the entrypoint attributes. 69 * 70 * SCTLR.M, SCTLR.C and SCTLR.I: These fields must be zero (as 71 * required by PSCI specification) 72 */ 73 sctlr_elx = (EP_GET_EE(ep->h.attr) != 0U) ? SCTLR_EE_BIT : 0UL; 74 if (GET_RW(ep->spsr) == MODE_RW_64) { 75 sctlr_elx |= SCTLR_EL1_RES1; 76 } else { 77 /* 78 * If the target execution state is AArch32 then the following 79 * fields need to be set. 80 * 81 * SCTRL_EL1.nTWE: Set to one so that EL0 execution of WFE 82 * instructions are not trapped to EL1. 83 * 84 * SCTLR_EL1.nTWI: Set to one so that EL0 execution of WFI 85 * instructions are not trapped to EL1. 86 * 87 * SCTLR_EL1.CP15BEN: Set to one to enable EL0 execution of the 88 * CP15DMB, CP15DSB, and CP15ISB instructions. 89 */ 90 sctlr_elx |= SCTLR_AARCH32_EL1_RES1 | SCTLR_CP15BEN_BIT 91 | SCTLR_NTWI_BIT | SCTLR_NTWE_BIT; 92 } 93 94 /* 95 * If workaround of errata 764081 for Cortex-A75 is used then set 96 * SCTLR_EL1.IESB to enable Implicit Error Synchronization Barrier. 97 */ 98 if (errata_a75_764081_applies()) { 99 sctlr_elx |= SCTLR_IESB_BIT; 100 } 101 102 /* Store the initialised SCTLR_EL1 value in the cpu_context */ 103 write_ctx_sctlr_el1_reg_errata(ctx, sctlr_elx); 104 105 /* 106 * Base the context ACTLR_EL1 on the current value, as it is 107 * implementation defined. The context restore process will write 108 * the value from the context to the actual register and can cause 109 * problems for processor cores that don't expect certain bits to 110 * be zero. 111 */ 112 actlr_elx = read_actlr_el1(); 113 write_el1_ctx_common(get_el1_sysregs_ctx(ctx), actlr_el1, actlr_elx); 114 } 115 #endif /* (IMAGE_BL1) || (IMAGE_BL31 && (!CTX_INCLUDE_EL2_REGS)) */ 116 117 /****************************************************************************** 118 * This function performs initializations that are specific to SECURE state 119 * and updates the cpu context specified by 'ctx'. 120 *****************************************************************************/ 121 static void setup_secure_context(cpu_context_t *ctx, const struct entry_point_info *ep) 122 { 123 u_register_t scr_el3; 124 el3_state_t *state; 125 126 state = get_el3state_ctx(ctx); 127 scr_el3 = read_ctx_reg(state, CTX_SCR_EL3); 128 129 #if defined(IMAGE_BL31) && !defined(SPD_spmd) 130 /* 131 * SCR_EL3.IRQ, SCR_EL3.FIQ: Enable the physical FIQ and IRQ routing as 132 * indicated by the interrupt routing model for BL31. 133 */ 134 scr_el3 |= get_scr_el3_from_routing_model(SECURE); 135 #endif 136 137 /* Allow access to Allocation Tags when FEAT_MTE2 is implemented and enabled. */ 138 if (is_feat_mte2_supported()) { 139 scr_el3 |= SCR_ATA_BIT; 140 } 141 142 write_ctx_reg(state, CTX_SCR_EL3, scr_el3); 143 144 /* 145 * Initialize EL1 context registers unless SPMC is running 146 * at S-EL2. 147 */ 148 #if (!SPMD_SPM_AT_SEL2) 149 setup_el1_context(ctx, ep); 150 #endif 151 152 manage_extensions_secure(ctx); 153 154 /** 155 * manage_extensions_secure_per_world api has to be executed once, 156 * as the registers getting initialised, maintain constant value across 157 * all the cpus for the secure world. 158 * Henceforth, this check ensures that the registers are initialised once 159 * and avoids re-initialization from multiple cores. 160 */ 161 if (!has_secure_perworld_init) { 162 manage_extensions_secure_per_world(); 163 } 164 } 165 166 #if ENABLE_RME 167 /****************************************************************************** 168 * This function performs initializations that are specific to REALM state 169 * and updates the cpu context specified by 'ctx'. 170 *****************************************************************************/ 171 static void setup_realm_context(cpu_context_t *ctx, const struct entry_point_info *ep) 172 { 173 u_register_t scr_el3; 174 el3_state_t *state; 175 176 state = get_el3state_ctx(ctx); 177 scr_el3 = read_ctx_reg(state, CTX_SCR_EL3); 178 179 scr_el3 |= SCR_NS_BIT | SCR_NSE_BIT; 180 181 /* CSV2 version 2 and above */ 182 if (is_feat_csv2_2_supported()) { 183 /* Enable access to the SCXTNUM_ELx registers. */ 184 scr_el3 |= SCR_EnSCXT_BIT; 185 } 186 187 if (is_feat_sctlr2_supported()) { 188 /* Set the SCTLR2En bit in SCR_EL3 to enable access to 189 * SCTLR2_ELx registers. 190 */ 191 scr_el3 |= SCR_SCTLR2En_BIT; 192 } 193 194 write_ctx_reg(state, CTX_SCR_EL3, scr_el3); 195 196 if (is_feat_fgt2_supported()) { 197 fgt2_enable(ctx); 198 } 199 200 if (is_feat_debugv8p9_supported()) { 201 debugv8p9_extended_bp_wp_enable(ctx); 202 } 203 204 if (is_feat_brbe_supported()) { 205 brbe_enable(ctx); 206 } 207 208 } 209 #endif /* ENABLE_RME */ 210 211 /****************************************************************************** 212 * This function performs initializations that are specific to NON-SECURE state 213 * and updates the cpu context specified by 'ctx'. 214 *****************************************************************************/ 215 static void setup_ns_context(cpu_context_t *ctx, const struct entry_point_info *ep) 216 { 217 u_register_t scr_el3; 218 el3_state_t *state; 219 220 state = get_el3state_ctx(ctx); 221 scr_el3 = read_ctx_reg(state, CTX_SCR_EL3); 222 223 /* SCR_NS: Set the NS bit */ 224 scr_el3 |= SCR_NS_BIT; 225 226 /* Allow access to Allocation Tags when FEAT_MTE2 is implemented and enabled. */ 227 if (is_feat_mte2_supported()) { 228 scr_el3 |= SCR_ATA_BIT; 229 } 230 231 /* 232 * Pointer Authentication feature, if present, is always enabled by 233 * default for Non secure lower exception levels. We do not have an 234 * explicit flag to set it. To prevent the leakage between the worlds 235 * during world switch, we enable it only for the non-secure world. 236 * 237 * CTX_INCLUDE_PAUTH_REGS flag, is explicitly used to enable for lower 238 * exception levels of secure and realm worlds. 239 * 240 * If the Secure/realm world wants to use pointer authentication, 241 * CTX_INCLUDE_PAUTH_REGS must be explicitly set to 1, in which case 242 * it will be enabled globally for all the contexts. 243 * 244 * SCR_EL3.API: Set to one to not trap any PAuth instructions at ELs 245 * other than EL3 246 * 247 * SCR_EL3.APK: Set to one to not trap any PAuth key values at ELs other 248 * than EL3 249 */ 250 if (!is_ctx_pauth_supported()) { 251 scr_el3 |= SCR_API_BIT | SCR_APK_BIT; 252 } 253 254 #if HANDLE_EA_EL3_FIRST_NS 255 /* SCR_EL3.EA: Route External Abort and SError Interrupt to EL3. */ 256 scr_el3 |= SCR_EA_BIT; 257 #endif 258 259 #if RAS_TRAP_NS_ERR_REC_ACCESS 260 /* 261 * SCR_EL3.TERR: Trap Error record accesses. Accesses to the RAS ERR 262 * and RAS ERX registers from EL1 and EL2(from any security state) 263 * are trapped to EL3. 264 * Set here to trap only for NS EL1/EL2 265 */ 266 scr_el3 |= SCR_TERR_BIT; 267 #endif 268 269 /* CSV2 version 2 and above */ 270 if (is_feat_csv2_2_supported()) { 271 /* Enable access to the SCXTNUM_ELx registers. */ 272 scr_el3 |= SCR_EnSCXT_BIT; 273 } 274 275 #ifdef IMAGE_BL31 276 /* 277 * SCR_EL3.IRQ, SCR_EL3.FIQ: Enable the physical FIQ and IRQ routing as 278 * indicated by the interrupt routing model for BL31. 279 */ 280 scr_el3 |= get_scr_el3_from_routing_model(NON_SECURE); 281 #endif 282 283 if (is_feat_the_supported()) { 284 /* Set the RCWMASKEn bit in SCR_EL3 to enable access to 285 * RCWMASK_EL1 and RCWSMASK_EL1 registers. 286 */ 287 scr_el3 |= SCR_RCWMASKEn_BIT; 288 } 289 290 if (is_feat_sctlr2_supported()) { 291 /* Set the SCTLR2En bit in SCR_EL3 to enable access to 292 * SCTLR2_ELx registers. 293 */ 294 scr_el3 |= SCR_SCTLR2En_BIT; 295 } 296 297 if (is_feat_d128_supported()) { 298 /* Set the D128En bit in SCR_EL3 to enable access to 128-bit 299 * versions of TTBR0_EL1, TTBR1_EL1, RCWMASK_EL1, RCWSMASK_EL1, 300 * PAR_EL1 and TTBR1_EL2, TTBR0_EL2 and VTTBR_EL2 registers. 301 */ 302 scr_el3 |= SCR_D128En_BIT; 303 } 304 305 if (is_feat_fpmr_supported()) { 306 /* Set the EnFPM bit in SCR_EL3 to enable access to FPMR 307 * register. 308 */ 309 scr_el3 |= SCR_EnFPM_BIT; 310 } 311 312 write_ctx_reg(state, CTX_SCR_EL3, scr_el3); 313 314 /* Initialize EL2 context registers */ 315 #if (CTX_INCLUDE_EL2_REGS && IMAGE_BL31) 316 317 /* 318 * Initialize SCTLR_EL2 context register with reset value. 319 */ 320 write_el2_ctx_common(get_el2_sysregs_ctx(ctx), sctlr_el2, SCTLR_EL2_RES1); 321 322 if (is_feat_hcx_supported()) { 323 /* 324 * Initialize register HCRX_EL2 with its init value. 325 * As the value of HCRX_EL2 is UNKNOWN on reset, there is a 326 * chance that this can lead to unexpected behavior in lower 327 * ELs that have not been updated since the introduction of 328 * this feature if not properly initialized, especially when 329 * it comes to those bits that enable/disable traps. 330 */ 331 write_el2_ctx_hcx(get_el2_sysregs_ctx(ctx), hcrx_el2, 332 HCRX_EL2_INIT_VAL); 333 } 334 335 if (is_feat_fgt_supported()) { 336 /* 337 * Initialize HFG*_EL2 registers with a default value so legacy 338 * systems unaware of FEAT_FGT do not get trapped due to their lack 339 * of initialization for this feature. 340 */ 341 write_el2_ctx_fgt(get_el2_sysregs_ctx(ctx), hfgitr_el2, 342 HFGITR_EL2_INIT_VAL); 343 write_el2_ctx_fgt(get_el2_sysregs_ctx(ctx), hfgrtr_el2, 344 HFGRTR_EL2_INIT_VAL); 345 write_el2_ctx_fgt(get_el2_sysregs_ctx(ctx), hfgwtr_el2, 346 HFGWTR_EL2_INIT_VAL); 347 } 348 #else 349 /* Initialize EL1 context registers */ 350 setup_el1_context(ctx, ep); 351 #endif /* (CTX_INCLUDE_EL2_REGS && IMAGE_BL31) */ 352 353 manage_extensions_nonsecure(ctx); 354 } 355 356 /******************************************************************************* 357 * The following function performs initialization of the cpu_context 'ctx' 358 * for first use that is common to all security states, and sets the 359 * initial entrypoint state as specified by the entry_point_info structure. 360 * 361 * The EE and ST attributes are used to configure the endianness and secure 362 * timer availability for the new execution context. 363 ******************************************************************************/ 364 static void setup_context_common(cpu_context_t *ctx, const entry_point_info_t *ep) 365 { 366 u_register_t scr_el3; 367 u_register_t mdcr_el3; 368 el3_state_t *state; 369 gp_regs_t *gp_regs; 370 371 state = get_el3state_ctx(ctx); 372 373 /* Clear any residual register values from the context */ 374 zeromem(ctx, sizeof(*ctx)); 375 376 /* 377 * The lower-EL context is zeroed so that no stale values leak to a world. 378 * It is assumed that an all-zero lower-EL context is good enough for it 379 * to boot correctly. However, there are very few registers where this 380 * is not true and some values need to be recreated. 381 */ 382 #if (CTX_INCLUDE_EL2_REGS && IMAGE_BL31) 383 el2_sysregs_t *el2_ctx = get_el2_sysregs_ctx(ctx); 384 385 /* 386 * These bits are set in the gicv3 driver. Losing them (especially the 387 * SRE bit) is problematic for all worlds. Henceforth recreate them. 388 */ 389 u_register_t icc_sre_el2_val = ICC_SRE_DIB_BIT | ICC_SRE_DFB_BIT | 390 ICC_SRE_EN_BIT | ICC_SRE_SRE_BIT; 391 write_el2_ctx_common(el2_ctx, icc_sre_el2, icc_sre_el2_val); 392 393 /* 394 * The actlr_el2 register can be initialized in platform's reset handler 395 * and it may contain access control bits (e.g. CLUSTERPMUEN bit). 396 */ 397 write_el2_ctx_common(el2_ctx, actlr_el2, read_actlr_el2()); 398 #endif /* (CTX_INCLUDE_EL2_REGS && IMAGE_BL31) */ 399 400 /* Start with a clean SCR_EL3 copy as all relevant values are set */ 401 scr_el3 = SCR_RESET_VAL; 402 403 /* 404 * SCR_EL3.TWE: Set to zero so that execution of WFE instructions at 405 * EL2, EL1 and EL0 are not trapped to EL3. 406 * 407 * SCR_EL3.TWI: Set to zero so that execution of WFI instructions at 408 * EL2, EL1 and EL0 are not trapped to EL3. 409 * 410 * SCR_EL3.SMD: Set to zero to enable SMC calls at EL1 and above, from 411 * both Security states and both Execution states. 412 * 413 * SCR_EL3.SIF: Set to one to disable secure instruction execution from 414 * Non-secure memory. 415 */ 416 scr_el3 &= ~(SCR_TWE_BIT | SCR_TWI_BIT | SCR_SMD_BIT); 417 418 scr_el3 |= SCR_SIF_BIT; 419 420 /* 421 * SCR_EL3.RW: Set the execution state, AArch32 or AArch64, for next 422 * Exception level as specified by SPSR. 423 */ 424 if (GET_RW(ep->spsr) == MODE_RW_64) { 425 scr_el3 |= SCR_RW_BIT; 426 } 427 428 /* 429 * SCR_EL3.ST: Traps Secure EL1 accesses to the Counter-timer Physical 430 * Secure timer registers to EL3, from AArch64 state only, if specified 431 * by the entrypoint attributes. If SEL2 is present and enabled, the ST 432 * bit always behaves as 1 (i.e. secure physical timer register access 433 * is not trapped) 434 */ 435 if (EP_GET_ST(ep->h.attr) != 0U) { 436 scr_el3 |= SCR_ST_BIT; 437 } 438 439 /* 440 * If FEAT_HCX is enabled, enable access to HCRX_EL2 by setting 441 * SCR_EL3.HXEn. 442 */ 443 if (is_feat_hcx_supported()) { 444 scr_el3 |= SCR_HXEn_BIT; 445 } 446 447 /* 448 * If FEAT_LS64_ACCDATA is enabled, enable access to ACCDATA_EL1 by 449 * setting SCR_EL3.ADEn and allow the ST64BV0 instruction by setting 450 * SCR_EL3.EnAS0. 451 */ 452 if (is_feat_ls64_accdata_supported()) { 453 scr_el3 |= SCR_ADEn_BIT | SCR_EnAS0_BIT; 454 } 455 456 /* 457 * If FEAT_RNG_TRAP is enabled, all reads of the RNDR and RNDRRS 458 * registers are trapped to EL3. 459 */ 460 if (is_feat_rng_trap_supported()) { 461 scr_el3 |= SCR_TRNDR_BIT; 462 } 463 464 #if FAULT_INJECTION_SUPPORT 465 /* Enable fault injection from lower ELs */ 466 scr_el3 |= SCR_FIEN_BIT; 467 #endif 468 469 /* 470 * Enable Pointer Authentication globally for all the worlds. 471 * 472 * SCR_EL3.API: Set to one to not trap any PAuth instructions at ELs 473 * other than EL3 474 * 475 * SCR_EL3.APK: Set to one to not trap any PAuth key values at ELs other 476 * than EL3 477 */ 478 if (is_ctx_pauth_supported()) { 479 scr_el3 |= SCR_API_BIT | SCR_APK_BIT; 480 } 481 482 /* 483 * SCR_EL3.TCR2EN: Enable access to TCR2_ELx for AArch64 if present. 484 */ 485 if (is_feat_tcr2_supported() && (GET_RW(ep->spsr) == MODE_RW_64)) { 486 scr_el3 |= SCR_TCR2EN_BIT; 487 } 488 489 /* 490 * SCR_EL3.PIEN: Enable permission indirection and overlay 491 * registers for AArch64 if present. 492 */ 493 if (is_feat_sxpie_supported() || is_feat_sxpoe_supported()) { 494 scr_el3 |= SCR_PIEN_BIT; 495 } 496 497 /* 498 * SCR_EL3.GCSEn: Enable GCS registers for AArch64 if present. 499 */ 500 if ((is_feat_gcs_supported()) && (GET_RW(ep->spsr) == MODE_RW_64)) { 501 scr_el3 |= SCR_GCSEn_BIT; 502 } 503 504 /* 505 * SCR_EL3.HCE: Enable HVC instructions if next execution state is 506 * AArch64 and next EL is EL2, or if next execution state is AArch32 and 507 * next mode is Hyp. 508 * SCR_EL3.FGTEn: Enable Fine Grained Virtualization Traps under the 509 * same conditions as HVC instructions and when the processor supports 510 * ARMv8.6-FGT. 511 * SCR_EL3.ECVEn: Enable Enhanced Counter Virtualization (ECV) 512 * CNTPOFF_EL2 register under the same conditions as HVC instructions 513 * and when the processor supports ECV. 514 */ 515 if (((GET_RW(ep->spsr) == MODE_RW_64) && (GET_EL(ep->spsr) == MODE_EL2)) 516 || ((GET_RW(ep->spsr) != MODE_RW_64) 517 && (GET_M32(ep->spsr) == MODE32_hyp))) { 518 scr_el3 |= SCR_HCE_BIT; 519 520 if (is_feat_fgt_supported()) { 521 scr_el3 |= SCR_FGTEN_BIT; 522 } 523 524 if (is_feat_ecv_supported()) { 525 scr_el3 |= SCR_ECVEN_BIT; 526 } 527 } 528 529 /* Enable WFE trap delay in SCR_EL3 if supported and configured */ 530 if (is_feat_twed_supported()) { 531 /* Set delay in SCR_EL3 */ 532 scr_el3 &= ~(SCR_TWEDEL_MASK << SCR_TWEDEL_SHIFT); 533 scr_el3 |= ((TWED_DELAY & SCR_TWEDEL_MASK) 534 << SCR_TWEDEL_SHIFT); 535 536 /* Enable WFE delay */ 537 scr_el3 |= SCR_TWEDEn_BIT; 538 } 539 540 #if IMAGE_BL31 && defined(SPD_spmd) && SPMD_SPM_AT_SEL2 541 /* Enable S-EL2 if FEAT_SEL2 is implemented for all the contexts. */ 542 if (is_feat_sel2_supported()) { 543 scr_el3 |= SCR_EEL2_BIT; 544 } 545 #endif /* (IMAGE_BL31 && defined(SPD_spmd) && SPMD_SPM_AT_SEL2) */ 546 547 if (is_feat_mec_supported()) { 548 scr_el3 |= SCR_MECEn_BIT; 549 } 550 551 /* 552 * Populate EL3 state so that we've the right context 553 * before doing ERET 554 */ 555 write_ctx_reg(state, CTX_SCR_EL3, scr_el3); 556 write_ctx_reg(state, CTX_ELR_EL3, ep->pc); 557 write_ctx_reg(state, CTX_SPSR_EL3, ep->spsr); 558 559 /* Start with a clean MDCR_EL3 copy as all relevant values are set */ 560 mdcr_el3 = MDCR_EL3_RESET_VAL; 561 562 /* --------------------------------------------------------------------- 563 * Initialise MDCR_EL3, setting all fields rather than relying on hw. 564 * Some fields are architecturally UNKNOWN on reset. 565 * 566 * MDCR_EL3.SDD: Set to one to disable AArch64 Secure self-hosted debug. 567 * Debug exceptions, other than Breakpoint Instruction exceptions, are 568 * disabled from all ELs in Secure state. 569 * 570 * MDCR_EL3.SPD32: Set to 0b10 to disable AArch32 Secure self-hosted 571 * privileged debug from S-EL1. 572 * 573 * MDCR_EL3.TDOSA: Set to zero so that EL2 and EL2 System register 574 * access to the powerdown debug registers do not trap to EL3. 575 * 576 * MDCR_EL3.TDA: Set to zero to allow EL0, EL1 and EL2 access to the 577 * debug registers, other than those registers that are controlled by 578 * MDCR_EL3.TDOSA. 579 */ 580 mdcr_el3 |= ((MDCR_SDD_BIT | MDCR_SPD32(MDCR_SPD32_DISABLE)) 581 & ~(MDCR_TDA_BIT | MDCR_TDOSA_BIT)) ; 582 write_ctx_reg(state, CTX_MDCR_EL3, mdcr_el3); 583 584 #if IMAGE_BL31 585 /* Enable FEAT_TRF for Non-Secure and prohibit for Secure state. */ 586 if (is_feat_trf_supported()) { 587 trf_enable(ctx); 588 } 589 590 pmuv3_enable(ctx); 591 #endif /* IMAGE_BL31 */ 592 593 /* 594 * Store the X0-X7 value from the entrypoint into the context 595 * Use memcpy as we are in control of the layout of the structures 596 */ 597 gp_regs = get_gpregs_ctx(ctx); 598 memcpy(gp_regs, (void *)&ep->args, sizeof(aapcs64_params_t)); 599 } 600 601 /******************************************************************************* 602 * Context management library initialization routine. This library is used by 603 * runtime services to share pointers to 'cpu_context' structures for secure 604 * non-secure and realm states. Management of the structures and their associated 605 * memory is not done by the context management library e.g. the PSCI service 606 * manages the cpu context used for entry from and exit to the non-secure state. 607 * The Secure payload dispatcher service manages the context(s) corresponding to 608 * the secure state. It also uses this library to get access to the non-secure 609 * state cpu context pointers. 610 * Lastly, this library provides the API to make SP_EL3 point to the cpu context 611 * which will be used for programming an entry into a lower EL. The same context 612 * will be used to save state upon exception entry from that EL. 613 ******************************************************************************/ 614 void __init cm_init(void) 615 { 616 /* 617 * The context management library has only global data to initialize, but 618 * that will be done when the BSS is zeroed out. 619 */ 620 } 621 622 /******************************************************************************* 623 * This is the high-level function used to initialize the cpu_context 'ctx' for 624 * first use. It performs initializations that are common to all security states 625 * and initializations specific to the security state specified in 'ep' 626 ******************************************************************************/ 627 void cm_setup_context(cpu_context_t *ctx, const entry_point_info_t *ep) 628 { 629 unsigned int security_state; 630 631 assert(ctx != NULL); 632 633 /* 634 * Perform initializations that are common 635 * to all security states 636 */ 637 setup_context_common(ctx, ep); 638 639 security_state = GET_SECURITY_STATE(ep->h.attr); 640 641 /* Perform security state specific initializations */ 642 switch (security_state) { 643 case SECURE: 644 setup_secure_context(ctx, ep); 645 break; 646 #if ENABLE_RME 647 case REALM: 648 setup_realm_context(ctx, ep); 649 break; 650 #endif 651 case NON_SECURE: 652 setup_ns_context(ctx, ep); 653 break; 654 default: 655 ERROR("Invalid security state\n"); 656 panic(); 657 break; 658 } 659 } 660 661 /******************************************************************************* 662 * Enable architecture extensions for EL3 execution. This function only updates 663 * registers in-place which are expected to either never change or be 664 * overwritten by el3_exit. Expects the core_pos of the current core as argument. 665 ******************************************************************************/ 666 #if IMAGE_BL31 667 void cm_manage_extensions_el3(unsigned int my_idx) 668 { 669 if (is_feat_sve_supported()) { 670 sve_init_el3(); 671 } 672 673 if (is_feat_amu_supported()) { 674 amu_init_el3(my_idx); 675 } 676 677 if (is_feat_sme_supported()) { 678 sme_init_el3(); 679 } 680 681 pmuv3_init_el3(); 682 } 683 #endif /* IMAGE_BL31 */ 684 685 /****************************************************************************** 686 * Function to initialise the registers with the RESET values in the context 687 * memory, which are maintained per world. 688 ******************************************************************************/ 689 #if IMAGE_BL31 690 void cm_el3_arch_init_per_world(per_world_context_t *per_world_ctx) 691 { 692 /* 693 * Initialise CPTR_EL3, setting all fields rather than relying on hw. 694 * 695 * CPTR_EL3.TFP: Set to zero so that accesses to the V- or Z- registers 696 * by Advanced SIMD, floating-point or SVE instructions (if 697 * implemented) do not trap to EL3. 698 * 699 * CPTR_EL3.TCPAC: Set to zero so that accesses to CPACR_EL1, 700 * CPTR_EL2,CPACR, or HCPTR do not trap to EL3. 701 */ 702 uint64_t cptr_el3 = CPTR_EL3_RESET_VAL & ~(TCPAC_BIT | TFP_BIT); 703 704 per_world_ctx->ctx_cptr_el3 = cptr_el3; 705 706 /* 707 * Initialize MPAM3_EL3 to its default reset value 708 * 709 * MPAM3_EL3_RESET_VAL sets the MPAM3_EL3.TRAPLOWER bit that forces 710 * all lower ELn MPAM3_EL3 register access to, trap to EL3 711 */ 712 713 per_world_ctx->ctx_mpam3_el3 = MPAM3_EL3_RESET_VAL; 714 } 715 #endif /* IMAGE_BL31 */ 716 717 /******************************************************************************* 718 * Initialise per_world_context for Non-Secure world. 719 * This function enables the architecture extensions, which have same value 720 * across the cores for the non-secure world. 721 ******************************************************************************/ 722 #if IMAGE_BL31 723 void manage_extensions_nonsecure_per_world(void) 724 { 725 cm_el3_arch_init_per_world(&per_world_context[CPU_CONTEXT_NS]); 726 727 if (is_feat_sme_supported()) { 728 sme_enable_per_world(&per_world_context[CPU_CONTEXT_NS]); 729 } 730 731 if (is_feat_sve_supported()) { 732 sve_enable_per_world(&per_world_context[CPU_CONTEXT_NS]); 733 } 734 735 if (is_feat_amu_supported()) { 736 amu_enable_per_world(&per_world_context[CPU_CONTEXT_NS]); 737 } 738 739 if (is_feat_sys_reg_trace_supported()) { 740 sys_reg_trace_enable_per_world(&per_world_context[CPU_CONTEXT_NS]); 741 } 742 743 if (is_feat_mpam_supported()) { 744 mpam_enable_per_world(&per_world_context[CPU_CONTEXT_NS]); 745 } 746 747 if (is_feat_fpmr_supported()) { 748 fpmr_enable_per_world(&per_world_context[CPU_CONTEXT_NS]); 749 } 750 } 751 #endif /* IMAGE_BL31 */ 752 753 /******************************************************************************* 754 * Initialise per_world_context for Secure world. 755 * This function enables the architecture extensions, which have same value 756 * across the cores for the secure world. 757 ******************************************************************************/ 758 static void manage_extensions_secure_per_world(void) 759 { 760 #if IMAGE_BL31 761 cm_el3_arch_init_per_world(&per_world_context[CPU_CONTEXT_SECURE]); 762 763 if (is_feat_sme_supported()) { 764 765 if (ENABLE_SME_FOR_SWD) { 766 /* 767 * Enable SME, SVE, FPU/SIMD in secure context, SPM must ensure 768 * SME, SVE, and FPU/SIMD context properly managed. 769 */ 770 sme_enable_per_world(&per_world_context[CPU_CONTEXT_SECURE]); 771 } else { 772 /* 773 * Disable SME, SVE, FPU/SIMD in secure context so non-secure 774 * world can safely use the associated registers. 775 */ 776 sme_disable_per_world(&per_world_context[CPU_CONTEXT_SECURE]); 777 } 778 } 779 if (is_feat_sve_supported()) { 780 if (ENABLE_SVE_FOR_SWD) { 781 /* 782 * Enable SVE and FPU in secure context, SPM must ensure 783 * that the SVE and FPU register contexts are properly managed. 784 */ 785 sve_enable_per_world(&per_world_context[CPU_CONTEXT_SECURE]); 786 } else { 787 /* 788 * Disable SVE and FPU in secure context so non-secure world 789 * can safely use them. 790 */ 791 sve_disable_per_world(&per_world_context[CPU_CONTEXT_SECURE]); 792 } 793 } 794 795 /* NS can access this but Secure shouldn't */ 796 if (is_feat_sys_reg_trace_supported()) { 797 sys_reg_trace_disable_per_world(&per_world_context[CPU_CONTEXT_SECURE]); 798 } 799 800 has_secure_perworld_init = true; 801 #endif /* IMAGE_BL31 */ 802 } 803 804 /******************************************************************************* 805 * Enable architecture extensions on first entry to Non-secure world. 806 ******************************************************************************/ 807 static void manage_extensions_nonsecure(cpu_context_t *ctx) 808 { 809 #if IMAGE_BL31 810 /* NOTE: registers are not context switched */ 811 if (is_feat_amu_supported()) { 812 amu_enable(ctx); 813 } 814 815 if (is_feat_sme_supported()) { 816 sme_enable(ctx); 817 } 818 819 if (is_feat_fgt2_supported()) { 820 fgt2_enable(ctx); 821 } 822 823 if (is_feat_debugv8p9_supported()) { 824 debugv8p9_extended_bp_wp_enable(ctx); 825 } 826 827 /* 828 * SPE, TRBE, and BRBE have multi-field enables that affect which world 829 * they apply to. Despite this, it is useful to ignore these for 830 * simplicity in determining the feature's per world enablement status. 831 * This is only possible when context is written per-world. Relied on 832 * by SMCCC_ARCH_FEATURE_AVAILABILITY 833 */ 834 if (is_feat_spe_supported()) { 835 spe_enable(ctx); 836 } 837 838 if (is_feat_trbe_supported()) { 839 trbe_enable(ctx); 840 } 841 842 if (is_feat_brbe_supported()) { 843 brbe_enable(ctx); 844 } 845 #endif /* IMAGE_BL31 */ 846 } 847 848 #if INIT_UNUSED_NS_EL2 849 /******************************************************************************* 850 * Enable architecture extensions in-place at EL2 on first entry to Non-secure 851 * world when EL2 is empty and unused. 852 ******************************************************************************/ 853 static void manage_extensions_nonsecure_el2_unused(void) 854 { 855 #if IMAGE_BL31 856 if (is_feat_spe_supported()) { 857 spe_init_el2_unused(); 858 } 859 860 if (is_feat_amu_supported()) { 861 amu_init_el2_unused(); 862 } 863 864 if (is_feat_mpam_supported()) { 865 mpam_init_el2_unused(); 866 } 867 868 if (is_feat_trbe_supported()) { 869 trbe_init_el2_unused(); 870 } 871 872 if (is_feat_sys_reg_trace_supported()) { 873 sys_reg_trace_init_el2_unused(); 874 } 875 876 if (is_feat_trf_supported()) { 877 trf_init_el2_unused(); 878 } 879 880 pmuv3_init_el2_unused(); 881 882 if (is_feat_sve_supported()) { 883 sve_init_el2_unused(); 884 } 885 886 if (is_feat_sme_supported()) { 887 sme_init_el2_unused(); 888 } 889 890 if (is_feat_mops_supported() && is_feat_hcx_supported()) { 891 write_hcrx_el2(read_hcrx_el2() | HCRX_EL2_MSCEn_BIT); 892 } 893 894 if (is_feat_pauth_supported()) { 895 pauth_enable_el2(); 896 } 897 #endif /* IMAGE_BL31 */ 898 } 899 #endif /* INIT_UNUSED_NS_EL2 */ 900 901 /******************************************************************************* 902 * Enable architecture extensions on first entry to Secure world. 903 ******************************************************************************/ 904 static void manage_extensions_secure(cpu_context_t *ctx) 905 { 906 #if IMAGE_BL31 907 if (is_feat_sme_supported()) { 908 if (ENABLE_SME_FOR_SWD) { 909 /* 910 * Enable SME, SVE, FPU/SIMD in secure context, secure manager 911 * must ensure SME, SVE, and FPU/SIMD context properly managed. 912 */ 913 sme_init_el3(); 914 sme_enable(ctx); 915 } else { 916 /* 917 * Disable SME, SVE, FPU/SIMD in secure context so non-secure 918 * world can safely use the associated registers. 919 */ 920 sme_disable(ctx); 921 } 922 } 923 924 /* 925 * SPE and TRBE cannot be fully disabled from EL3 registers alone, only 926 * sysreg access can. In case the EL1 controls leave them active on 927 * context switch, we want the owning security state to be NS so Secure 928 * can't be DOSed. 929 */ 930 if (is_feat_spe_supported()) { 931 spe_disable(ctx); 932 } 933 934 if (is_feat_trbe_supported()) { 935 trbe_disable(ctx); 936 } 937 #endif /* IMAGE_BL31 */ 938 } 939 940 #if !IMAGE_BL1 941 /******************************************************************************* 942 * The following function initializes the cpu_context for a CPU specified by 943 * its `cpu_idx` for first use, and sets the initial entrypoint state as 944 * specified by the entry_point_info structure. 945 ******************************************************************************/ 946 void cm_init_context_by_index(unsigned int cpu_idx, 947 const entry_point_info_t *ep) 948 { 949 cpu_context_t *ctx; 950 ctx = cm_get_context_by_index(cpu_idx, GET_SECURITY_STATE(ep->h.attr)); 951 cm_setup_context(ctx, ep); 952 } 953 #endif /* !IMAGE_BL1 */ 954 955 /******************************************************************************* 956 * The following function initializes the cpu_context for the current CPU 957 * for first use, and sets the initial entrypoint state as specified by the 958 * entry_point_info structure. 959 ******************************************************************************/ 960 void cm_init_my_context(const entry_point_info_t *ep) 961 { 962 cpu_context_t *ctx; 963 ctx = cm_get_context(GET_SECURITY_STATE(ep->h.attr)); 964 cm_setup_context(ctx, ep); 965 } 966 967 /* EL2 present but unused, need to disable safely. SCTLR_EL2 can be ignored */ 968 static void init_nonsecure_el2_unused(cpu_context_t *ctx) 969 { 970 #if INIT_UNUSED_NS_EL2 971 u_register_t hcr_el2 = HCR_RESET_VAL; 972 u_register_t mdcr_el2; 973 u_register_t scr_el3; 974 975 scr_el3 = read_ctx_reg(get_el3state_ctx(ctx), CTX_SCR_EL3); 976 977 /* Set EL2 register width: Set HCR_EL2.RW to match SCR_EL3.RW */ 978 if ((scr_el3 & SCR_RW_BIT) != 0U) { 979 hcr_el2 |= HCR_RW_BIT; 980 } 981 982 write_hcr_el2(hcr_el2); 983 984 /* 985 * Initialise CPTR_EL2 setting all fields rather than relying on the hw. 986 * All fields have architecturally UNKNOWN reset values. 987 */ 988 write_cptr_el2(CPTR_EL2_RESET_VAL); 989 990 /* 991 * Initialise CNTHCTL_EL2. All fields are architecturally UNKNOWN on 992 * reset and are set to zero except for field(s) listed below. 993 * 994 * CNTHCTL_EL2.EL1PTEN: Set to one to disable traps to Hyp mode of 995 * Non-secure EL0 and EL1 accesses to the physical timer registers. 996 * 997 * CNTHCTL_EL2.EL1PCTEN: Set to one to disable traps to Hyp mode of 998 * Non-secure EL0 and EL1 accesses to the physical counter registers. 999 */ 1000 write_cnthctl_el2(CNTHCTL_RESET_VAL | EL1PCEN_BIT | EL1PCTEN_BIT); 1001 1002 /* 1003 * Initialise CNTVOFF_EL2 to zero as it resets to an architecturally 1004 * UNKNOWN value. 1005 */ 1006 write_cntvoff_el2(0); 1007 1008 /* 1009 * Set VPIDR_EL2 and VMPIDR_EL2 to match MIDR_EL1 and MPIDR_EL1 1010 * respectively. 1011 */ 1012 write_vpidr_el2(read_midr_el1()); 1013 write_vmpidr_el2(read_mpidr_el1()); 1014 1015 /* 1016 * Initialise VTTBR_EL2. All fields are architecturally UNKNOWN on reset. 1017 * 1018 * VTTBR_EL2.VMID: Set to zero. Even though EL1&0 stage 2 address 1019 * translation is disabled, cache maintenance operations depend on the 1020 * VMID. 1021 * 1022 * VTTBR_EL2.BADDR: Set to zero as EL1&0 stage 2 address translation is 1023 * disabled. 1024 */ 1025 write_vttbr_el2(VTTBR_RESET_VAL & 1026 ~((VTTBR_VMID_MASK << VTTBR_VMID_SHIFT) | 1027 (VTTBR_BADDR_MASK << VTTBR_BADDR_SHIFT))); 1028 1029 /* 1030 * Initialise MDCR_EL2, setting all fields rather than relying on hw. 1031 * Some fields are architecturally UNKNOWN on reset. 1032 * 1033 * MDCR_EL2.TDRA: Set to zero so that Non-secure EL0 and EL1 System 1034 * register accesses to the Debug ROM registers are not trapped to EL2. 1035 * 1036 * MDCR_EL2.TDOSA: Set to zero so that Non-secure EL1 System register 1037 * accesses to the powerdown debug registers are not trapped to EL2. 1038 * 1039 * MDCR_EL2.TDA: Set to zero so that System register accesses to the 1040 * debug registers do not trap to EL2. 1041 * 1042 * MDCR_EL2.TDE: Set to zero so that debug exceptions are not routed to 1043 * EL2. 1044 */ 1045 mdcr_el2 = MDCR_EL2_RESET_VAL & 1046 ~(MDCR_EL2_TDRA_BIT | MDCR_EL2_TDOSA_BIT | MDCR_EL2_TDA_BIT | 1047 MDCR_EL2_TDE_BIT); 1048 1049 write_mdcr_el2(mdcr_el2); 1050 1051 /* 1052 * Initialise HSTR_EL2. All fields are architecturally UNKNOWN on reset. 1053 * 1054 * HSTR_EL2.T<n>: Set all these fields to zero so that Non-secure EL0 or 1055 * EL1 accesses to System registers do not trap to EL2. 1056 */ 1057 write_hstr_el2(HSTR_EL2_RESET_VAL & ~(HSTR_EL2_T_MASK)); 1058 1059 /* 1060 * Initialise CNTHP_CTL_EL2. All fields are architecturally UNKNOWN on 1061 * reset. 1062 * 1063 * CNTHP_CTL_EL2:ENABLE: Set to zero to disable the EL2 physical timer 1064 * and prevent timer interrupts. 1065 */ 1066 write_cnthp_ctl_el2(CNTHP_CTL_RESET_VAL & ~(CNTHP_CTL_ENABLE_BIT)); 1067 1068 manage_extensions_nonsecure_el2_unused(); 1069 #endif /* INIT_UNUSED_NS_EL2 */ 1070 } 1071 1072 /******************************************************************************* 1073 * Prepare the CPU system registers for first entry into realm, secure, or 1074 * normal world. 1075 * 1076 * If execution is requested to EL2 or hyp mode, SCTLR_EL2 is initialized 1077 * If execution is requested to non-secure EL1 or svc mode, and the CPU supports 1078 * EL2 then EL2 is disabled by configuring all necessary EL2 registers. 1079 * For all entries, the EL1 registers are initialized from the cpu_context 1080 ******************************************************************************/ 1081 void cm_prepare_el3_exit(uint32_t security_state) 1082 { 1083 u_register_t sctlr_el2, scr_el3; 1084 cpu_context_t *ctx = cm_get_context(security_state); 1085 1086 assert(ctx != NULL); 1087 1088 if (security_state == NON_SECURE) { 1089 uint64_t el2_implemented = el_implemented(2); 1090 1091 scr_el3 = read_ctx_reg(get_el3state_ctx(ctx), 1092 CTX_SCR_EL3); 1093 1094 if (el2_implemented != EL_IMPL_NONE) { 1095 1096 /* 1097 * If context is not being used for EL2, initialize 1098 * HCRX_EL2 with its init value here. 1099 */ 1100 if (is_feat_hcx_supported()) { 1101 write_hcrx_el2(HCRX_EL2_INIT_VAL); 1102 } 1103 1104 /* 1105 * Initialize Fine-grained trap registers introduced 1106 * by FEAT_FGT so all traps are initially disabled when 1107 * switching to EL2 or a lower EL, preventing undesired 1108 * behavior. 1109 */ 1110 if (is_feat_fgt_supported()) { 1111 /* 1112 * Initialize HFG*_EL2 registers with a default 1113 * value so legacy systems unaware of FEAT_FGT 1114 * do not get trapped due to their lack of 1115 * initialization for this feature. 1116 */ 1117 write_hfgitr_el2(HFGITR_EL2_INIT_VAL); 1118 write_hfgrtr_el2(HFGRTR_EL2_INIT_VAL); 1119 write_hfgwtr_el2(HFGWTR_EL2_INIT_VAL); 1120 } 1121 1122 /* Condition to ensure EL2 is being used. */ 1123 if ((scr_el3 & SCR_HCE_BIT) != 0U) { 1124 /* Initialize SCTLR_EL2 register with reset value. */ 1125 sctlr_el2 = SCTLR_EL2_RES1; 1126 1127 /* 1128 * If workaround of errata 764081 for Cortex-A75 1129 * is used then set SCTLR_EL2.IESB to enable 1130 * Implicit Error Synchronization Barrier. 1131 */ 1132 if (errata_a75_764081_applies()) { 1133 sctlr_el2 |= SCTLR_IESB_BIT; 1134 } 1135 1136 write_sctlr_el2(sctlr_el2); 1137 } else { 1138 /* 1139 * (scr_el3 & SCR_HCE_BIT==0) 1140 * EL2 implemented but unused. 1141 */ 1142 init_nonsecure_el2_unused(ctx); 1143 } 1144 } 1145 } 1146 #if (!CTX_INCLUDE_EL2_REGS) 1147 /* Restore EL1 system registers, only when CTX_INCLUDE_EL2_REGS=0 */ 1148 cm_el1_sysregs_context_restore(security_state); 1149 #endif 1150 cm_set_next_eret_context(security_state); 1151 } 1152 1153 #if (CTX_INCLUDE_EL2_REGS && IMAGE_BL31) 1154 1155 static void el2_sysregs_context_save_fgt(el2_sysregs_t *ctx) 1156 { 1157 write_el2_ctx_fgt(ctx, hdfgrtr_el2, read_hdfgrtr_el2()); 1158 if (is_feat_amu_supported()) { 1159 write_el2_ctx_fgt(ctx, hafgrtr_el2, read_hafgrtr_el2()); 1160 } 1161 write_el2_ctx_fgt(ctx, hdfgwtr_el2, read_hdfgwtr_el2()); 1162 write_el2_ctx_fgt(ctx, hfgitr_el2, read_hfgitr_el2()); 1163 write_el2_ctx_fgt(ctx, hfgrtr_el2, read_hfgrtr_el2()); 1164 write_el2_ctx_fgt(ctx, hfgwtr_el2, read_hfgwtr_el2()); 1165 } 1166 1167 static void el2_sysregs_context_restore_fgt(el2_sysregs_t *ctx) 1168 { 1169 write_hdfgrtr_el2(read_el2_ctx_fgt(ctx, hdfgrtr_el2)); 1170 if (is_feat_amu_supported()) { 1171 write_hafgrtr_el2(read_el2_ctx_fgt(ctx, hafgrtr_el2)); 1172 } 1173 write_hdfgwtr_el2(read_el2_ctx_fgt(ctx, hdfgwtr_el2)); 1174 write_hfgitr_el2(read_el2_ctx_fgt(ctx, hfgitr_el2)); 1175 write_hfgrtr_el2(read_el2_ctx_fgt(ctx, hfgrtr_el2)); 1176 write_hfgwtr_el2(read_el2_ctx_fgt(ctx, hfgwtr_el2)); 1177 } 1178 1179 static void el2_sysregs_context_save_fgt2(el2_sysregs_t *ctx) 1180 { 1181 write_el2_ctx_fgt2(ctx, hdfgrtr2_el2, read_hdfgrtr2_el2()); 1182 write_el2_ctx_fgt2(ctx, hdfgwtr2_el2, read_hdfgwtr2_el2()); 1183 write_el2_ctx_fgt2(ctx, hfgitr2_el2, read_hfgitr2_el2()); 1184 write_el2_ctx_fgt2(ctx, hfgrtr2_el2, read_hfgrtr2_el2()); 1185 write_el2_ctx_fgt2(ctx, hfgwtr2_el2, read_hfgwtr2_el2()); 1186 } 1187 1188 static void el2_sysregs_context_restore_fgt2(el2_sysregs_t *ctx) 1189 { 1190 write_hdfgrtr2_el2(read_el2_ctx_fgt2(ctx, hdfgrtr2_el2)); 1191 write_hdfgwtr2_el2(read_el2_ctx_fgt2(ctx, hdfgwtr2_el2)); 1192 write_hfgitr2_el2(read_el2_ctx_fgt2(ctx, hfgitr2_el2)); 1193 write_hfgrtr2_el2(read_el2_ctx_fgt2(ctx, hfgrtr2_el2)); 1194 write_hfgwtr2_el2(read_el2_ctx_fgt2(ctx, hfgwtr2_el2)); 1195 } 1196 1197 static void el2_sysregs_context_save_mpam(el2_sysregs_t *ctx) 1198 { 1199 u_register_t mpam_idr = read_mpamidr_el1(); 1200 1201 write_el2_ctx_mpam(ctx, mpam2_el2, read_mpam2_el2()); 1202 1203 /* 1204 * The context registers that we intend to save would be part of the 1205 * PE's system register frame only if MPAMIDR_EL1.HAS_HCR == 1. 1206 */ 1207 if ((mpam_idr & MPAMIDR_HAS_HCR_BIT) == 0U) { 1208 return; 1209 } 1210 1211 /* 1212 * MPAMHCR_EL2, MPAMVPMV_EL2 and MPAMVPM0_EL2 are always present if 1213 * MPAMIDR_HAS_HCR_BIT == 1. 1214 */ 1215 write_el2_ctx_mpam(ctx, mpamhcr_el2, read_mpamhcr_el2()); 1216 write_el2_ctx_mpam(ctx, mpamvpm0_el2, read_mpamvpm0_el2()); 1217 write_el2_ctx_mpam(ctx, mpamvpmv_el2, read_mpamvpmv_el2()); 1218 1219 /* 1220 * The number of MPAMVPM registers is implementation defined, their 1221 * number is stored in the MPAMIDR_EL1 register. 1222 */ 1223 switch ((mpam_idr >> MPAMIDR_EL1_VPMR_MAX_SHIFT) & MPAMIDR_EL1_VPMR_MAX_MASK) { 1224 case 7: 1225 write_el2_ctx_mpam(ctx, mpamvpm7_el2, read_mpamvpm7_el2()); 1226 __fallthrough; 1227 case 6: 1228 write_el2_ctx_mpam(ctx, mpamvpm6_el2, read_mpamvpm6_el2()); 1229 __fallthrough; 1230 case 5: 1231 write_el2_ctx_mpam(ctx, mpamvpm5_el2, read_mpamvpm5_el2()); 1232 __fallthrough; 1233 case 4: 1234 write_el2_ctx_mpam(ctx, mpamvpm4_el2, read_mpamvpm4_el2()); 1235 __fallthrough; 1236 case 3: 1237 write_el2_ctx_mpam(ctx, mpamvpm3_el2, read_mpamvpm3_el2()); 1238 __fallthrough; 1239 case 2: 1240 write_el2_ctx_mpam(ctx, mpamvpm2_el2, read_mpamvpm2_el2()); 1241 __fallthrough; 1242 case 1: 1243 write_el2_ctx_mpam(ctx, mpamvpm1_el2, read_mpamvpm1_el2()); 1244 break; 1245 } 1246 } 1247 1248 static void el2_sysregs_context_restore_mpam(el2_sysregs_t *ctx) 1249 { 1250 u_register_t mpam_idr = read_mpamidr_el1(); 1251 1252 write_mpam2_el2(read_el2_ctx_mpam(ctx, mpam2_el2)); 1253 1254 if ((mpam_idr & MPAMIDR_HAS_HCR_BIT) == 0U) { 1255 return; 1256 } 1257 1258 write_mpamhcr_el2(read_el2_ctx_mpam(ctx, mpamhcr_el2)); 1259 write_mpamvpm0_el2(read_el2_ctx_mpam(ctx, mpamvpm0_el2)); 1260 write_mpamvpmv_el2(read_el2_ctx_mpam(ctx, mpamvpmv_el2)); 1261 1262 switch ((mpam_idr >> MPAMIDR_EL1_VPMR_MAX_SHIFT) & MPAMIDR_EL1_VPMR_MAX_MASK) { 1263 case 7: 1264 write_mpamvpm7_el2(read_el2_ctx_mpam(ctx, mpamvpm7_el2)); 1265 __fallthrough; 1266 case 6: 1267 write_mpamvpm6_el2(read_el2_ctx_mpam(ctx, mpamvpm6_el2)); 1268 __fallthrough; 1269 case 5: 1270 write_mpamvpm5_el2(read_el2_ctx_mpam(ctx, mpamvpm5_el2)); 1271 __fallthrough; 1272 case 4: 1273 write_mpamvpm4_el2(read_el2_ctx_mpam(ctx, mpamvpm4_el2)); 1274 __fallthrough; 1275 case 3: 1276 write_mpamvpm3_el2(read_el2_ctx_mpam(ctx, mpamvpm3_el2)); 1277 __fallthrough; 1278 case 2: 1279 write_mpamvpm2_el2(read_el2_ctx_mpam(ctx, mpamvpm2_el2)); 1280 __fallthrough; 1281 case 1: 1282 write_mpamvpm1_el2(read_el2_ctx_mpam(ctx, mpamvpm1_el2)); 1283 break; 1284 } 1285 } 1286 1287 /* --------------------------------------------------------------------------- 1288 * The following registers are not added: 1289 * ICH_AP0R<n>_EL2 1290 * ICH_AP1R<n>_EL2 1291 * ICH_LR<n>_EL2 1292 * 1293 * NOTE: For a system with S-EL2 present but not enabled, accessing 1294 * ICC_SRE_EL2 is undefined from EL3. To workaround this change the 1295 * SCR_EL3.NS = 1 before accessing this register. 1296 * --------------------------------------------------------------------------- 1297 */ 1298 static void el2_sysregs_context_save_gic(el2_sysregs_t *ctx, uint32_t security_state) 1299 { 1300 u_register_t scr_el3 = read_scr_el3(); 1301 1302 #if defined(SPD_spmd) && SPMD_SPM_AT_SEL2 1303 write_el2_ctx_common(ctx, icc_sre_el2, read_icc_sre_el2()); 1304 #else 1305 write_scr_el3(scr_el3 | SCR_NS_BIT); 1306 isb(); 1307 1308 write_el2_ctx_common(ctx, icc_sre_el2, read_icc_sre_el2()); 1309 1310 write_scr_el3(scr_el3); 1311 isb(); 1312 #endif 1313 write_el2_ctx_common(ctx, ich_hcr_el2, read_ich_hcr_el2()); 1314 1315 if (errata_ich_vmcr_el2_applies()) { 1316 if (security_state == SECURE) { 1317 write_scr_el3(scr_el3 & ~SCR_NS_BIT); 1318 } else { 1319 write_scr_el3(scr_el3 | SCR_NS_BIT); 1320 } 1321 isb(); 1322 } 1323 1324 write_el2_ctx_common(ctx, ich_vmcr_el2, read_ich_vmcr_el2()); 1325 1326 if (errata_ich_vmcr_el2_applies()) { 1327 write_scr_el3(scr_el3); 1328 isb(); 1329 } 1330 } 1331 1332 static void el2_sysregs_context_restore_gic(el2_sysregs_t *ctx, uint32_t security_state) 1333 { 1334 u_register_t scr_el3 = read_scr_el3(); 1335 1336 #if defined(SPD_spmd) && SPMD_SPM_AT_SEL2 1337 write_icc_sre_el2(read_el2_ctx_common(ctx, icc_sre_el2)); 1338 #else 1339 write_scr_el3(scr_el3 | SCR_NS_BIT); 1340 isb(); 1341 1342 write_icc_sre_el2(read_el2_ctx_common(ctx, icc_sre_el2)); 1343 1344 write_scr_el3(scr_el3); 1345 isb(); 1346 #endif 1347 write_ich_hcr_el2(read_el2_ctx_common(ctx, ich_hcr_el2)); 1348 1349 if (errata_ich_vmcr_el2_applies()) { 1350 if (security_state == SECURE) { 1351 write_scr_el3(scr_el3 & ~SCR_NS_BIT); 1352 } else { 1353 write_scr_el3(scr_el3 | SCR_NS_BIT); 1354 } 1355 isb(); 1356 } 1357 1358 write_ich_vmcr_el2(read_el2_ctx_common(ctx, ich_vmcr_el2)); 1359 1360 if (errata_ich_vmcr_el2_applies()) { 1361 write_scr_el3(scr_el3); 1362 isb(); 1363 } 1364 } 1365 1366 /* ----------------------------------------------------- 1367 * The following registers are not added: 1368 * AMEVCNTVOFF0<n>_EL2 1369 * AMEVCNTVOFF1<n>_EL2 1370 * ----------------------------------------------------- 1371 */ 1372 static void el2_sysregs_context_save_common(el2_sysregs_t *ctx) 1373 { 1374 write_el2_ctx_common(ctx, actlr_el2, read_actlr_el2()); 1375 write_el2_ctx_common(ctx, afsr0_el2, read_afsr0_el2()); 1376 write_el2_ctx_common(ctx, afsr1_el2, read_afsr1_el2()); 1377 write_el2_ctx_common(ctx, amair_el2, read_amair_el2()); 1378 write_el2_ctx_common(ctx, cnthctl_el2, read_cnthctl_el2()); 1379 write_el2_ctx_common(ctx, cntvoff_el2, read_cntvoff_el2()); 1380 write_el2_ctx_common(ctx, cptr_el2, read_cptr_el2()); 1381 if (CTX_INCLUDE_AARCH32_REGS) { 1382 write_el2_ctx_common(ctx, dbgvcr32_el2, read_dbgvcr32_el2()); 1383 } 1384 write_el2_ctx_common(ctx, elr_el2, read_elr_el2()); 1385 write_el2_ctx_common(ctx, esr_el2, read_esr_el2()); 1386 write_el2_ctx_common(ctx, far_el2, read_far_el2()); 1387 write_el2_ctx_common(ctx, hacr_el2, read_hacr_el2()); 1388 write_el2_ctx_common(ctx, hcr_el2, read_hcr_el2()); 1389 write_el2_ctx_common(ctx, hpfar_el2, read_hpfar_el2()); 1390 write_el2_ctx_common(ctx, hstr_el2, read_hstr_el2()); 1391 write_el2_ctx_common(ctx, mair_el2, read_mair_el2()); 1392 write_el2_ctx_common(ctx, mdcr_el2, read_mdcr_el2()); 1393 write_el2_ctx_common(ctx, sctlr_el2, read_sctlr_el2()); 1394 write_el2_ctx_common(ctx, spsr_el2, read_spsr_el2()); 1395 write_el2_ctx_common(ctx, sp_el2, read_sp_el2()); 1396 write_el2_ctx_common(ctx, tcr_el2, read_tcr_el2()); 1397 write_el2_ctx_common(ctx, tpidr_el2, read_tpidr_el2()); 1398 write_el2_ctx_common(ctx, vbar_el2, read_vbar_el2()); 1399 write_el2_ctx_common(ctx, vmpidr_el2, read_vmpidr_el2()); 1400 write_el2_ctx_common(ctx, vpidr_el2, read_vpidr_el2()); 1401 write_el2_ctx_common(ctx, vtcr_el2, read_vtcr_el2()); 1402 1403 write_el2_ctx_common_sysreg128(ctx, ttbr0_el2, read_ttbr0_el2()); 1404 write_el2_ctx_common_sysreg128(ctx, vttbr_el2, read_vttbr_el2()); 1405 } 1406 1407 static void el2_sysregs_context_restore_common(el2_sysregs_t *ctx) 1408 { 1409 write_actlr_el2(read_el2_ctx_common(ctx, actlr_el2)); 1410 write_afsr0_el2(read_el2_ctx_common(ctx, afsr0_el2)); 1411 write_afsr1_el2(read_el2_ctx_common(ctx, afsr1_el2)); 1412 write_amair_el2(read_el2_ctx_common(ctx, amair_el2)); 1413 write_cnthctl_el2(read_el2_ctx_common(ctx, cnthctl_el2)); 1414 write_cntvoff_el2(read_el2_ctx_common(ctx, cntvoff_el2)); 1415 write_cptr_el2(read_el2_ctx_common(ctx, cptr_el2)); 1416 if (CTX_INCLUDE_AARCH32_REGS) { 1417 write_dbgvcr32_el2(read_el2_ctx_common(ctx, dbgvcr32_el2)); 1418 } 1419 write_elr_el2(read_el2_ctx_common(ctx, elr_el2)); 1420 write_esr_el2(read_el2_ctx_common(ctx, esr_el2)); 1421 write_far_el2(read_el2_ctx_common(ctx, far_el2)); 1422 write_hacr_el2(read_el2_ctx_common(ctx, hacr_el2)); 1423 write_hcr_el2(read_el2_ctx_common(ctx, hcr_el2)); 1424 write_hpfar_el2(read_el2_ctx_common(ctx, hpfar_el2)); 1425 write_hstr_el2(read_el2_ctx_common(ctx, hstr_el2)); 1426 write_mair_el2(read_el2_ctx_common(ctx, mair_el2)); 1427 write_mdcr_el2(read_el2_ctx_common(ctx, mdcr_el2)); 1428 write_sctlr_el2(read_el2_ctx_common(ctx, sctlr_el2)); 1429 write_spsr_el2(read_el2_ctx_common(ctx, spsr_el2)); 1430 write_sp_el2(read_el2_ctx_common(ctx, sp_el2)); 1431 write_tcr_el2(read_el2_ctx_common(ctx, tcr_el2)); 1432 write_tpidr_el2(read_el2_ctx_common(ctx, tpidr_el2)); 1433 write_ttbr0_el2(read_el2_ctx_common(ctx, ttbr0_el2)); 1434 write_vbar_el2(read_el2_ctx_common(ctx, vbar_el2)); 1435 write_vmpidr_el2(read_el2_ctx_common(ctx, vmpidr_el2)); 1436 write_vpidr_el2(read_el2_ctx_common(ctx, vpidr_el2)); 1437 write_vtcr_el2(read_el2_ctx_common(ctx, vtcr_el2)); 1438 write_vttbr_el2(read_el2_ctx_common(ctx, vttbr_el2)); 1439 } 1440 1441 /******************************************************************************* 1442 * Save EL2 sysreg context 1443 ******************************************************************************/ 1444 void cm_el2_sysregs_context_save(uint32_t security_state) 1445 { 1446 cpu_context_t *ctx; 1447 el2_sysregs_t *el2_sysregs_ctx; 1448 1449 ctx = cm_get_context(security_state); 1450 assert(ctx != NULL); 1451 1452 el2_sysregs_ctx = get_el2_sysregs_ctx(ctx); 1453 1454 el2_sysregs_context_save_common(el2_sysregs_ctx); 1455 el2_sysregs_context_save_gic(el2_sysregs_ctx, security_state); 1456 1457 if (is_feat_mte2_supported()) { 1458 write_el2_ctx_mte2(el2_sysregs_ctx, tfsr_el2, read_tfsr_el2()); 1459 } 1460 1461 if (is_feat_mpam_supported()) { 1462 el2_sysregs_context_save_mpam(el2_sysregs_ctx); 1463 } 1464 1465 if (is_feat_fgt_supported()) { 1466 el2_sysregs_context_save_fgt(el2_sysregs_ctx); 1467 } 1468 1469 if (is_feat_fgt2_supported()) { 1470 el2_sysregs_context_save_fgt2(el2_sysregs_ctx); 1471 } 1472 1473 if (is_feat_ecv_v2_supported()) { 1474 write_el2_ctx_ecv(el2_sysregs_ctx, cntpoff_el2, read_cntpoff_el2()); 1475 } 1476 1477 if (is_feat_vhe_supported()) { 1478 write_el2_ctx_vhe(el2_sysregs_ctx, contextidr_el2, 1479 read_contextidr_el2()); 1480 write_el2_ctx_vhe_sysreg128(el2_sysregs_ctx, ttbr1_el2, read_ttbr1_el2()); 1481 } 1482 1483 if (is_feat_ras_supported()) { 1484 write_el2_ctx_ras(el2_sysregs_ctx, vdisr_el2, read_vdisr_el2()); 1485 write_el2_ctx_ras(el2_sysregs_ctx, vsesr_el2, read_vsesr_el2()); 1486 } 1487 1488 if (is_feat_nv2_supported()) { 1489 write_el2_ctx_neve(el2_sysregs_ctx, vncr_el2, read_vncr_el2()); 1490 } 1491 1492 if (is_feat_trf_supported()) { 1493 write_el2_ctx_trf(el2_sysregs_ctx, trfcr_el2, read_trfcr_el2()); 1494 } 1495 1496 if (is_feat_csv2_2_supported()) { 1497 write_el2_ctx_csv2_2(el2_sysregs_ctx, scxtnum_el2, 1498 read_scxtnum_el2()); 1499 } 1500 1501 if (is_feat_hcx_supported()) { 1502 write_el2_ctx_hcx(el2_sysregs_ctx, hcrx_el2, read_hcrx_el2()); 1503 } 1504 1505 if (is_feat_tcr2_supported()) { 1506 write_el2_ctx_tcr2(el2_sysregs_ctx, tcr2_el2, read_tcr2_el2()); 1507 } 1508 1509 if (is_feat_sxpie_supported()) { 1510 write_el2_ctx_sxpie(el2_sysregs_ctx, pire0_el2, read_pire0_el2()); 1511 write_el2_ctx_sxpie(el2_sysregs_ctx, pir_el2, read_pir_el2()); 1512 } 1513 1514 if (is_feat_sxpoe_supported()) { 1515 write_el2_ctx_sxpoe(el2_sysregs_ctx, por_el2, read_por_el2()); 1516 } 1517 1518 if (is_feat_brbe_supported()) { 1519 write_el2_ctx_brbe(el2_sysregs_ctx, brbcr_el2, read_brbcr_el2()); 1520 } 1521 1522 if (is_feat_s2pie_supported()) { 1523 write_el2_ctx_s2pie(el2_sysregs_ctx, s2pir_el2, read_s2pir_el2()); 1524 } 1525 1526 if (is_feat_gcs_supported()) { 1527 write_el2_ctx_gcs(el2_sysregs_ctx, gcscr_el2, read_gcscr_el2()); 1528 write_el2_ctx_gcs(el2_sysregs_ctx, gcspr_el2, read_gcspr_el2()); 1529 } 1530 1531 if (is_feat_sctlr2_supported()) { 1532 write_el2_ctx_sctlr2(el2_sysregs_ctx, sctlr2_el2, read_sctlr2_el2()); 1533 } 1534 } 1535 1536 /******************************************************************************* 1537 * Restore EL2 sysreg context 1538 ******************************************************************************/ 1539 void cm_el2_sysregs_context_restore(uint32_t security_state) 1540 { 1541 cpu_context_t *ctx; 1542 el2_sysregs_t *el2_sysregs_ctx; 1543 1544 ctx = cm_get_context(security_state); 1545 assert(ctx != NULL); 1546 1547 el2_sysregs_ctx = get_el2_sysregs_ctx(ctx); 1548 1549 el2_sysregs_context_restore_common(el2_sysregs_ctx); 1550 el2_sysregs_context_restore_gic(el2_sysregs_ctx, security_state); 1551 1552 if (is_feat_mte2_supported()) { 1553 write_tfsr_el2(read_el2_ctx_mte2(el2_sysregs_ctx, tfsr_el2)); 1554 } 1555 1556 if (is_feat_mpam_supported()) { 1557 el2_sysregs_context_restore_mpam(el2_sysregs_ctx); 1558 } 1559 1560 if (is_feat_fgt_supported()) { 1561 el2_sysregs_context_restore_fgt(el2_sysregs_ctx); 1562 } 1563 1564 if (is_feat_fgt2_supported()) { 1565 el2_sysregs_context_restore_fgt2(el2_sysregs_ctx); 1566 } 1567 1568 if (is_feat_ecv_v2_supported()) { 1569 write_cntpoff_el2(read_el2_ctx_ecv(el2_sysregs_ctx, cntpoff_el2)); 1570 } 1571 1572 if (is_feat_vhe_supported()) { 1573 write_contextidr_el2(read_el2_ctx_vhe(el2_sysregs_ctx, 1574 contextidr_el2)); 1575 write_ttbr1_el2(read_el2_ctx_vhe(el2_sysregs_ctx, ttbr1_el2)); 1576 } 1577 1578 if (is_feat_ras_supported()) { 1579 write_vdisr_el2(read_el2_ctx_ras(el2_sysregs_ctx, vdisr_el2)); 1580 write_vsesr_el2(read_el2_ctx_ras(el2_sysregs_ctx, vsesr_el2)); 1581 } 1582 1583 if (is_feat_nv2_supported()) { 1584 write_vncr_el2(read_el2_ctx_neve(el2_sysregs_ctx, vncr_el2)); 1585 } 1586 1587 if (is_feat_trf_supported()) { 1588 write_trfcr_el2(read_el2_ctx_trf(el2_sysregs_ctx, trfcr_el2)); 1589 } 1590 1591 if (is_feat_csv2_2_supported()) { 1592 write_scxtnum_el2(read_el2_ctx_csv2_2(el2_sysregs_ctx, 1593 scxtnum_el2)); 1594 } 1595 1596 if (is_feat_hcx_supported()) { 1597 write_hcrx_el2(read_el2_ctx_hcx(el2_sysregs_ctx, hcrx_el2)); 1598 } 1599 1600 if (is_feat_tcr2_supported()) { 1601 write_tcr2_el2(read_el2_ctx_tcr2(el2_sysregs_ctx, tcr2_el2)); 1602 } 1603 1604 if (is_feat_sxpie_supported()) { 1605 write_pire0_el2(read_el2_ctx_sxpie(el2_sysregs_ctx, pire0_el2)); 1606 write_pir_el2(read_el2_ctx_sxpie(el2_sysregs_ctx, pir_el2)); 1607 } 1608 1609 if (is_feat_sxpoe_supported()) { 1610 write_por_el2(read_el2_ctx_sxpoe(el2_sysregs_ctx, por_el2)); 1611 } 1612 1613 if (is_feat_s2pie_supported()) { 1614 write_s2pir_el2(read_el2_ctx_s2pie(el2_sysregs_ctx, s2pir_el2)); 1615 } 1616 1617 if (is_feat_gcs_supported()) { 1618 write_gcscr_el2(read_el2_ctx_gcs(el2_sysregs_ctx, gcscr_el2)); 1619 write_gcspr_el2(read_el2_ctx_gcs(el2_sysregs_ctx, gcspr_el2)); 1620 } 1621 1622 if (is_feat_sctlr2_supported()) { 1623 write_sctlr2_el2(read_el2_ctx_sctlr2(el2_sysregs_ctx, sctlr2_el2)); 1624 } 1625 1626 if (is_feat_brbe_supported()) { 1627 write_brbcr_el2(read_el2_ctx_brbe(el2_sysregs_ctx, brbcr_el2)); 1628 } 1629 } 1630 #endif /* (CTX_INCLUDE_EL2_REGS && IMAGE_BL31) */ 1631 1632 #if IMAGE_BL31 1633 /********************************************************************************* 1634 * This function allows Architecture features asymmetry among cores. 1635 * TF-A assumes that all the cores in the platform has architecture feature parity 1636 * and hence the context is setup on different core (e.g. primary sets up the 1637 * context for secondary cores).This assumption may not be true for systems where 1638 * cores are not conforming to same Arch version or there is CPU Erratum which 1639 * requires certain feature to be be disabled only on a given core. 1640 * 1641 * This function is called on secondary cores to override any disparity in context 1642 * setup by primary, this would be called during warmboot path. 1643 *********************************************************************************/ 1644 void cm_handle_asymmetric_features(void) 1645 { 1646 cpu_context_t *ctx __maybe_unused = cm_get_context(NON_SECURE); 1647 1648 assert(ctx != NULL); 1649 1650 #if ENABLE_SPE_FOR_NS == FEAT_STATE_CHECK_ASYMMETRIC 1651 if (is_feat_spe_supported()) { 1652 spe_enable(ctx); 1653 } else { 1654 spe_disable(ctx); 1655 } 1656 #endif 1657 1658 if (check_if_trbe_disable_affected_core()) { 1659 if (is_feat_trbe_supported()) { 1660 trbe_disable(ctx); 1661 } 1662 } 1663 1664 #if ENABLE_FEAT_TCR2 == FEAT_STATE_CHECK_ASYMMETRIC 1665 el3_state_t *el3_state = get_el3state_ctx(ctx); 1666 u_register_t spsr = read_ctx_reg(el3_state, CTX_SPSR_EL3); 1667 1668 if (is_feat_tcr2_supported() && (GET_RW(spsr) == MODE_RW_64)) { 1669 tcr2_enable(ctx); 1670 } else { 1671 tcr2_disable(ctx); 1672 } 1673 #endif 1674 1675 } 1676 #endif 1677 1678 /******************************************************************************* 1679 * This function is used to exit to Non-secure world. If CTX_INCLUDE_EL2_REGS 1680 * is enabled, it restores EL1 and EL2 sysreg contexts instead of directly 1681 * updating EL1 and EL2 registers. Otherwise, it calls the generic 1682 * cm_prepare_el3_exit function. 1683 ******************************************************************************/ 1684 void cm_prepare_el3_exit_ns(void) 1685 { 1686 #if IMAGE_BL31 1687 /* 1688 * Check and handle Architecture feature asymmetry among cores. 1689 * 1690 * In warmboot path secondary cores context is initialized on core which 1691 * did CPU_ON SMC call, if there is feature asymmetry in these cores handle 1692 * it in this function call. 1693 * For Symmetric cores this is an empty function. 1694 */ 1695 cm_handle_asymmetric_features(); 1696 #endif 1697 1698 #if (CTX_INCLUDE_EL2_REGS && IMAGE_BL31) 1699 #if ENABLE_ASSERTIONS 1700 cpu_context_t *ctx = cm_get_context(NON_SECURE); 1701 assert(ctx != NULL); 1702 1703 /* Assert that EL2 is used. */ 1704 u_register_t scr_el3 = read_ctx_reg(get_el3state_ctx(ctx), CTX_SCR_EL3); 1705 assert(((scr_el3 & SCR_HCE_BIT) != 0UL) && 1706 (el_implemented(2U) != EL_IMPL_NONE)); 1707 #endif /* ENABLE_ASSERTIONS */ 1708 1709 /* Restore EL2 sysreg contexts */ 1710 cm_el2_sysregs_context_restore(NON_SECURE); 1711 cm_set_next_eret_context(NON_SECURE); 1712 #else 1713 cm_prepare_el3_exit(NON_SECURE); 1714 #endif /* (CTX_INCLUDE_EL2_REGS && IMAGE_BL31) */ 1715 } 1716 1717 #if ((IMAGE_BL1) || (IMAGE_BL31 && (!CTX_INCLUDE_EL2_REGS))) 1718 /******************************************************************************* 1719 * The next set of six functions are used by runtime services to save and restore 1720 * EL1 context on the 'cpu_context' structure for the specified security state. 1721 ******************************************************************************/ 1722 static void el1_sysregs_context_save(el1_sysregs_t *ctx) 1723 { 1724 write_el1_ctx_common(ctx, spsr_el1, read_spsr_el1()); 1725 write_el1_ctx_common(ctx, elr_el1, read_elr_el1()); 1726 1727 #if (!ERRATA_SPECULATIVE_AT) 1728 write_el1_ctx_common(ctx, sctlr_el1, read_sctlr_el1()); 1729 write_el1_ctx_common(ctx, tcr_el1, read_tcr_el1()); 1730 #endif /* (!ERRATA_SPECULATIVE_AT) */ 1731 1732 write_el1_ctx_common(ctx, cpacr_el1, read_cpacr_el1()); 1733 write_el1_ctx_common(ctx, csselr_el1, read_csselr_el1()); 1734 write_el1_ctx_common(ctx, sp_el1, read_sp_el1()); 1735 write_el1_ctx_common(ctx, esr_el1, read_esr_el1()); 1736 write_el1_ctx_common(ctx, mair_el1, read_mair_el1()); 1737 write_el1_ctx_common(ctx, amair_el1, read_amair_el1()); 1738 write_el1_ctx_common(ctx, actlr_el1, read_actlr_el1()); 1739 write_el1_ctx_common(ctx, tpidr_el1, read_tpidr_el1()); 1740 write_el1_ctx_common(ctx, tpidr_el0, read_tpidr_el0()); 1741 write_el1_ctx_common(ctx, tpidrro_el0, read_tpidrro_el0()); 1742 write_el1_ctx_common(ctx, far_el1, read_far_el1()); 1743 write_el1_ctx_common(ctx, afsr0_el1, read_afsr0_el1()); 1744 write_el1_ctx_common(ctx, afsr1_el1, read_afsr1_el1()); 1745 write_el1_ctx_common(ctx, contextidr_el1, read_contextidr_el1()); 1746 write_el1_ctx_common(ctx, vbar_el1, read_vbar_el1()); 1747 write_el1_ctx_common(ctx, mdccint_el1, read_mdccint_el1()); 1748 write_el1_ctx_common(ctx, mdscr_el1, read_mdscr_el1()); 1749 1750 write_el1_ctx_common_sysreg128(ctx, par_el1, read_par_el1()); 1751 write_el1_ctx_common_sysreg128(ctx, ttbr0_el1, read_ttbr0_el1()); 1752 write_el1_ctx_common_sysreg128(ctx, ttbr1_el1, read_ttbr1_el1()); 1753 1754 if (CTX_INCLUDE_AARCH32_REGS) { 1755 /* Save Aarch32 registers */ 1756 write_el1_ctx_aarch32(ctx, spsr_abt, read_spsr_abt()); 1757 write_el1_ctx_aarch32(ctx, spsr_und, read_spsr_und()); 1758 write_el1_ctx_aarch32(ctx, spsr_irq, read_spsr_irq()); 1759 write_el1_ctx_aarch32(ctx, spsr_fiq, read_spsr_fiq()); 1760 write_el1_ctx_aarch32(ctx, dacr32_el2, read_dacr32_el2()); 1761 write_el1_ctx_aarch32(ctx, ifsr32_el2, read_ifsr32_el2()); 1762 } 1763 1764 if (NS_TIMER_SWITCH) { 1765 /* Save NS Timer registers */ 1766 write_el1_ctx_arch_timer(ctx, cntp_ctl_el0, read_cntp_ctl_el0()); 1767 write_el1_ctx_arch_timer(ctx, cntp_cval_el0, read_cntp_cval_el0()); 1768 write_el1_ctx_arch_timer(ctx, cntv_ctl_el0, read_cntv_ctl_el0()); 1769 write_el1_ctx_arch_timer(ctx, cntv_cval_el0, read_cntv_cval_el0()); 1770 write_el1_ctx_arch_timer(ctx, cntkctl_el1, read_cntkctl_el1()); 1771 } 1772 1773 if (is_feat_mte2_supported()) { 1774 write_el1_ctx_mte2(ctx, tfsre0_el1, read_tfsre0_el1()); 1775 write_el1_ctx_mte2(ctx, tfsr_el1, read_tfsr_el1()); 1776 write_el1_ctx_mte2(ctx, rgsr_el1, read_rgsr_el1()); 1777 write_el1_ctx_mte2(ctx, gcr_el1, read_gcr_el1()); 1778 } 1779 1780 if (is_feat_ras_supported()) { 1781 write_el1_ctx_ras(ctx, disr_el1, read_disr_el1()); 1782 } 1783 1784 if (is_feat_s1pie_supported()) { 1785 write_el1_ctx_s1pie(ctx, pire0_el1, read_pire0_el1()); 1786 write_el1_ctx_s1pie(ctx, pir_el1, read_pir_el1()); 1787 } 1788 1789 if (is_feat_s1poe_supported()) { 1790 write_el1_ctx_s1poe(ctx, por_el1, read_por_el1()); 1791 } 1792 1793 if (is_feat_s2poe_supported()) { 1794 write_el1_ctx_s2poe(ctx, s2por_el1, read_s2por_el1()); 1795 } 1796 1797 if (is_feat_tcr2_supported()) { 1798 write_el1_ctx_tcr2(ctx, tcr2_el1, read_tcr2_el1()); 1799 } 1800 1801 if (is_feat_trf_supported()) { 1802 write_el1_ctx_trf(ctx, trfcr_el1, read_trfcr_el1()); 1803 } 1804 1805 if (is_feat_csv2_2_supported()) { 1806 write_el1_ctx_csv2_2(ctx, scxtnum_el0, read_scxtnum_el0()); 1807 write_el1_ctx_csv2_2(ctx, scxtnum_el1, read_scxtnum_el1()); 1808 } 1809 1810 if (is_feat_gcs_supported()) { 1811 write_el1_ctx_gcs(ctx, gcscr_el1, read_gcscr_el1()); 1812 write_el1_ctx_gcs(ctx, gcscre0_el1, read_gcscre0_el1()); 1813 write_el1_ctx_gcs(ctx, gcspr_el1, read_gcspr_el1()); 1814 write_el1_ctx_gcs(ctx, gcspr_el0, read_gcspr_el0()); 1815 } 1816 1817 if (is_feat_the_supported()) { 1818 write_el1_ctx_the_sysreg128(ctx, rcwmask_el1, read_rcwmask_el1()); 1819 write_el1_ctx_the_sysreg128(ctx, rcwsmask_el1, read_rcwsmask_el1()); 1820 } 1821 1822 if (is_feat_sctlr2_supported()) { 1823 write_el1_ctx_sctlr2(ctx, sctlr2_el1, read_sctlr2_el1()); 1824 } 1825 1826 if (is_feat_ls64_accdata_supported()) { 1827 write_el1_ctx_ls64(ctx, accdata_el1, read_accdata_el1()); 1828 } 1829 } 1830 1831 static void el1_sysregs_context_restore(el1_sysregs_t *ctx) 1832 { 1833 write_spsr_el1(read_el1_ctx_common(ctx, spsr_el1)); 1834 write_elr_el1(read_el1_ctx_common(ctx, elr_el1)); 1835 1836 #if (!ERRATA_SPECULATIVE_AT) 1837 write_sctlr_el1(read_el1_ctx_common(ctx, sctlr_el1)); 1838 write_tcr_el1(read_el1_ctx_common(ctx, tcr_el1)); 1839 #endif /* (!ERRATA_SPECULATIVE_AT) */ 1840 1841 write_cpacr_el1(read_el1_ctx_common(ctx, cpacr_el1)); 1842 write_csselr_el1(read_el1_ctx_common(ctx, csselr_el1)); 1843 write_sp_el1(read_el1_ctx_common(ctx, sp_el1)); 1844 write_esr_el1(read_el1_ctx_common(ctx, esr_el1)); 1845 write_ttbr0_el1(read_el1_ctx_common(ctx, ttbr0_el1)); 1846 write_ttbr1_el1(read_el1_ctx_common(ctx, ttbr1_el1)); 1847 write_mair_el1(read_el1_ctx_common(ctx, mair_el1)); 1848 write_amair_el1(read_el1_ctx_common(ctx, amair_el1)); 1849 write_actlr_el1(read_el1_ctx_common(ctx, actlr_el1)); 1850 write_tpidr_el1(read_el1_ctx_common(ctx, tpidr_el1)); 1851 write_tpidr_el0(read_el1_ctx_common(ctx, tpidr_el0)); 1852 write_tpidrro_el0(read_el1_ctx_common(ctx, tpidrro_el0)); 1853 write_par_el1(read_el1_ctx_common(ctx, par_el1)); 1854 write_far_el1(read_el1_ctx_common(ctx, far_el1)); 1855 write_afsr0_el1(read_el1_ctx_common(ctx, afsr0_el1)); 1856 write_afsr1_el1(read_el1_ctx_common(ctx, afsr1_el1)); 1857 write_contextidr_el1(read_el1_ctx_common(ctx, contextidr_el1)); 1858 write_vbar_el1(read_el1_ctx_common(ctx, vbar_el1)); 1859 write_mdccint_el1(read_el1_ctx_common(ctx, mdccint_el1)); 1860 write_mdscr_el1(read_el1_ctx_common(ctx, mdscr_el1)); 1861 1862 if (CTX_INCLUDE_AARCH32_REGS) { 1863 /* Restore Aarch32 registers */ 1864 write_spsr_abt(read_el1_ctx_aarch32(ctx, spsr_abt)); 1865 write_spsr_und(read_el1_ctx_aarch32(ctx, spsr_und)); 1866 write_spsr_irq(read_el1_ctx_aarch32(ctx, spsr_irq)); 1867 write_spsr_fiq(read_el1_ctx_aarch32(ctx, spsr_fiq)); 1868 write_dacr32_el2(read_el1_ctx_aarch32(ctx, dacr32_el2)); 1869 write_ifsr32_el2(read_el1_ctx_aarch32(ctx, ifsr32_el2)); 1870 } 1871 1872 if (NS_TIMER_SWITCH) { 1873 /* Restore NS Timer registers */ 1874 write_cntp_ctl_el0(read_el1_ctx_arch_timer(ctx, cntp_ctl_el0)); 1875 write_cntp_cval_el0(read_el1_ctx_arch_timer(ctx, cntp_cval_el0)); 1876 write_cntv_ctl_el0(read_el1_ctx_arch_timer(ctx, cntv_ctl_el0)); 1877 write_cntv_cval_el0(read_el1_ctx_arch_timer(ctx, cntv_cval_el0)); 1878 write_cntkctl_el1(read_el1_ctx_arch_timer(ctx, cntkctl_el1)); 1879 } 1880 1881 if (is_feat_mte2_supported()) { 1882 write_tfsre0_el1(read_el1_ctx_mte2(ctx, tfsre0_el1)); 1883 write_tfsr_el1(read_el1_ctx_mte2(ctx, tfsr_el1)); 1884 write_rgsr_el1(read_el1_ctx_mte2(ctx, rgsr_el1)); 1885 write_gcr_el1(read_el1_ctx_mte2(ctx, gcr_el1)); 1886 } 1887 1888 if (is_feat_ras_supported()) { 1889 write_disr_el1(read_el1_ctx_ras(ctx, disr_el1)); 1890 } 1891 1892 if (is_feat_s1pie_supported()) { 1893 write_pire0_el1(read_el1_ctx_s1pie(ctx, pire0_el1)); 1894 write_pir_el1(read_el1_ctx_s1pie(ctx, pir_el1)); 1895 } 1896 1897 if (is_feat_s1poe_supported()) { 1898 write_por_el1(read_el1_ctx_s1poe(ctx, por_el1)); 1899 } 1900 1901 if (is_feat_s2poe_supported()) { 1902 write_s2por_el1(read_el1_ctx_s2poe(ctx, s2por_el1)); 1903 } 1904 1905 if (is_feat_tcr2_supported()) { 1906 write_tcr2_el1(read_el1_ctx_tcr2(ctx, tcr2_el1)); 1907 } 1908 1909 if (is_feat_trf_supported()) { 1910 write_trfcr_el1(read_el1_ctx_trf(ctx, trfcr_el1)); 1911 } 1912 1913 if (is_feat_csv2_2_supported()) { 1914 write_scxtnum_el0(read_el1_ctx_csv2_2(ctx, scxtnum_el0)); 1915 write_scxtnum_el1(read_el1_ctx_csv2_2(ctx, scxtnum_el1)); 1916 } 1917 1918 if (is_feat_gcs_supported()) { 1919 write_gcscr_el1(read_el1_ctx_gcs(ctx, gcscr_el1)); 1920 write_gcscre0_el1(read_el1_ctx_gcs(ctx, gcscre0_el1)); 1921 write_gcspr_el1(read_el1_ctx_gcs(ctx, gcspr_el1)); 1922 write_gcspr_el0(read_el1_ctx_gcs(ctx, gcspr_el0)); 1923 } 1924 1925 if (is_feat_the_supported()) { 1926 write_rcwmask_el1(read_el1_ctx_the(ctx, rcwmask_el1)); 1927 write_rcwsmask_el1(read_el1_ctx_the(ctx, rcwsmask_el1)); 1928 } 1929 1930 if (is_feat_sctlr2_supported()) { 1931 write_sctlr2_el1(read_el1_ctx_sctlr2(ctx, sctlr2_el1)); 1932 } 1933 1934 if (is_feat_ls64_accdata_supported()) { 1935 write_accdata_el1(read_el1_ctx_ls64(ctx, accdata_el1)); 1936 } 1937 } 1938 1939 /******************************************************************************* 1940 * The next couple of functions are used by runtime services to save and restore 1941 * EL1 context on the 'cpu_context' structure for the specified security state. 1942 ******************************************************************************/ 1943 void cm_el1_sysregs_context_save(uint32_t security_state) 1944 { 1945 cpu_context_t *ctx; 1946 1947 ctx = cm_get_context(security_state); 1948 assert(ctx != NULL); 1949 1950 el1_sysregs_context_save(get_el1_sysregs_ctx(ctx)); 1951 1952 #if IMAGE_BL31 1953 if (security_state == SECURE) { 1954 PUBLISH_EVENT(cm_exited_secure_world); 1955 } else { 1956 PUBLISH_EVENT(cm_exited_normal_world); 1957 } 1958 #endif 1959 } 1960 1961 void cm_el1_sysregs_context_restore(uint32_t security_state) 1962 { 1963 cpu_context_t *ctx; 1964 1965 ctx = cm_get_context(security_state); 1966 assert(ctx != NULL); 1967 1968 el1_sysregs_context_restore(get_el1_sysregs_ctx(ctx)); 1969 1970 #if IMAGE_BL31 1971 if (security_state == SECURE) { 1972 PUBLISH_EVENT(cm_entering_secure_world); 1973 } else { 1974 PUBLISH_EVENT(cm_entering_normal_world); 1975 } 1976 #endif 1977 } 1978 1979 #endif /* ((IMAGE_BL1) || (IMAGE_BL31 && (!CTX_INCLUDE_EL2_REGS))) */ 1980 1981 /******************************************************************************* 1982 * This function populates ELR_EL3 member of 'cpu_context' pertaining to the 1983 * given security state with the given entrypoint 1984 ******************************************************************************/ 1985 void cm_set_elr_el3(uint32_t security_state, uintptr_t entrypoint) 1986 { 1987 cpu_context_t *ctx; 1988 el3_state_t *state; 1989 1990 ctx = cm_get_context(security_state); 1991 assert(ctx != NULL); 1992 1993 /* Populate EL3 state so that ERET jumps to the correct entry */ 1994 state = get_el3state_ctx(ctx); 1995 write_ctx_reg(state, CTX_ELR_EL3, entrypoint); 1996 } 1997 1998 /******************************************************************************* 1999 * This function populates ELR_EL3 and SPSR_EL3 members of 'cpu_context' 2000 * pertaining to the given security state 2001 ******************************************************************************/ 2002 void cm_set_elr_spsr_el3(uint32_t security_state, 2003 uintptr_t entrypoint, uint32_t spsr) 2004 { 2005 cpu_context_t *ctx; 2006 el3_state_t *state; 2007 2008 ctx = cm_get_context(security_state); 2009 assert(ctx != NULL); 2010 2011 /* Populate EL3 state so that ERET jumps to the correct entry */ 2012 state = get_el3state_ctx(ctx); 2013 write_ctx_reg(state, CTX_ELR_EL3, entrypoint); 2014 write_ctx_reg(state, CTX_SPSR_EL3, spsr); 2015 } 2016 2017 /******************************************************************************* 2018 * This function updates a single bit in the SCR_EL3 member of the 'cpu_context' 2019 * pertaining to the given security state using the value and bit position 2020 * specified in the parameters. It preserves all other bits. 2021 ******************************************************************************/ 2022 void cm_write_scr_el3_bit(uint32_t security_state, 2023 uint32_t bit_pos, 2024 uint32_t value) 2025 { 2026 cpu_context_t *ctx; 2027 el3_state_t *state; 2028 u_register_t scr_el3; 2029 2030 ctx = cm_get_context(security_state); 2031 assert(ctx != NULL); 2032 2033 /* Ensure that the bit position is a valid one */ 2034 assert(((1UL << bit_pos) & SCR_VALID_BIT_MASK) != 0U); 2035 2036 /* Ensure that the 'value' is only a bit wide */ 2037 assert(value <= 1U); 2038 2039 /* 2040 * Get the SCR_EL3 value from the cpu context, clear the desired bit 2041 * and set it to its new value. 2042 */ 2043 state = get_el3state_ctx(ctx); 2044 scr_el3 = read_ctx_reg(state, CTX_SCR_EL3); 2045 scr_el3 &= ~(1UL << bit_pos); 2046 scr_el3 |= (u_register_t)value << bit_pos; 2047 write_ctx_reg(state, CTX_SCR_EL3, scr_el3); 2048 } 2049 2050 /******************************************************************************* 2051 * This function retrieves SCR_EL3 member of 'cpu_context' pertaining to the 2052 * given security state. 2053 ******************************************************************************/ 2054 u_register_t cm_get_scr_el3(uint32_t security_state) 2055 { 2056 const cpu_context_t *ctx; 2057 const el3_state_t *state; 2058 2059 ctx = cm_get_context(security_state); 2060 assert(ctx != NULL); 2061 2062 /* Populate EL3 state so that ERET jumps to the correct entry */ 2063 state = get_el3state_ctx(ctx); 2064 return read_ctx_reg(state, CTX_SCR_EL3); 2065 } 2066 2067 /******************************************************************************* 2068 * This function is used to program the context that's used for exception 2069 * return. This initializes the SP_EL3 to a pointer to a 'cpu_context' set for 2070 * the required security state 2071 ******************************************************************************/ 2072 void cm_set_next_eret_context(uint32_t security_state) 2073 { 2074 cpu_context_t *ctx; 2075 2076 ctx = cm_get_context(security_state); 2077 assert(ctx != NULL); 2078 2079 cm_set_next_context(ctx); 2080 } 2081