1 /* 2 * Copyright (c) 2018-2020, Arm Limited and Contributors. All rights reserved. 3 * Copyright (c) 2021-2022, Xilinx, Inc. All rights reserved. 4 * Copyright (c) 2022-2025, Advanced Micro Devices, Inc. All rights reserved. 5 * 6 * SPDX-License-Identifier: BSD-3-Clause 7 */ 8 9 #ifndef PLATFORM_DEF_H 10 #define PLATFORM_DEF_H 11 12 #include <arch.h> 13 #include "def.h" 14 15 /******************************************************************************* 16 * Generic platform constants 17 ******************************************************************************/ 18 19 /* Size of cacheable stacks */ 20 #define PLATFORM_STACK_SIZE U(0x440) 21 22 #define PLATFORM_CLUSTER_COUNT U(4) 23 #define PLATFORM_CORE_COUNT_PER_CLUSTER U(2) /* 2 CPUs per cluster */ 24 25 #define PLATFORM_CORE_COUNT (PLATFORM_CLUSTER_COUNT * PLATFORM_CORE_COUNT_PER_CLUSTER) 26 27 #define E_INVALID_CORE_COUNT -1 28 #define E_INVALID_CLUSTER_COUNT -3 29 30 #define PLAT_MAX_PWR_LVL U(2) 31 #define PLAT_MAX_RET_STATE U(1) 32 #define PLAT_MAX_OFF_STATE U(2) 33 34 /******************************************************************************* 35 * BL31 specific defines. 36 ******************************************************************************/ 37 /* 38 * Put BL31 at the top of the Trusted SRAM (just below the shared memory, if 39 * present). BL31_BASE is calculated using the current BL31 debug size plus a 40 * little space for growth. 41 */ 42 #ifndef MEM_BASE 43 # define BL31_BASE U(0xBBF00000) 44 # define BL31_LIMIT U(0xBC000000) 45 #else 46 # define BL31_BASE U(MEM_BASE) 47 # define BL31_LIMIT U(MEM_BASE + MEM_SIZE) 48 # ifdef MEM_PROGBITS_SIZE 49 # define BL31_PROGBITS_LIMIT U(MEM_BASE + \ 50 MEM_PROGBITS_SIZE) 51 # endif 52 #endif 53 54 /******************************************************************************* 55 * BL32 specific defines. 56 ******************************************************************************/ 57 #ifndef BL32_MEM_BASE 58 # define BL32_BASE U(0x01800000) 59 # define BL32_LIMIT U(0x09800000) 60 #else 61 # define BL32_BASE U(BL32_MEM_BASE) 62 # define BL32_LIMIT U(BL32_MEM_BASE + BL32_MEM_SIZE) 63 #endif 64 65 /******************************************************************************* 66 * BL33 specific defines. 67 ******************************************************************************/ 68 #ifndef PRELOADED_BL33_BASE 69 # define PLAT_ARM_NS_IMAGE_BASE U(0x40000000) 70 #else 71 # define PLAT_ARM_NS_IMAGE_BASE U(PRELOADED_BL33_BASE) 72 #endif 73 74 /******************************************************************************* 75 * TSP specific defines. 76 ******************************************************************************/ 77 #define TSP_SEC_MEM_BASE BL32_BASE 78 #define TSP_SEC_MEM_SIZE (BL32_LIMIT - BL32_BASE) 79 80 /* ID of the secure physical generic timer interrupt used by the TSP */ 81 #define ARM_IRQ_SEC_PHY_TIMER U(29) 82 #define TSP_IRQ_SEC_PHY_TIMER ARM_IRQ_SEC_PHY_TIMER 83 84 /******************************************************************************* 85 * Platform specific page table and MMU setup constants 86 ******************************************************************************/ 87 #define PLAT_DDR_LOWMEM_MAX U(0x80000000) 88 89 #define PLAT_PHY_ADDR_SPACE_SIZE (1ULL << 32U) 90 #define PLAT_VIRT_ADDR_SPACE_SIZE (1ULL << 32U) 91 92 #define XILINX_OF_BOARD_DTB_MAX_SIZE U(0x200000) 93 94 #define PLAT_OCM_BASE U(0xBBF00000) 95 #define PLAT_OCM_LIMIT U(0xBC000000) 96 97 #if TRANSFER_LIST 98 /* 99 * FIXME: This address should come from firmware before TF-A 100 * Having this to make sure the transfer list functionality works 101 */ 102 #define FW_HANDOFF_BASE U(0x1000000) 103 #define FW_HANDOFF_SIZE U(0x600000) 104 #endif 105 106 #define IS_TFA_IN_OCM(x) ((x >= PLAT_OCM_BASE) && (x < PLAT_OCM_LIMIT)) 107 108 #ifndef MAX_MMAP_REGIONS 109 #if (defined(XILINX_OF_BOARD_DTB_ADDR) && !IS_TFA_IN_OCM(BL31_BASE)) 110 #define MAX_MMAP_REGIONS 11 111 #else 112 #define MAX_MMAP_REGIONS 10 113 #endif 114 #endif 115 116 #ifndef MAX_XLAT_TABLES 117 #define MAX_XLAT_TABLES U(12) 118 #endif 119 120 #define CACHE_WRITEBACK_SHIFT U(6) 121 #define CACHE_WRITEBACK_GRANULE (1 << CACHE_WRITEBACK_SHIFT) 122 123 #define PLAT_GICD_BASE_VALUE U(0xE2000000) 124 #define PLAT_GICR_BASE_VALUE U(0xE2060000) 125 126 /* 127 * Define a list of Group 1 Secure and Group 0 interrupts as per GICv3 128 * terminology. On a GICv2 system or mode, the lists will be merged and treated 129 * as Group 0 interrupts. 130 */ 131 #define PLAT_IPI_IRQ 89 132 #define PLAT_VERSAL_IPI_IRQ PLAT_IPI_IRQ 133 134 #define PLAT_G1S_IRQ_PROPS(grp) \ 135 INTR_PROP_DESC(IRQ_SEC_PHY_TIMER, GIC_HIGHEST_SEC_PRIORITY, grp, \ 136 GIC_INTR_CFG_LEVEL) 137 138 #define PLAT_G0_IRQ_PROPS(grp) \ 139 INTR_PROP_DESC(PLAT_VERSAL_IPI_IRQ, GIC_HIGHEST_SEC_PRIORITY, grp, \ 140 GIC_INTR_CFG_EDGE), \ 141 142 #define IRQ_MAX 200U 143 144 #endif /* PLATFORM_DEF_H */ 145